IE801491L - Data transmission - Google Patents

Data transmission

Info

Publication number
IE801491L
IE801491L IE801491A IE149180A IE801491L IE 801491 L IE801491 L IE 801491L IE 801491 A IE801491 A IE 801491A IE 149180 A IE149180 A IE 149180A IE 801491 L IE801491 L IE 801491L
Authority
IE
Ireland
Prior art keywords
logic
signal
output
toggle
state
Prior art date
Application number
IE801491A
Other versions
IE50068B1 (en
Original Assignee
Plessey Co Plc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Plc filed Critical Plessey Co Plc
Publication of IE801491L publication Critical patent/IE801491L/en
Publication of IE50068B1 publication Critical patent/IE50068B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H04L1/0063—Single parity check

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

The method is used where a data input/output mechanism is protected by a parity bit and is controlled by a signal whose state determines when a transfer is in progress. Data and a parity bit is presented from a controller to a parity checker P1 the output of which is a logic '1' signal if corruption has not occurred. A "Request" signal is provided via a delay line DE1 producing a positive-going clock signal for a first toggle T1 which presents a logic '0' to the clock input of a second toggle F1 providing a non-alarm signal output. If the output of the checker P1 remains in a logic '1' state when the "Request" signal goes to the logic "0" state the logic '1' is clocked into the first toggle T1 causing the output of the second toggle F1 to change state and indicate an alarm condition. A "Routine" signal is provided by the controller which is gated with the parity bit to provide a check on the output of the first and second toggles to ensure that they are not held in the logic '0' state. <IMAGE> [GB2054326A]
IE1491/80A 1979-07-18 1980-07-17 Method of routining parity checking circuits IE50068B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB7925090A GB2054326B (en) 1979-07-18 1979-07-18 Method of routining parity checking circuits

Publications (2)

Publication Number Publication Date
IE801491L true IE801491L (en) 1981-01-18
IE50068B1 IE50068B1 (en) 1986-02-05

Family

ID=10506592

Family Applications (1)

Application Number Title Priority Date Filing Date
IE1491/80A IE50068B1 (en) 1979-07-18 1980-07-17 Method of routining parity checking circuits

Country Status (6)

Country Link
BR (1) BR8004152A (en)
GB (1) GB2054326B (en)
IE (1) IE50068B1 (en)
NZ (1) NZ193793A (en)
PT (1) PT71448A (en)
ZA (1) ZA802954B (en)

Also Published As

Publication number Publication date
GB2054326A (en) 1981-02-11
PT71448A (en) 1980-07-01
IE50068B1 (en) 1986-02-05
NZ193793A (en) 1983-03-15
BR8004152A (en) 1981-01-21
GB2054326B (en) 1983-10-19
ZA802954B (en) 1981-05-27

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