IE50068B1 - Method of routining parity checking circuits - Google Patents

Abstract

The method is used where a data input/output mechanism is protected by a parity bit and is controlled by a signal whose state determines when a transfer is in progress. Data and a parity bit is presented from a controller to a parity checker P1 the output of which is a logic '1' signal if corruption has not occurred. A "Request" signal is provided via a delay line DE1 producing a positive-going clock signal for a first toggle T1 which presents a logic '0' to the clock input of a second toggle F1 providing a non-alarm signal output. If the output of the checker P1 remains in a logic '1' state when the "Request" signal goes to the logic "0" state the logic '1' is clocked into the first toggle T1 causing the output of the second toggle F1 to change state and indicate an alarm condition. A "Routine" signal is provided by the controller which is gated with the parity bit to provide a check on the output of the first and second toggles to ensure that they are not held in the logic '0' state.

Description

The present invention relates to parity checking arrangements for use in data transmission systems.

In data transmission systems it is common place to insert at the transmitting end of such a system, a parity bit in a data message which is indicative of the odd or even parity of that message. At the receiving end of the data transmission the data bits and parity bit are presented to a parity checking circuit which gives an indication of whether or not the message has been corrupted during transmission.

If a parity checking circuit becomes faulty and its output sticks in a particular state then the mechanism by which the message is checked for corruption could always give an uncorrupted indication.

Therefore, an aim of the present invention is to provide a parity checking arrangement which provides an indication when such arrangement becomes faulty.

According to the present invention there is provided a parity checking - 2 50068 arrangement for use in data transmission systems of the type in which the data is accompanied by a clocking signal, wherein the arrangement includes a parity checker, monitoring means for monitoring the performance of the parity checker and means for generating an alarm signal when the monitoring means detects that the parity checker output has remained in a predetermined faulty state after the removal of the clocking signal.

An embodiment of the invention will be described with reference to the accompanying drawing which shows one method of performing the invention.

A central controller (not shown) provides an eight bit data message D1-D8 and a single parity bit DP. The state of the pariiybit DP is chosen to make an odd number of 1's in the data message D1-D8 and the parity bit DP.

Considering the case when the ROUTINE signal = 0 and the REQUEST signal = 1.

The REQUEST signal provides a clocking signal for the parity checking arrangement. The data bits D1-D8 and parity bit DP from the central controller pass through AND-gates G and are presented to parity checker P1.

If the data has been transmitted and received without corruption the output of parity checker P1 will be at the logic '1' state and the data will be stored in the Data Storage Logic DSL. When the transfer of data D1-D8 is complete the REQUEST signal returns to a logic '0' state, AND-dates G present a bad parity pattern of logic O's to Parity Checker P1, and after a propagation delay through Parity Checker PI a logic '0' state appears at the input D of toggle T1 if Parity Checker PI has functioned correctly. During this period the REQUEST signal has passed through Delay Element DE1 and inverter 11 giving a positive-going edge at the clock input CK of toggle TI after the logic '0' state has settled at input D of toggle T1. The resulting Q output signal from toggle T1 is in the logic '0' state and is applied to the clock input CK of Fault Latch F1. The Q output signal from Fault Latch F1 does not - 3 50068 change state and remains in the logic '0' state, indicating a non-alarm condition which is fed to the Data Storage Logic DSL and the central controller allowing the data to be stored. This sequence continues each time the REQUEST signal is activated and cleared.

If a fault occurs causing the output of Parity Checker Pl to stick in the logic '1' state, indicating non-corrupted transmission of data, independent of its input signals, the data transmission system will be unprotected against data corruption. Under this condition when the REQUEST signal goes to the logic ‘0' state the output of Parity Checker PI will not return to the logic ’0’ state. A logic '1' signal will be clocked into the D input of toggle Ti. The Q output of toggle T1 goes to the logic '1' state and is applied to the clock input CK of Fault Latch F1. The Q output of Fault Latch FI goes to the logic '1' state indicating an alarm condition which is fed back to the Data Storage Logic DSL and the central controller and prevents the data which may be corrupted from being stored. The alarm condition will persist until the RESET ALARM signal is activated and applied to input R of Fault Latch F1 via inverter 12.

The ROUTINE signal is provided to check that the outputs of toggle TI and Fault Latch F1 are not stuck in the logic '0' state. When the ROUTINE signal = 1 set by the central controller during a periodic routining operation, and the REQUEST signal goes to the logic '0' state, good parity signals are applied to Parity Checker P1, because the data parity bit DP is inverted when ROUTINE = 1 by an Invert/Non-invert gate E1. If toggle T1 and Fault Latch F1 are functioning correctly the Alarm signal will set. The application of the Reset Alarm signal and the removal of the ROUTINE signal will set the circuit to its original condition and the continuous routining of the Parity Checker P1 will continue. - 4 50068 The above description has been of one embodiment only and is not intended to limit the scope of the invention. Alternative arrangements will readily be seen by those skilled in the art. For example, a serial input/output system could be used and a serial in/parallel out circuit would replace AND-gates G and the REQUEST signal would be connected to the reset input of the serial in/parallel out circuit.

In either a serial or parallel system the number of data and parity bits and hence the number of parity checkers could be increased. The outputs from the parity checkers would be merged to verify that all had returned to the bad parity state when a data transfer was not in progress.

Claims (5)

1. A parity checking arrangement for use in data transmission systems of the type in which the data is accompanied by a clocking signal, wherein the arrangement includes a parity checker, monitoring means for monitoring the performance of the parity checker, and means for generating an alarm signal when the monitoring means detects that the parity checker output has remained in a predetermined faulty state after the removal of the clocking signal.

2. A parity checking arrangement according to Claim 1 wherein the monitoring means is a toggle which has the clocking signal applied to its clock input by way of a delay device.

3. A parity checking arrangement according to Claim 1 and 2 wherein the means for generating the alarm signal is a toggle arranged to operate as a latch and is clocked by the output of the toggle which monitors the parity checker. - 5 50068

4. A parity checking arrangement as claimed in Claim 3 wherein the toggle and latch are checked to ensure that their outputs do not remain in a predetermined state by inverting a data parity bit presented to the parity checker and simulating an alarm generating condition.

5. 5. A parity checking arrangement substantially as described with reference to the accompanying drawing.