JPS57157324A - Data input and output device - Google Patents

Data input and output device

Info

Publication number
JPS57157324A
JPS57157324A JP56041774A JP4177481A JPS57157324A JP S57157324 A JPS57157324 A JP S57157324A JP 56041774 A JP56041774 A JP 56041774A JP 4177481 A JP4177481 A JP 4177481A JP S57157324 A JPS57157324 A JP S57157324A
Authority
JP
Japan
Prior art keywords
computer
data bus
input
internal
request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56041774A
Other languages
Japanese (ja)
Inventor
Yoshimori Obata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56041774A priority Critical patent/JPS57157324A/en
Publication of JPS57157324A publication Critical patent/JPS57157324A/en
Pending legal-status Critical Current

Links

Landscapes

  • Input From Keyboards Or The Like (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To prevent the effect on an input and output operation even with a failure in a display circuit, by connecting the display circuit to an internal data bus splitting a part of the data bus of a computer.
CONSTITUTION: An internal data bus splitting a data bus of a computer is provided in an input and output device IOD, and when no input and output request is given by the computer to the IOD, a gate signal (a) or (c) is outputted from a control circuit with a display selection signal set with a display changeover switch, internal input data ID0WIDn or internal latch data OD0WODn are outputted to the internal data bus through a bus driver. On the other hand, if a request is given from the computer, the request of the computer side has the priority, the display on the present internal data bus is stopped, control signals (a)W(e) are operated through the request of the computer side, allowing to input and output the data with the computer.
COPYRIGHT: (C)1982,JPO&Japio
JP56041774A 1981-03-24 1981-03-24 Data input and output device Pending JPS57157324A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56041774A JPS57157324A (en) 1981-03-24 1981-03-24 Data input and output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56041774A JPS57157324A (en) 1981-03-24 1981-03-24 Data input and output device

Publications (1)

Publication Number Publication Date
JPS57157324A true JPS57157324A (en) 1982-09-28

Family

ID=12617720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56041774A Pending JPS57157324A (en) 1981-03-24 1981-03-24 Data input and output device

Country Status (1)

Country Link
JP (1) JPS57157324A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988010465A1 (en) * 1987-06-19 1988-12-29 Fanuc Ltd Signal output device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988010465A1 (en) * 1987-06-19 1988-12-29 Fanuc Ltd Signal output device
US5097438A (en) * 1987-06-19 1992-03-17 Fanuc, Ltd. Dynamic electric signal output circuit

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