HK61976A - Electronic timepiece - Google Patents

Abstract

1401776 Electronic timepieces SUWA SEIKOSHA K K 7 Sept 1972 [8 Sept 1971 9 Sept 1971 10 Sept 1971] 41582/72 Heading G3T A wholly electronic timepiece (e.g. a watch) having liquid crystal or light-emitting diode digital display, is provided with not more than two manually operable members (coupled to mechanical switches) for selecting part of the time indication to be corrected and resetting to zero or correcting the selected parts of the time indication individually. The switches may additionally be arranged for simultaneously resetting all of the parts of the time indication to zero. In an embodiment Fig. 9, a frequency divider DIV feeds signals at 1Hz to divider counters 1' to 5' for operating the hours, tens of minutes, minutes, tens of seconds and seconds respectively of the time display 7' in known manner. When setting, a signal applied at terminal S-R is passed by a switch Ss to a rotary selector switch So' detailed in Figs. 10 to 14 (not shown) and comprising an axially movable rotatable stem. With the selector wiper engaging a contact Sr the signal will reset all of the counters 1' to 5' and all of the parts of the time display to zero. With the wiper at a contact Sa, the hours and tens of minutes will be zeroed. Similarly the minutes will be zeroed with the wiper at contact S13 and so on. If the switch Ss is now opened and closed periodically, the appropriate part or parts of the time display can be advanced to the correct time. Fast correction of the time can be achieved by applying the output of the divider DIV selectively to the minutes and second counters Fig. 18 (not shown). In an arrangement to prevent overshoot when correcting the displayed time, Fig. 19 (not shown) a desired time indication is read into the timepiece and is continuously compared with the actual indication being corrected. Thus as shown in Fig. 20, each counter of Fig. 19 comprises two sets of binary flip-flops A, B, C, D and a, b, c, d, each set constituting a <SP>1</SP>/ 10 sub-dividing circuit X, Y respectively. For example if the desired 1-seconds indication is "5" then a setting signal is applied to terminal Sb" which sets the subcircuit flip-flops a, b, c, d for 0, 1, 0, 1. A correcting signal is then applied at Sc" and is fed to flipflops ABCD via a gate GY. When the outputs of ABCD coincide with the outputs of a, b, c, d respectively, the outputs of gates Ga to Gd and hence of gate Gw, go to "high". The output of Gw together with a control singal at Sa" make gate Gx output go high. Thus a gate Gz is caused to block correcting signals to ABCD sub-circuit and overshoot is prevented. The divider counter circuits 2', 3', 4', 5' are constructed in like manner to that of 1', in Fig. 20.