HK14485A - Shadow masking process for forming source and drain regions for field-effect transistors and like regions - Google Patents

Shadow masking process for forming source and drain regions for field-effect transistors and like regions

Info

Publication number
HK14485A
HK14485A HK144/85A HK14485A HK14485A HK 14485 A HK14485 A HK 14485A HK 144/85 A HK144/85 A HK 144/85A HK 14485 A HK14485 A HK 14485A HK 14485 A HK14485 A HK 14485A
Authority
HK
Hong Kong
Prior art keywords
regions
field
effect transistors
forming source
masking process
Prior art date
Application number
HK144/85A
Other languages
English (en)
Inventor
Robert M Jecmen
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK14485A publication Critical patent/HK14485A/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/143—Shadow masking

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
HK144/85A 1979-02-05 1985-02-28 Shadow masking process for forming source and drain regions for field-effect transistors and like regions HK14485A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/009,303 US4198250A (en) 1979-02-05 1979-02-05 Shadow masking process for forming source and drain regions for field-effect transistors and like regions

Publications (1)

Publication Number Publication Date
HK14485A true HK14485A (en) 1985-03-08

Family

ID=21736824

Family Applications (1)

Application Number Title Priority Date Filing Date
HK144/85A HK14485A (en) 1979-02-05 1985-02-28 Shadow masking process for forming source and drain regions for field-effect transistors and like regions

Country Status (6)

Country Link
US (1) US4198250A (xx)
JP (1) JPS55107268A (xx)
DE (1) DE3000847A1 (xx)
GB (1) GB2041644B (xx)
HK (1) HK14485A (xx)
SG (1) SG60784G (xx)

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US4330931A (en) * 1981-02-03 1982-05-25 Intel Corporation Process for forming metal plated regions and lines in MOS circuits
US4472874A (en) * 1981-06-10 1984-09-25 Tokyo Shibaura Denki Kabushiki Kaisha Method of forming planar isolation regions having field inversion regions
US4394182A (en) * 1981-10-14 1983-07-19 Rockwell International Corporation Microelectronic shadow masking process for reducing punchthrough
US4599118A (en) * 1981-12-30 1986-07-08 Mostek Corporation Method of making MOSFET by multiple implantations followed by a diffusion step
USRE32800E (en) * 1981-12-30 1988-12-13 Sgs-Thomson Microelectronics, Inc. Method of making mosfet by multiple implantations followed by a diffusion step
DE3279662D1 (en) * 1981-12-30 1989-06-01 Thomson Components Mostek Corp Triple diffused short channel device structure
US4474623A (en) * 1982-04-26 1984-10-02 Raytheon Company Method of passivating a semiconductor body
JPS5933880A (ja) * 1982-08-19 1984-02-23 Nec Corp 半導体装置の製造方法
KR930007195B1 (ko) * 1984-05-23 1993-07-31 가부시끼가이샤 히다찌세이사꾸쇼 반도체 장치와 그 제조 방법
US5352620A (en) * 1984-05-23 1994-10-04 Hitachi, Ltd. Method of making semiconductor device with memory cells and peripheral transistors
DE3426421A1 (de) * 1984-07-18 1986-01-23 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum herstellen einer halbleiteranordnung
IT1214805B (it) * 1984-08-21 1990-01-18 Ates Componenti Elettron Spositivi a semiconduttore con giunprocesso per la fabbricazione di dizioni planari a concentrazione di carica variabile e ad altissima tensione di breakdown
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US4703551A (en) * 1986-01-24 1987-11-03 Ncr Corporation Process for forming LDD MOS/CMOS structures
US4682404A (en) * 1986-10-23 1987-07-28 Ncr Corporation MOSFET process using implantation through silicon
US4728617A (en) * 1986-11-04 1988-03-01 Intel Corporation Method of fabricating a MOSFET with graded source and drain regions
US4784965A (en) * 1986-11-04 1988-11-15 Intel Corporation Source drain doping technique
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US4933994A (en) * 1987-06-11 1990-06-19 General Electric Company Method for fabricating a self-aligned lightly doped drain semiconductor device with silicide
US4818714A (en) * 1987-12-02 1989-04-04 Advanced Micro Devices, Inc. Method of making a high performance MOS device having LDD regions with graded junctions
US5015595A (en) * 1988-09-09 1991-05-14 Advanced Micro Devices, Inc. Method of making a high performance MOS device having both P- and N-LDD regions using single photoresist mask
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US5227321A (en) * 1990-07-05 1993-07-13 Micron Technology, Inc. Method for forming MOS transistors
US5023190A (en) * 1990-08-03 1991-06-11 Micron Technology, Inc. CMOS processes
US5219782A (en) * 1992-03-30 1993-06-15 Texas Instruments Incorporated Sublithographic antifuse method for manufacturing
EP0607658A3 (en) * 1992-11-13 1995-08-30 At & T Corp Manufacturing of a MOSFET.
US5472895A (en) * 1993-12-27 1995-12-05 Hyundai Electronics Industries Co., Ltd. Method for manufacturing a transistor of a semiconductor device
JP3008154B2 (ja) * 1994-12-19 2000-02-14 セイコーインスツルメンツ株式会社 半導体装置の製造方法
KR960042942A (ko) * 1995-05-04 1996-12-21 빈센트 비.인그라시아 반도체 디바이스 형성 방법
US5650343A (en) * 1995-06-07 1997-07-22 Advanced Micro Devices, Inc. Self-aligned implant energy modulation for shallow source drain extension formation
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US7332439B2 (en) * 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
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US8541296B2 (en) * 2011-09-01 2013-09-24 The Institute of Microelectronics Chinese Academy of Science Method of manufacturing dummy gates in gate last process
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Also Published As

Publication number Publication date
US4198250A (en) 1980-04-15
DE3000847A1 (de) 1980-08-07
JPS55107268A (en) 1980-08-16
GB2041644B (en) 1983-05-11
GB2041644A (en) 1980-09-10
SG60784G (en) 1985-03-15

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