HK1001575A1 - Multi-layer lead frame for a semiconductor device - Google Patents

Multi-layer lead frame for a semiconductor device

Info

Publication number
HK1001575A1
HK1001575A1 HK98100452A HK98100452A HK1001575A1 HK 1001575 A1 HK1001575 A1 HK 1001575A1 HK 98100452 A HK98100452 A HK 98100452A HK 98100452 A HK98100452 A HK 98100452A HK 1001575 A1 HK1001575 A1 HK 1001575A1
Authority
HK
Hong Kong
Prior art keywords
semiconductor device
lead frame
layer lead
layer
frame
Prior art date
Application number
HK98100452A
Other languages
English (en)
Inventor
Mitsuharu Shimizu
Yoshiki Takeda
Hirofumi Fujii
Original Assignee
Shinko Electric Ind Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Ind Co filed Critical Shinko Electric Ind Co
Publication of HK1001575A1 publication Critical patent/HK1001575A1/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49527—Additional leads the additional leads being a multilayer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H01L2924/30111—Impedance matching

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
HK98100452A 1990-09-04 1998-01-20 Multi-layer lead frame for a semiconductor device HK1001575A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2235067A JP2966067B2 (ja) 1990-09-04 1990-09-04 多層リードフレーム

Publications (1)

Publication Number Publication Date
HK1001575A1 true HK1001575A1 (en) 1998-06-26

Family

ID=16980581

Family Applications (1)

Application Number Title Priority Date Filing Date
HK98100452A HK1001575A1 (en) 1990-09-04 1998-01-20 Multi-layer lead frame for a semiconductor device

Country Status (6)

Country Link
US (1) US5235209A (fr)
EP (1) EP0474469B1 (fr)
JP (1) JP2966067B2 (fr)
KR (1) KR950001369B1 (fr)
DE (1) DE69125072T2 (fr)
HK (1) HK1001575A1 (fr)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2108542A1 (fr) * 1992-02-18 1993-08-19 Bidyut K. Bhattacharyya Procede mesique de fabrication de boitiers ci moules en plastique multicouche
JPH0653277A (ja) * 1992-06-04 1994-02-25 Lsi Logic Corp 半導体装置アセンブリおよびその組立方法
US5854094A (en) * 1992-07-28 1998-12-29 Shinko Electric Industries Co., Ltd. Process for manufacturing metal plane support for multi-layer lead frames
US5777265A (en) * 1993-01-21 1998-07-07 Intel Corporation Multilayer molded plastic package design
JP2931741B2 (ja) * 1993-09-24 1999-08-09 株式会社東芝 半導体装置
US5343074A (en) * 1993-10-04 1994-08-30 Motorola, Inc. Semiconductor device having voltage distribution ring(s) and method for making the same
US5578869A (en) * 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
JP2536459B2 (ja) * 1994-09-26 1996-09-18 日本電気株式会社 半導体装置及びその製造方法
GB2293918A (en) * 1994-10-06 1996-04-10 Ibm Electronic circuit packaging
US5965936A (en) * 1997-12-31 1999-10-12 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
AU4152096A (en) * 1994-11-10 1996-06-06 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
US5818114A (en) * 1995-05-26 1998-10-06 Hewlett-Packard Company Radially staggered bond pad arrangements for integrated circuit pad circuitry
GB9515651D0 (en) * 1995-07-31 1995-09-27 Sgs Thomson Microelectronics A method of manufacturing a ball grid array package
US6054754A (en) 1997-06-06 2000-04-25 Micron Technology, Inc. Multi-capacitance lead frame decoupling device
US6515359B1 (en) * 1998-01-20 2003-02-04 Micron Technology, Inc. Lead frame decoupling capacitor semiconductor device packages including the same and methods
US6114756A (en) 1998-04-01 2000-09-05 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit leadframes
US6414386B1 (en) * 2000-03-20 2002-07-02 International Business Machines Corporation Method to reduce number of wire-bond loop heights versus the total quantity of power and signal rings
KR20030066994A (ko) * 2002-02-06 2003-08-14 주식회사 칩팩코리아 다층 리드프레임 및 이를 이용한 칩 사이즈 패키지
US8354743B2 (en) * 2010-01-27 2013-01-15 Honeywell International Inc. Multi-tiered integrated circuit package
US9741644B2 (en) 2015-05-04 2017-08-22 Honeywell International Inc. Stacking arrangement for integration of multiple integrated circuits

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61108160A (ja) * 1984-11-01 1986-05-26 Nec Corp コンデンサ内蔵型半導体装置及びその製造方法
GB2174538A (en) * 1985-04-24 1986-11-05 Stanley Bracey Semiconductor package
JP2734463B2 (ja) * 1989-04-27 1998-03-30 株式会社日立製作所 半導体装置
JP2744685B2 (ja) * 1990-08-08 1998-04-28 三菱電機株式会社 半導体装置

Also Published As

Publication number Publication date
DE69125072D1 (de) 1997-04-17
KR920007164A (ko) 1992-04-28
EP0474469B1 (fr) 1997-03-12
US5235209A (en) 1993-08-10
EP0474469A1 (fr) 1992-03-11
JP2966067B2 (ja) 1999-10-25
JPH04114461A (ja) 1992-04-15
DE69125072T2 (de) 1997-06-19
KR950001369B1 (ko) 1995-02-17

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Legal Events

Date Code Title Description
PF Patent in force
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20100904