GB2337026A - Plasma etching silicon nitride using tetrafluoromethane, argon and nitrogen - Google Patents
Plasma etching silicon nitride using tetrafluoromethane, argon and nitrogen Download PDFInfo
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- GB2337026A GB2337026A GB9809769A GB9809769A GB2337026A GB 2337026 A GB2337026 A GB 2337026A GB 9809769 A GB9809769 A GB 9809769A GB 9809769 A GB9809769 A GB 9809769A GB 2337026 A GB2337026 A GB 2337026A
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- silicon nitride
- nitride layer
- argon
- methane
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- 229910052581 Si3N4 Inorganic materials 0.000 title abstract description 73
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 title abstract description 73
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 title abstract description 50
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 title abstract description 43
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 title abstract description 27
- 229910052786 argon Inorganic materials 0.000 title abstract description 25
- 238000001020 plasma etching Methods 0.000 title abstract description 15
- 229910052757 nitrogen Inorganic materials 0.000 title description 21
- 238000000034 method Methods 0.000 abstract description 41
- 239000000758 substrate Substances 0.000 abstract description 24
- 239000004065 semiconductor Substances 0.000 abstract description 21
- 238000002955 isolation Methods 0.000 abstract description 15
- 229910052751 metal Inorganic materials 0.000 abstract description 11
- 239000002184 metal Substances 0.000 abstract description 11
- 239000000203 mixture Substances 0.000 abstract description 9
- 229910021332 silicide Inorganic materials 0.000 abstract description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 7
- 230000000873 masking effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 24
- 229920000642 polymer Polymers 0.000 description 22
- 239000000463 material Substances 0.000 description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 239000002245 particle Substances 0.000 description 14
- 230000015572 biosynthetic process Effects 0.000 description 11
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 4
- 241000206607 Porphyra umbilicalis Species 0.000 description 4
- 239000012774 insulation material Substances 0.000 description 4
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Natural products C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 101100393235 Caenorhabditis elegans gon-1 gene Proteins 0.000 description 1
- -1 argaon Chemical compound 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Inorganic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Drying Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A silicon nitride layer 401 on a semiconductor substrate 400 with a photo-resist masking layer 402 is removed by anisotropic plasma etching using a mixture of tetrafluoromethane (CF 4 ), argon (Ar) and nitrogen (N 2 ). The method can be used for shallow trench isolation and for fabricating a poly-gate where the silicon nitride layer is formed on a metal silicide layer.
Description
1 METHOD OF EMUNG SELICON NITRIDE
Field of the Invention
BACKGROL-1\X OF THE INVENTION 2337026 The invention relates to an etching method in an integrated circuit (IC), and more par-ticularly to a method of etching the cap silicon nitride layer (Cap- Si'l',4) on a poly ni 1 1 1 si icon crate or a mask silicon itride layer for fabricating a shallow trench isolation (STI), so that the bias of the critical dimension (CD) is improved.
io Description of the Related Art
Refeming to Fig. 1, a conventional poly-silicon gate is shown. On a semiconductor substrate 100, a poly-gate comprises a crate oxide layer 10 1, a poly-sillcon layer 101, a metal silicide laver 103, for example, a tungsten silicide (WSi) due to the very poor conductivity of poly-silicon, and a cap silicon nitride laver 104. The cap silicon 'de la 1 i itri ver 104 is formed to prevent 'the damage of the poly-gate in the subsequent process, for example, damage caused during the formation of a sourceldrain recrion or self-alianed window, In addition, with the formation of the cap silicon nitride layer, the necking effect caused by subsequent exposure process during photo litho araphy is 0 0 0 prevented. In a conventional process of patterning the silicon nitride layer, a silicon 0 layer is formed first. Using a photo-mask, a photo-resist layer is formed on the nitri silicon nitride layer. The exposed silicon nitride layer is then removed by anisotropic plasma etching. In the conventional method, fluoromethane polymer (CF.J are in use, 0 for example, tri-fluo ro- methane (C1U3)/tetra-fluoro -methane (CF4)/araon(Ar). The flow rate of the triflu oro- methane and the tetra-fluoro-methane are about 'J0sccm to 2 70sccm, and the flow rate of the argon is about 400sccin to 800sccm. Since the particle 0 of fluoro-methane polymer is very large, the etched surface is very rough and ragged.
W WC> Therefore, a large CD bias is produced. In the subsequent process, for example, in the W subsequent p hoto- litho grap hy, a serious nuisalignment or an error during exposure is e'ly caused due to a large CD bias, so that the device reliability is decreased, and the asi c production quality is degraded.
On the other hand, while formina a shallow trench isolation, a similar problem occurs. Referrina to F1.. 2a, on a semiconductor substrate 200, a mask silicon nitride layer 201 is formed. A photo-resist layer 202 is formed on the mask silicon nitnide layer io 201. Using photo-lithography and etching, the photo-resist layer 202 is defined as shown as 202a in Fig. ?a.
Referring to Fig. 2b, using anisotropic plasma etching, the exposed silicon nitride layer 201. In the conventional method, fluoro-methane polymer (CF.,) are in use, for example, tn'-fiuoro-methane (CH13)/tetratluoro-methane (CFt)/areon(Ar). The flow rate of the tri-fluoro-methane and the tetra-fluoro-methane are about 30secm to 70sccm, and the flow rate of the arcron is about 400sccm to 800sccm. Since the particle of Z fluoro-methane polymer is very large, the etched surface is very rough and ragged. Therefore, a larae CD bias is produced. The resultant silicon nitnide layer 20 1 a is shown as figure. In addition, during etching, a fluonide layer is formed. The formation of the 20 fluoride cause the difficulty of ftornuing a gate oxide layer in the subsequent process. Usina a conventional method, a part of the semiconductor substrate 200 is removed, so that a trench is formed within the substrate 200. By filling the trench with an insulated material, for example, an oxide, an shallow trench isolation is formed.
3 SUi'vIARY OF THE INVENTION It is therefore an object of the invention to provide a method of etching a sili g i icon 'de layer. Using difFerent etching reactive material, the CD bias is decreased.
Utri Consequently, the reliability of devices is enhanced, and the production quality is improved.
It is therefore another object of the invention to provide a method of etching a s itride layer.Using different etching reactive material, the silicon nitride layer i 11 ni 1 1 1 1 1 is gate oxide layer is ethced with the formation of a fluoride layer, so that the formation of a affected.
1 z 1 It is a further object of the invention to provide a method of etching a silicon n'de layer. Du 'rig the formation of a cap silicon nitride layer on a poly-gate, a thin itn n 1 1 0 polymer layer is formed on the cap silicon nitride layer simultaneously. The height of the polv-aate is increas1-d, so that an intlerconneci, flor example, a metal plug, is formed with a larger depth in the subsequent metal-lization process. With a larcer depth, the su.-face area is increased, and therefore, the capacitanc-- of the intercorunect is increased.
Consequently, a higher operation speed is obtained.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of etching a silicon nitride layer. On a sen-dconductor substrate having a silicon nitride layer and a photo-resist layer on the silicon nitride layer formed thereon, the silicon nitride layer is removed by anisotropic plasma etching with the photo-resist layer as a mask. A mixture of tetra-fluoro-methane, argon, and nitrogen is used as an etching reactive material. The tetrafluoro-methane with a flowing rate of about 40sccm to 80sccm is functioned to removed the exposed silicon nitride layer. The argon with a 4 flowina rate of about 400sccm to 800 sccm is used for particle bombardment. The rutrogen with a flowing rate of about 20sccm to 60sccm is to form a thin and hard polymer layer on the silicon nitride layer.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of fabricating a poly-gate. A semiconductor substrate having a gate oxide layer, a poly-silicon layer on the gate oxide layer, a metal silicide layer on the poly-silicon layer, a silicon nitride layer on the poly-silicon layer, and a photo-resist layer covering a W part of the silicon nitride layer is provided. Using aruisotropic plasma etching, the io exposed silicon nitride layer is removed. A nuixture of tetra-fluoro-methane, argon, and nitrogen is used as an etching reactive material. The tetra-fluoro-methane with a flowing rate of about 40sccm to 80sccm is functioned to removed the exposed silicon 'de layer. The argon with a flowing rate of about 400scern to 800 sccm is used for utn particle bombardment. The nitrogen with a rate of about 20sccm to 60s-1cm is o fom, a thin and hard polymer layer on the silicon I'llitride layer.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of fabricatina a shallow trench isolation. A semiconductor substrate havina a silicon nitride thereon and a photo-resist layer covering a part of the silicon ruitride layer is provided. The exposed silicon nitride layer is removed by anisotropic plasma etching until the semiconductor substrate is exposed. A mixture of tetra-fluoro-methane, argon, and nitrogen is used as an etching reactive material. The tetra-fluoro-methane with a flowing rate of about 40sccm to 80seem is functioned to removed the exposed silicon nitride layer. The argon with a flowing rate of about 400scem to 800 sccm is used for 0 c particle bombardment. The nitrogen with a flowing rate of about 20sccm to 60sccm is 0 0 to form a thin and hard polymer layer on the silicon nitride layer- The photo-resist layer is removed. A part of the exposed senuiconductor substrate is removed to form a trench. The trench is filled with an insulation material.
It is to be understood that both the forecoinz aeneral description and the followin. detailed description are exemplary and explanatory only And are not restrictive of the invention, as claimed.
BRIEF DESCRIPTION OF THEE DRAWrNGS
Fia -ate; igure 1 shows a conventional fabricating process of a poly Figure 2a to Figure 2b show a conventional method of fabricatine, a shallow trench isolation; Figure 3a to Figure 3b show a inethod of fabricating a poly-gate in a preferred embodiment accordina to the invention; and Figure 4a to Figure 4c show a method of fabricating a shallow trench isolation in a preferred embodiment according to the invention.
0 6 DESCRIPTION OF TEE PREFERRED EN1BODUVIENTS
In Fig. 3a to Fig.3jb, a method of fabricatina a poly-gate in the first preferred embodiment according to the invention is shown.
io Referrina to Fig. 3a, a semiconductor substrate 300 havina a isolation structure 301, for example, a field oxide layer, a gate oxide layer 302 thereon, a first poly-silicon layer 303 and 303a on the gate oxide layer 302 and the isolation structure 301, respectively, and a metal silicide layer, for example, a tungsten silicide laver, 304 and 304a on the polysilicon layer 303 and 303a, respectively is provided.
Referring Fig. 3jb, over the semiconductor substrate 300, a silicon nitnide layer is formed. A photo-resist layer (not shown) is defined and aligned with the poly-silicon layer 303 and 303-1a on the silicon nitride layer to cover a part of the silicon nitride layer. The exposed silicon nitride layer is removed by anisotropic plasma etching. A mixture of tetra-fluoromethane, argon, and nitrogen:s used as an --tchin,c, reactive material. The tetra-fluornc-me-hane wlzh a t'lowing ra:e of about 40sccm to 80sccm is r-unctioned to removed the exposed silicon nitride layer. The argon with a flowiri-cr rate of about 400sccm to 800 sccm is used for particle bombardment. The nitrogen with a flowing rate of about 20sccm to 60sccm is to form a thin and hard polymer layer on the silicon nitride layer. As shown in the figure, after removing the photo-resist layer, on the metal silicide layer 304 and 304a, a cap silicon nitride layer 305, 305a and a polymer layer 306, 306a are formed sequentially.
By the above etching process, the CD bias 0 silicon nitride layer is effective improved. Moreover, a thin and hard polymer layer is formed on the silicon nitride layer. In the subsequent metallization process for forming an interconnect, for example, a metal plug, the depth of the interconnect is increased, so that the surface area is enlarged.
0 7 Consequently, the capacitance is increased, and the operation speed of the device is enhanced.
In Fig. 4a to Fig. 4c, a method of fabricating a shallow trench isolation in the second embodiment accordina to the invention is shown.
Referrina to Fla. 4a, a semiconductor substrate 400 havine, a silicon nitride layer 401 thereon and a photo-resist layer 402 covering a part of the silicon nitride layer is provided. The semiconductor substrate 400 covered by the exposed silicon nitride layer 401 is a predetermined area for forming a shallow trench isolation.
Referring to Fig. 4b, the exposed silicon nitride layer is removed by anisotropic P CP io plasma etching until the semiconductor substrate is exposed. A rluixture of tetra-fluoro methane, argon, and nitrogen is used as an etching reactive material. The tetra-fluoro methane with a flo,,;inc, rate of about 40sccm to 80sccm is functioned to removed the exposed silicon nitride layer. The argon with a flowing rate of about 400secm. to 800 sccm is used for particle bombardment. The nitrogen with a flowing rate of about 20sccm to 60sccm. is to form a thin and hard polymer layer on the silicon nitride layer.
By the above etchine, reactive material, the formation of a fluoride layer is prevented, so .P that the formation of a gate oxide in the subsequent process is not affected. The photoresist layer 402 is then removed, and the resultant structure is as shown in the figure.
Referring to Fia. 4c, using a conventional method, a part of the exposed semiconductor substrate 400 is removed to form a trench. By filling the trench with an insulation material, for example, oxide, a shallow trench 403 isolation is formed.
It is therefore a characteristic of the invention to provide an etchincr method with a rruxture of tetra-flu o ro -methane, argon, and nitrogen as an etching, reactive material. The tetra-fluoro-methane with a flowing rate of about 40secm. to 80sccm is functioned to c 8 removed the exposed silicon nitride layer. The argon with a flowing rate of about 400sccm to 800 sccm is used for particle bombardment. The nitrogen with a flowing rate of about 20sccm to 60sccm is to form a thin and hard polymer layer on the silicon nitride layer. Using the function of the etching reactive material, the CD bias of the silicon nitride layer Is effectively improved. While fabricating a poly- gate, a thin polymer layer is formed on the cap silicon nitride layer to increase to depth of an interconnect formed subsequently. Thus, the capacitance of the interconnect is increased, and consequently, the operation speed of the device is enhancled. On the other hand, during the formation of a shallow trench isolation, using the etching reactive material in the invention, the formation of a fluoride layer is prevented. Therefore, the formation of a aate oxide layer in the subsequent process is not affected.
Other embodiment of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein, It is Intended that the specification and examples to be considered as exemplary orily, with a true sccpe and spirit of the invention being indicated by the following clanns.
is 9 WHAT IS CLARvIED IS:
1. A method of etching a silicon nitride layer, wherein a semiconductor substrate comprising a silicon nitride layer thereon and a photo-resist layer covering a part of the silicon nitride layer is provided, comprising:
removing the exposed silicon nitride layer by using a mixture of tetrafluoromethane, argon, and nitrogen as an etching reactive material.
2. The method according to claim 1, wherein the exposed silicon nitride layer Is 0 removed by anisotropic plasma etching.
1 The method according to claim 1, wherein:
0 the tetra-fluoro -methane has a flowing rate of about 40sccm to 80sccm; the argon has a flowing rate of about 400sccm to 800sccm; and the nitrogen has a flowing rat.' of about 20sccm to 60sccm.
0 4. The method accordina to claim 3, wherein:
0 the function of the tetra-fluoro-methane is to removed the exposed silicon ruitnide layer; layer.
the function of the argon is for particle bombardment; and 0 the function of the nitrocren is to form a thin polymer layer on the silicon nitride 'i 5. A method of etching a silicon nitride layer, wherein a semiconductor 1:1 substrate comprising a silicon ruitnide layer thereon and a photo-resist layer cove i 0 1 ring a part of the silicon ruitride layer is provided, comprising: removing the exposing silicon nitride layer by using anisotropic plasma etching 1.1 0 C with a mixture of tetra-fluo romethane, argon, and nitrogen as an etchine, reactive material, wherein: the. tetra- flu oro -methane for removing the exposed silicon nitride layer having a flowing rate of about 40sccm to 80sccm; the argon for particle bombardment having a flowing rate of about 400sccm to 800sccm; and the nitrogen forraing a thin polymer layer on the silicon nitride layer havincy a io flowing rate of about 20sccm to 60sccm.
1 6 A method of forming a poly-gate, wherein a semiconductor havina a aate z> 0 0 o'de layer, a polv_si.liconlayer and a metal sillicide layer defined on the gate oxide layer, a X1 1 ilicon 't ide layer oil the metal silicide layer, and a photo-resist!aye.- covering a part of' il rll ri the silicon nitride layer is provided, comprisincl: removing the exposing silicon Witride layer by using with a r-riL'X-LJre of tetrafluoro-methane, argaon, and nitrogen as an etching reactive material; and removinc, the photo-resist layer.
c 7. The method according to claim 6, wherein the exposed silicon nitride layer is removed by ansiotroplc plasma etching, 8. The method according to claim 6, further comphising foming a polymer layer on the silicon nitride layer.
11 9. The method according to claim 6, wherein:
0 the tetra-fluoro-methane has a flowing rate of about 40sccm to 80sccm; the ar-on has a flowine, rate of about 400sccm to 800sccm; and W 0 the nitrogen has a flowing rate of about 20sccm to 60sccm.
10. The method according to claim 9, wherein- the function of the tetra-fluoro-methane is to removed the exposed silicon nitride layer; the function of the are is for particle bombardment; and 1 gon 1 1 the function of the nitrogen is to form a thin polymer layer on the silicon nitride layer.
11. A method of forming a poly-aate, wherein a semiconductor having a gate oxide layer, a poly-silicon layer and a metal silicide layer defined on the crate oxide layer, a ilicon nitride layer on the metal sdicide layer, and a photo-resist lay r co- e s e d= a pan of i5 the silicon nitride layer is provided, comprising:
removing the exposing silicon nitride layer by using anisotropic plasma etching with a mixture of tetra-fluoro-methane, argon, and nitrogen as an etching reactive W material., forming a thin polymer layer on the silicon nitride layer; and removing the photo-resist layer, wherein:
the tetra-fluoro- methane for removing the exposed silicon nitride layer having a flowina rate of about 40sccm to 80sccm.
the argon for particle bombardment having a flowing rate of about 400sccm to 1 '1 800sccm. and 12 the nitro-en forniing a thin polymer layer on the silicon nitride layer having a flowing 1, rate of about 20sccm to 60sccm.
12. A method of forming a shallow trench isolation, wherein a senuiconductor 5 substrate havine, a silicon nitride layer and a photoresist layer covering a par-t of the W s'ficon nitride layer provided, compri i 1 1 1 ising:
removing the exposing silicon Witride layer by using with a mixture of tetra- p W Z fluoro-methane, argon, and nitroaen as an etching reactive material until the semiconductor substrate 'is exposed; removing the photo-resist layer; removing a part of the exposed semiconductor substrate to form a trench; and filling the trench with an insulation material.
13. The method accordina to claim 12, wherein the exposed silicon lmitnide layer is removed by ansiotropic plasma etching 14. The method accordina to claim 12, wherein:
0 the tetra-fluoro-methane has a flowing rate of about 40scem to 80sccm; the araon has a flowina rate of about 400sccm to 800sccm- and the nitroaen has a flowing rate of about 20sccm to 60sccm.
z 15. The method accordin. to claim 14, wherein:
0 the function of the tetra-fluo ro -methane is to removed the exposed silicon nitride layer., 13 the function of the argon is for particle bombardment,, and the function of the nitrogen is to form a thin polymer layer on the silicon nitride layer.
16. A method of formine, a shallow trench wherein a semiconductor substrate having a silicon nitride layer and a photo-resist layer covering a pan of the silicon nitride layer is provided, comprising.
removing the exposing silicon nitride layer by using anisotropic plasma etching with a mixture of tetra-fluo ro- methane, arg rutroeen as an etchincr reactive gon, and material until the semiconductor substrate is exposed; to removing the photo-resist layer; removing a part of the exposed serriconductor substrate to form a trench. and filling the trench with an Insulation material, wherein:
the -etra--3,.uoro-.methane for rernoving L,'-,e ex-,os--.,', slL-c--r 111-.-de laye- h-aving a zo,wng rat.- of about 40scc,-,i to 80sc--m,.
the argon for particle bombardment having a flowing rate of about 400scem to 800sccm; and the ritrogen forming a thin polymer layer on the silicon nitride laver having a flowing rate of about 20sccm to 60sccm.
17. A method of etching a silicon nitride layer, substantially as hereinbefore described with reference to and/or substantially as illustrated in any one of or any combination of Figs. 3a to 4c of the accompanying drawings.
18. A method of forming a poly-gate, substantially as hereinbefore described with reference to and/or substantially as illustrated in any one of or any combination of Figs. 3a to 4c of the accompanying drawings.
0 14 19. A method of forming a shallow trench isolation, substantially as hereinbefore described with reference to and/or substantially as illustrated in any one of or any combination of Figs. 3a to 4c of the accompanying drawings.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9809769A GB2337026B (en) | 1998-03-09 | 1998-05-07 | Method of etching silicon nitride |
| DE19821452A DE19821452B4 (en) | 1998-03-09 | 1998-05-13 | A method of making a shallow trench isolation in a semiconductor substrate |
| NL1009202A NL1009202C2 (en) | 1998-03-09 | 1998-05-19 | Method for etching silicon nitride. |
| JP10139493A JPH11283964A (en) | 1998-03-09 | 1998-05-21 | Etching method of silicon nitride |
| FR9806530A FR2775830B1 (en) | 1998-03-09 | 1998-05-25 | PROCESS FOR ATTACKING SILICON NITRIDE |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW87103397 | 1998-03-09 | ||
| GB9809769A GB2337026B (en) | 1998-03-09 | 1998-05-07 | Method of etching silicon nitride |
| NL1009202A NL1009202C2 (en) | 1998-03-09 | 1998-05-19 | Method for etching silicon nitride. |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9809769D0 GB9809769D0 (en) | 1998-07-08 |
| GB2337026A true GB2337026A (en) | 1999-11-10 |
| GB2337026B GB2337026B (en) | 2000-11-08 |
Family
ID=27269304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9809769A Expired - Fee Related GB2337026B (en) | 1998-03-09 | 1998-05-07 | Method of etching silicon nitride |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH11283964A (en) |
| DE (1) | DE19821452B4 (en) |
| FR (1) | FR2775830B1 (en) |
| GB (1) | GB2337026B (en) |
| NL (1) | NL1009202C2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5719089A (en) * | 1996-06-21 | 1998-02-17 | Vanguard International Semiconductor Corporation | Method for etching polymer-assisted reduced small contacts for ultra large scale integration semiconductor devices |
| US5728619A (en) * | 1996-03-20 | 1998-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective reactive Ion etch (RIE) method for forming a narrow line-width high aspect ratio via through an integrated circuit layer |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4857140A (en) * | 1987-07-16 | 1989-08-15 | Texas Instruments Incorporated | Method for etching silicon nitride |
| US5176790A (en) * | 1991-09-25 | 1993-01-05 | Applied Materials, Inc. | Process for forming a via in an integrated circuit structure by etching through an insulation layer while inhibiting sputtering of underlying metal |
| US5269879A (en) * | 1991-10-16 | 1993-12-14 | Lam Research Corporation | Method of etching vias without sputtering of underlying electrically conductive layer |
| DE4340590A1 (en) * | 1992-12-03 | 1994-06-09 | Hewlett Packard Co | Trench isolation using doped sidewalls |
| US5514247A (en) * | 1994-07-08 | 1996-05-07 | Applied Materials, Inc. | Process for plasma etching of vias |
| US5935877A (en) * | 1995-09-01 | 1999-08-10 | Applied Materials, Inc. | Etch process for forming contacts over titanium silicide |
| US5843847A (en) * | 1996-04-29 | 1998-12-01 | Applied Materials, Inc. | Method for etching dielectric layers with high selectivity and low microloading |
-
1998
- 1998-05-07 GB GB9809769A patent/GB2337026B/en not_active Expired - Fee Related
- 1998-05-13 DE DE19821452A patent/DE19821452B4/en not_active Expired - Fee Related
- 1998-05-19 NL NL1009202A patent/NL1009202C2/en not_active IP Right Cessation
- 1998-05-21 JP JP10139493A patent/JPH11283964A/en active Pending
- 1998-05-25 FR FR9806530A patent/FR2775830B1/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5728619A (en) * | 1996-03-20 | 1998-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective reactive Ion etch (RIE) method for forming a narrow line-width high aspect ratio via through an integrated circuit layer |
| US5719089A (en) * | 1996-06-21 | 1998-02-17 | Vanguard International Semiconductor Corporation | Method for etching polymer-assisted reduced small contacts for ultra large scale integration semiconductor devices |
Also Published As
| Publication number | Publication date |
|---|---|
| NL1009202C2 (en) | 1999-11-22 |
| GB2337026B (en) | 2000-11-08 |
| JPH11283964A (en) | 1999-10-15 |
| FR2775830A1 (en) | 1999-09-10 |
| DE19821452A1 (en) | 1999-09-23 |
| FR2775830B1 (en) | 2002-10-11 |
| DE19821452B4 (en) | 2005-02-17 |
| GB9809769D0 (en) | 1998-07-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20090507 |