FR2775830B1 - PROCESS FOR ATTACKING SILICON NITRIDE - Google Patents

PROCESS FOR ATTACKING SILICON NITRIDE

Info

Publication number
FR2775830B1
FR2775830B1 FR9806530A FR9806530A FR2775830B1 FR 2775830 B1 FR2775830 B1 FR 2775830B1 FR 9806530 A FR9806530 A FR 9806530A FR 9806530 A FR9806530 A FR 9806530A FR 2775830 B1 FR2775830 B1 FR 2775830B1
Authority
FR
France
Prior art keywords
silicon nitride
attacking silicon
attacking
nitride
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9806530A
Other languages
French (fr)
Other versions
FR2775830A1 (en
Inventor
Yi Chun Chang
Ming Sheng Kuo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Publication of FR2775830A1 publication Critical patent/FR2775830A1/en
Application granted granted Critical
Publication of FR2775830B1 publication Critical patent/FR2775830B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
FR9806530A 1998-03-09 1998-05-25 PROCESS FOR ATTACKING SILICON NITRIDE Expired - Fee Related FR2775830B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
TW87103397 1998-03-09
GB9809769A GB2337026B (en) 1998-03-09 1998-05-07 Method of etching silicon nitride
NL1009202A NL1009202C2 (en) 1998-03-09 1998-05-19 Method for etching silicon nitride.

Publications (2)

Publication Number Publication Date
FR2775830A1 FR2775830A1 (en) 1999-09-10
FR2775830B1 true FR2775830B1 (en) 2002-10-11

Family

ID=27269304

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9806530A Expired - Fee Related FR2775830B1 (en) 1998-03-09 1998-05-25 PROCESS FOR ATTACKING SILICON NITRIDE

Country Status (5)

Country Link
JP (1) JPH11283964A (en)
DE (1) DE19821452B4 (en)
FR (1) FR2775830B1 (en)
GB (1) GB2337026B (en)
NL (1) NL1009202C2 (en)

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4857140A (en) * 1987-07-16 1989-08-15 Texas Instruments Incorporated Method for etching silicon nitride
US5176790A (en) * 1991-09-25 1993-01-05 Applied Materials, Inc. Process for forming a via in an integrated circuit structure by etching through an insulation layer while inhibiting sputtering of underlying metal
US5269879A (en) * 1991-10-16 1993-12-14 Lam Research Corporation Method of etching vias without sputtering of underlying electrically conductive layer
DE4340590A1 (en) * 1992-12-03 1994-06-09 Hewlett Packard Co Trench isolation using doped sidewalls
US5514247A (en) * 1994-07-08 1996-05-07 Applied Materials, Inc. Process for plasma etching of vias
US5935877A (en) * 1995-09-01 1999-08-10 Applied Materials, Inc. Etch process for forming contacts over titanium silicide
US5728619A (en) * 1996-03-20 1998-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Selective reactive Ion etch (RIE) method for forming a narrow line-width high aspect ratio via through an integrated circuit layer
US5843847A (en) * 1996-04-29 1998-12-01 Applied Materials, Inc. Method for etching dielectric layers with high selectivity and low microloading
US5719089A (en) * 1996-06-21 1998-02-17 Vanguard International Semiconductor Corporation Method for etching polymer-assisted reduced small contacts for ultra large scale integration semiconductor devices

Also Published As

Publication number Publication date
NL1009202C2 (en) 1999-11-22
JPH11283964A (en) 1999-10-15
GB2337026B (en) 2000-11-08
DE19821452A1 (en) 1999-09-23
GB2337026A (en) 1999-11-10
GB9809769D0 (en) 1998-07-08
DE19821452B4 (en) 2005-02-17
FR2775830A1 (en) 1999-09-10

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20150130