GB2314677A - Polysilicon thin film transistor with silicide and method for fabricating the same - Google Patents

Polysilicon thin film transistor with silicide and method for fabricating the same Download PDF

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Publication number
GB2314677A
GB2314677A GB9712868A GB9712868A GB2314677A GB 2314677 A GB2314677 A GB 2314677A GB 9712868 A GB9712868 A GB 9712868A GB 9712868 A GB9712868 A GB 9712868A GB 2314677 A GB2314677 A GB 2314677A
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layer
polysilicon
silicide
gate insulating
thin film
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GB9712868D0 (en
GB2314677B (en
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Jin Jang
Jeong Ha Lee
Jai Il Ryu
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LG Electronics Inc
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LG Electronics Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT

Abstract

A polysilicon TFT has a gate electrode (14) on an gate insulating film (13) on a polysilicon layer (11) and source/drain electrodes (15) on both sides of the gate insulating film (13). The electrodes (14), (15) are formed of a silicide (12). The fabrication process can thus be simplified, and the production yield as well as device operation reliability can be improved because the gate insulating film (13) and overlying heavily doped semiconductor layer (16) over a channel region are used as an ion injection mask, so obviating the use a stopper of a nitride or oxide film.

Description

2314677 POLYSILICON THIN FILM TRANSISTOR WITH SILICIDE AND METHOD FOR
FABRICATING THE SAME The preserif invention relates to a thin fflm transistor (TFT) and a method for fabricating the same, and more particularly, to a polycrystalline silicon (polysilicon) TFT with I silicide and a method for fabricatina the same.
Among the various metals that can form silicides, refractory metals, such as NIn, Ta, Ti, W, and Cr, and quasi-novel metals, such as Co, Ni, and Pd have been popular. A high quality silicide is simple to form and etch, and has strong chemical bonds. Of these silicide 0 forming metals, a quasi-novel metal forms a silicide at a low temperature (-2000C) in a form of MSi (IM denotps a metal) with more metal than saicon. Particularly, nickel is suitable for the material of a TFT electrode, because nickel siEcide forms a long, thin siEcide layer with little change in thickness throughout its surface, providing a uniform resistance for the nickel siEcide. Moreover, nickel forms a low resistance siEcide when reacting with polysiEcon.
In general, the TFT has been widely used as a pixel electrode driving device in a liquid crystal display (LCD) or as a switching device in an SRAM. The structure of such a TFT can be classified accordin- iguration of an active layer, a semiconductor layer pattern.
to the conf For example, the staggered type has a gate electrode and source/drain electrodes disposed between a semiconductor layer, and a coplanar type has the gate electrode and the source/drain electrodes disposed on one side of the semiconductor layer.
Fig. 3 illustrates a cross-section of a conventional staggered type TFT. The 0 conventional staaaered type TFT includes source/drain electrodes 15 spaced a predeterinined I 2 distance apart on an insulating substrate 10, heavily doped semiconductor layers 16 formed on each of the source/drain electrodes 15, a semiconductor layer 11, serving as a channel, formed on the heavily doped semiconductor layer 16 and the insulating substrate 10 between the heavily doped semiconductor layer 16. A gate insulating Elm 13 is formed on the semiconductor layer 11, and a gate ellectrode 14 is Formed of a coriducrive materlial on a portion of the gate insulating film 13 corresponding to a channel portion of the semiconductor 0 Z layer 11. However, because the heavily doped semiconductor layer 16 is exposed to air, the conventional staggered type TFT has a low Yield.
Fig. 4 illustrates a cross-section of an inverted sta gered type TFT suggested to solve 0 9 cc the aforementioned problem. The inverted staggered type TFT includes a gate electrode 14 =..7 formed on an insulating substrate 10, a gate insulating Elm 13 formed on the entire surface of the above structure, and a semiconductor layer 11 formed on the gate insulating film 13 over the gate electrode.14. Moreover, sourceldrain electrodes 15 are formed in contact with both sides of the semiconductor layer 11, and heavUy doped semiconductor layers 16 are formed at the interface oetween the semiconductor layer 11, and the sourceldrain electrodes 15. Such a TFT structure is applicable to an amorphous silicon TFT.
Fig. 5 Iustrates a cross-section of a conventional coplanar type TFT. The conventional coplanar type TFT includes a semiconductor layer 11, serving as a channel, formed of polysUicon on an insulating substrate 10 an ion stopper 17 formed of a silicon rutride or oxide film on a central portion of the senUconductor layer 11, and heavily doped semiconductor layers 16 formed on the semiconductor layer I I at both sides of the ion stopper 17. Moreover, a gate insulating Elm 13 of silicon oxide or nitride is formed over an entire surface of the resultant structure, portions of which are removed to expose a part of the heavily doped semiconductor layers 16. A gate electrode 14 is formed on the gate Insulating 3 film 13 over the ion stopper 17, and source/drain electrodes 15 are formed on both sides of the gate electrode 14 and in contact With the exposed heavily doped semiconductor layers 16. However, this conventional coplanar type TFT has a problem of low yield because the ion stopper 17 (nitride or oxide) is used as a mask in the separate ion injection process, complicating the fabrication process.
Accordingly, the present invention is directed to a polysilicon thin film transistor with a si.licide and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a polysilicon thin fdm transistor which has little parasitic capacitance.
Another object of the present invention is to provide a method for fabricating a thin film transistor whigh has a simple fabrication process and improve production yield.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent tforn the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the wTitten description and claims hereof as wefl as the aupended, drawiriggs.
According to a first aspect of the present invention, there is provided a polysilicon thin film transistor with a silicide including silicide layers of low parasitic capacitance and sheet resistivity provided in substitution of impurity doped semiconductor layers which serve as contact layers formed by n type ion (for example P ions) doping of a semiconductor layer on a gate insulating film on a portion of a semiconductor layer to be used as a channel formed on an insulating substrate and 4 of the semiconductor layer on both sides of the gate insulating film and deposition of metal layers on the doped semiconductor layers, a gate electrode, and source/drain electrodes.
In another aspect of the present invention, a polysilicon thin film transistor comprises a substrate; a polysilicon layer on the substrate; a gate Insulating layer on the semiconductor layer; a first sflicide acting as a gate electrode on the gate insulating layer-, and second and third silicides acting. as source and drain electrodes, respectively, on the semiconductor layer at respective sides of the first silicide.
In another aspect of the present invention, there Is provided a method for fabricating a fall self-align type pianar polysiEcon thin film transistor, including the steps of forming a gate 0 = C insulating film on a poiysihcon layer on an ir:isulating substrate, forming an amorphous silicon layer on the -ate insulating Elm, selectively removing the amorphous silicon layer and the gate 0 ID C insulating film to leave a portion of each of the amorphous silicon layer and the gate inulating film on a channel region, converting the amorphous silicon layer into a siEcide, converting the polysilicon layer on both sides of the gate ins;ulating film into a sihcide, the polysilicon layer being usea as source/drain, and forming gate and source/drain electrodes of silicide layers.
In another aspect of the present inventiOr4 a method for fabricating a self-align type planar poiysiEcon thin film transistor comprises the steps of forming a polysilicon layer on an insulating substrate; forming a gate insulating film on the polysilicori layer-, forming an amorphous silicon layer on the gate insulating film, selectively removing a portion of the amorphous silicon layer and the gate insulating film so as to leave a portion on a channel region; converting the remaining amorphous silicon layer into a silicide to form a gate electrode; and converting the polysilicon layer at sides of the crate insulating film into a silicide to form source and drain electrodes.
In a further aspect of the present invention, a method for fabricating a self-aiign type planar polysilicon thin film transistor comprises the steps of forming a first semiconductor layer on an insulating substrate; forming a gate insulating film on the semiconductor layer; forming a second semiconductor layer on the gate insulating film; patteming the gate M 0 insulating film and the second semiconductor layer to expose first and second side portions of the first semiconductor layer; ion doping the second semiconductor layer and the first and second side portions of the first semiconductor layer; and forming a silicide layer over the 0ate insulating film and the first and second side portions of the first semiconductor layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
For a better understanding of the invention, an embodiment will now be described by way of example, with reference to the accompanying drawings, in which:
Fig. I illustrates an electron microscopic photograph of a surface of nickel silicide manufactured in accordance with a preferred embodiment of the present invention; Fig 2 illustrates a graph of sheet resistivity versus annealing temperature of nickel silicide formed from nickel deposited on an ion doped amorphous silicon in accordance with a preferred embodiment of the present invention; Fig. 33 is a cross-sectional view of a conventional stac-ered type TFT; Fia. 4 is a cross-sectional view of an inverted staggered type TFT; Fig. 5 is a cross-sectional view of a conventional coplanar type TFT1 0 6 Fig. 6 is a cross-sectional view of a polysilicon TFT with a silicide in accordance with a preferred embodiment of the present invention; Figs. 7A and 7B illustrate the steps for fabricating the polysilicon TFT with a silicide in accordance with a preferred embodiment of the present invention; Figs. 8A and 8B illustrate transition and output characteristics of a laser annealed polysilicon TFT with a silicide in accordance with a prefer-red embodiment of the present invention, respectively; and Figs. 9A_and 9B illustrate transition and output characteristics of a laser annealed polysilicon TFT with a sIcide in accordance with a prefer- red embodiment of the present invention, respectively.
Fig. I illustrates an electron microscopic photograph of a surface of nickel silicide manufactured. in accordance with a preferred embodiment of the present invention- The nickel silicide is formed by plasma chemical vapor deposition of an amorphous sdi.con to a thickness of about 300A on a substrate at a temperature of 250C with an RF power of 15W, ion showering with a P ion dose of JOIIjL 10" cm-13 RF sputtering of nickel to a thickness of I OOA for 15 seconds at a temperature of 200'C, and annealing at a temperature of 260'C for one hour. As seen from the photograph, uniform silicide crystals are grown.
Fig. 2 illustrates a graph of sheet resistivity versus the annealing temperature of the nickel silicide formed from the nickel deposited on the ion-,doped amorphous silicon. The anneaag period is one hour for each case. The graph shows that although the sheet resistivity is about 500/cm2 when the annealing temperature is about 200'C, the sheet resistivity sharply 7 drops below 5 Q/cm2when the annealing temperature is over 23)O'C. The sheet resistivI is within a range of about I Q/cm2 when the annealing temperatures is over 260 " C. The extrapolation of this curve indicates that the sheet resistivity would be substantially constant even if the annealing temperature is elevated even higher. Thus, the nickel silicide can be applicable to a seLf-aligned type polysilicon TFT because the nickel silicide can form a low resistance electrode required for the polysilicon TFT.
Fig. 6 illustrates a cross-section of a polysilicon TFT with a silicide according to a preferred embodiment of the present invention. Referring to Fig. 6, the polysilicon TFT includes a semiconductor layer I I formed on an insulating substrate 10 made of quartz or glass or on an oxide film deposited thereon, a gate irtsulating film 13 formed of an oxide or nitride film, on the entire surface of the above structure, portions of which are removed to expose portions of the semiconductor layer 11. Heavily doped semiconductor layers 16 are formed on the gate insulating layer 1 3 and the exposed portions of the semiconductor layer 11, and doped nickel silicide layers 12 are formed over the heavily doped semiconductor layer 16. The doped nickel siEciae layers 12 and heavfly doped semiconductor layers 16 together constitute gate electrode 14 over the gate insulating film D and source/drain electrodes 15 over the semiconductor layer 11, respectively.
In this embodiment, the gate insulating film 1-33 and an overlying semiconductor layer 16 block or prevent an ion injection into the channel region of the semiconductor layer 11. Thus, it becomes possible to inject ions into the semiconductor layer I I on both sides of the gate insulatiril., film D and over the gate insulating film 13 to form heavily doped semiconductor layers 16. (This process is performed before forming the nickel silicide layers 12.) This eliminates the need for an ion stopper. Therefore, the polysilicon TFT accordina to the present invention does not require an ion-stopper forming step, because an additional 8 semiconductor layer is formed on the crate insulatina film and is converted into a silicide.
Also, this TFT has a simple fabrication process and higher production yield, because the crate 0 electrode of the nickel silicide layer on the gate insulating 51m forms a self-aligned structure with the source/drain regions.
Fias. 7A and 7B illustrate a method for fabricating the polysilicon TFT with a silicide according to a preferred embodiment of the present invention.
0 Referring to Fig. 7A, a semiconductor layer I I and a crate insulating film 13 are formed on an insulating substrate 10 in succession. Another semiconductor layer is formed on the :7 - gate insulating'film 1-3). The semiconductor layer on the crate insulating film D and the gate C insulating film 13) are patterned together, and then ion showering is performed to form heavily doped semiconductor layers 16 in the serniconductor layer on the crate insulatma film 1-3) and the exposed semiconductor layer I I on both sides of the crate insulating film 1-3).
0 1=1 Referring to Fig. 7B, nickel having a thickness of -3) 0 A is RFsputtered on the heavily 0 - doped semiconductor layers 16 to form nickel silicide layers 12 over the.. gate insulatin=1 film 13 and at both sides of the gate insulating film D. In the sputtering, a nickel target of p I ty 6; uri is preheated for 20 minutes at a temperature of 200'C under an initial vacuum of '-)xlO-" Torr. The sputtering is performed at 75 W RF power for 5 seconds. Then, the substance is annealed in an argon ambient for one hour at a substrate temperature of 260C to form nickel silicide layers 12. Residual nickel that did not react with silicon is removed by a mixture of IINO, and HCI with a ratio of 1:5.
Fig. 8A illustrates transition characteristics of a laser annealed polysilicon TFT with a doped nickel silicide according to a preferred embodiment of the present invention. The polysilicon TFT has a channel width/leng-th of (39-79)pm/(13-33)pm, for example. The field effect mobility and a threshold voltage obtained at the drain voltage of I V are 30.6 crn2/Vs
9 and 0.5 V, respectively. The figure shows that the leakage current is about 10 A, and the on/off current ratio is more than 10'.
Fig. 8B illustrates a graph showing output characteristics of the laser annealed polysilicon TET with a doped nickel silicide according to a preferred embodiment of the present invention. Fig. 8B shows no current crowding effect and kink effect even when the W drain voltage is low.
C' Filp 9A illustrates a graph showing transition characteristics of a solid state crystallized polysilicon TFT with a doped nickel siEcide according to a preferred embodiment of the present invention. The polysiEcon TFT has a channel width/length of(') 9-79) mrnl(l 3) -3) 3) urn, for example. The figure shows that the leakage current is less than 1 W10 A and the on/oE =ent ratio is more than 10'.
Fig. 9B illustrates a graph showing output characteristics of the solid state crystallized polysiEcon TFT with a doped nickel sificide according to the preferred embodiment of the present invention. Fig. 9B shows no current crowding effect and kink effect even when drain voltage is low. The crystallized polysilicon TFT of tne present invention has field efFect mobility and threshold voltage of 9.6 cnifVs and 5.9V, respectively, which are calculated at a channel transconductance g, according to a gate voltage obtained in a Enear region of the output characteristic curve.
According to the embodiment described, the fabrication process can be simplified, and the production yield as well as device operation reliability can be improved because the gate insulating film 13 and the overlying semiconductor layer over a channel region is used as an ion injection mask without using a stopper of a nitride or oxide film.
It will be apparent to those skilled in the art that various modifications and variations can be made in the polysilicon TFT with a silicide and a method for fabricating the same of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (27)

1. A polysilicon thin film transistor comprising a substrate; a polysilicon layer on the substrate; a gate insulating layer on the polysilicon layer; a aate electrode on the -ate insulating layer; and 0 0 I'D source and drain electrodes on the semiconductor layer at respective sides of the gate electrode, the source and drain electrodes being ohmic contact layers formed of silicide.
2. A polysilicon thin film transistor according to claim 1, wherein the gate electrode is formed of a siEcide.
3 A polysilicon thin film transistor according to claim 1, wherein the gate electrode is 0 formed of a silicide on a amorphous silicon formed on the gate insulating fdm.
4. A polysilicon thin fflm transistor according to claim 1, wherein the gate electrode is formed of a silicide on a doped amorphous silicon formed on the gate imulating 51m.
5. A polysiEcon thin film transistor comprising a substrate; a polysfficon layer on the substrate; a gate insulating layer on the polysilicon layer; a first sIl.icide acting as a gate electrode on the gate insulating layer; and 12 second and third silicides acting as source and drain electrodes, respectively, on the polysilicon layer at respective sides of the first silicide.
6. The polysilicon thin film transistor according to any one of the preceding claims, wherein the silicide includes Mn, Ta, Ti, W, Cr, Co, Pd or nickel silicides.
7. The polysilicon thin film transistor according to any one of the preceding claims, wherein a channel between the source and drain electrodes has a width of 39-79,um and a length of 13-33#m.
8. The polysilicon thin film transistor according to any one of the preceding claims, wherein the polysilicon thin film transistor has a leakage current of about 10" A and an on/off current ratio of more than 10'.
9. A method for fabricating a self-align type coplanar polysilicon thinfilm, transistor, the method comprising the steps offorming a polysilicon layer on an insulating substrate; forming a gate insulating film on the polysilicon layer, formiricr an amorphous sfficon layer on the gate insulating filmselectively removing the amorphous silicon layer and the gate isulating film to 0 0 leave a portion of each of the amorphous silicon layer and the gate insulating film on a channel region; converting the amorphous silicon layer into a silicide to form a gate electrode; and converting the polysilicon layer at sides of the gate insulating film into a silicide to
1 0 0 form source and drain electrodes.
13 10. The method according to claim 9, wherein the polysilicon layer is laser annealed.
11. The method according to claim 9, wherein the polysilicon layer is solid state crystallized.
12. The method according to claim 9, 10 or 11, wherein the silicide includes Mn, Ta, Ti, W, Cr, Co, Pd or nickel silicides.
13. The method according to claim 9, 10, 11 or 12, wherein the amorphous silicon layer is doped before the step of forming the silicide.
14. The method according to claim 9, 10, 11 or 12, wherein the amorphous silicon layer at sides of the gate insulating film is doped before the step of forming the silicide.
15. The method according to claim 9, 10, 11, 12, 13 or 14, wherein the gate insulating film is formed of a nitride film.
16. The method according to any one of claims 9 to 15, wherein a channel is formed having a width of about 59,um and a length of about 23Aim.
17. The method according to any one of claims 9 to 16, wherein the polysilicon thin film transistor is formed to have a leakage current of less than 10 A and an on/off current ratio of more than 1T.
14
18. A method for fabricating a self-aligm type planar po[ysificon thin film transi Istor, the method comprising the steps of: forrrUng a first semiconductor layer on an insulating substrateforMIng a gate insulating film on the serniconductor layer; fornung a second semiconductor layer on the gate insulating film; 0 C.7 patterning the gate insulating film and the second semiconductor layer to expose first and second side portions of the first semiconductor layer; ion doping the second semiconductor layer and the first and second side portions of the first semiconductor layer; and forming a silicide layer over the gate insulating film and the first and second side portions of the first semiconductor layer.
19, The mpthod according to claim 18, wherein the polysilicon layer is laser annealed.
20. The method according to claim 18, wherein the polysilicon layer is solid state crystallized.
21. The method according to claim 18, 19 or 20, wherein the silicide includes Mn, Ta, Ti, W, Cr, Co, Pd or nickel silicides.
22. The method according to claim 18, 19, 20 or 21, wherein the gate insulating film is formed of a nitride film.
23. The method according to claim 18, 19, 20, 21 or 22, wherein a channel is formed having a width of 39-79,um and a length of 13-33ym.
24. The method according to claim 18, 19, 20, 21, 22 or 23, wherein the polysilicon thin film transistor is formed to have a leakage current of about 100 A and an on/off current ratio of more than 10'.
25. A method of forming a thin film transistor electrode, the method comprising applying a metal to a heavily doped semiconductor layer such that a metal silicide layer is formed.
26. A thin film transistor substantially as hereinbefore described with reference to and/or as illustrated in any one of or any combination of Figs. 1, 2 and 6 to 9B of the accompanying drawings.
27. A method of forming a thin film transistor substantially as hereinbefore C described with reference to and/or as illustrated in any one of or any combination of Figs. 1, 2 and 6 to 9B of the accompanying drawings.
GB9712868A 1996-06-28 1997-06-18 Method for fabricating thin film transistor Expired - Lifetime GB2314677B (en)

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EP0451968A1 (en) * 1990-04-11 1991-10-16 THE GENERAL ELECTRIC COMPANY, p.l.c. Process for manufacturing thin film transistor
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103943509A (en) * 2014-04-11 2014-07-23 深圳市华星光电技术有限公司 Manufacture procedure method of thin film transistor
CN103943509B (en) * 2014-04-11 2017-02-15 深圳市华星光电技术有限公司 Manufacture procedure method of thin film transistor

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JPH1098199A (en) 1998-04-14
KR100252926B1 (en) 2000-04-15
DE19727396A1 (en) 1998-01-02
FR2752338B1 (en) 2001-05-18
KR980006438A (en) 1998-03-30
GB9712868D0 (en) 1997-08-20
FR2752338A1 (en) 1998-02-13
GB2314677B (en) 2000-04-05

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