CN100411153C - Method for producing film tranistor array and its driving circuit - Google Patents
Method for producing film tranistor array and its driving circuit Download PDFInfo
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- CN100411153C CN100411153C CNB2006101006496A CN200610100649A CN100411153C CN 100411153 C CN100411153 C CN 100411153C CN B2006101006496 A CNB2006101006496 A CN B2006101006496A CN 200610100649 A CN200610100649 A CN 200610100649A CN 100411153 C CN100411153 C CN 100411153C
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Abstract
This invention relates to a method for manufacturing a film transistor array and a driving circuit including: providing a base plate to form a polysilicon layer and a doped film of a first kind of conduction, carrying out a first photo-mask technology to form multiple island structures, carrying out a second photo-mask technology to inject the doped regions of the second conduction type in the doped film of the first one, forming a first conduction layer on the structure and carrying out a third photo-mask technology to form a source and a drain and a lower electrode of a memory condenser, forming a first dielectric layer and a second conduction layer and carrying out a fourth photo-mask technology to form a stacked structure of a gating insulation layer and the grating and forming a dielectric layer and an upper electrode of the memory capacitor forming a protection layer on the structure and carrying out a fifth photo-mask to form an open-end for exposing the source and drain and the upper electrode of the capacitor, forming a conduction layer on the structure and carrying out a sixth photo-mask to form lead and pixel electrode.
Description
The application is dividing an application of No. 03101633.2 application for a patent for invention.
Technical field
The present invention relates to the manufacture method of a kind of thin film transistor (TFT) array and drive circuit thereof, and the particularly a kind of thin film transistor (TFT) array that can finish with six road photo-marsk processes and the manufacture method of drive circuit thereof.
Background technology
At improving rapidly of multimedia society, be indebted to the leap progress of semiconductor element or man-machine display device mostly.With regard to display, (Cathode Ray Tube CRT) because of having excellent display quality and its economy, monopolizes monitor market in recent years to cathode ray tube always.Yet, operate the environment of most terminating machine/display equipments on the table for the individual, or with the incision of the viewpoint of environmental protection, if predicted cathode ray tube because of still there being a lot of problems in space utilization and the energy resource consumption with the trend of saving the energy, and the method for solution can't effectively be provided for the demand of light, thin, short, little and low consumpting power.Therefore, have that high image quality, space utilization efficient are good, the Thin Film Transistor-LCD (TFT-LCD) of low consumpting power, advantageous characteristic such as radiationless becomes the main flow in market gradually.
Our known thin-film transistor can be divided into two kinds of amorphous silicon film transistor and polycrystalline SiTFTs haply.Low temperature polycrystalline silicon (LTPS) technology is different from general traditional amorphous silicon (a-Si) technology, its electron mobility can reach more than the 200cm2/V-sec, therefore can make the size of thin-film transistor littler, have the aperture opening ratio (aperture ratio) that increases display, reduce function such as power consumption.In addition, the low temperature polycrystalline silicon manufacturing process can be manufactured in the part drive circuit on the substrate in company with the thin-film transistor manufacturing process in the lump, significantly promotes the characteristic and the reliability of display panels, so manufacturing cost significantly reduces.
Fig. 1 (A) illustrates profile into existing thin film transistor (TFT) array and drive circuit manufacturing process to Fig. 1 (H).Please refer to Figure 1A, one substrate 100 at first is provided, and on substrate 100, form a polysilicon layer (polysilicon layer), then define this polysilicon layer, so that it forms island structure 102a, 102b, the 102c of a plurality of polycrystalline silicon materials with the first road photo-marsk process (Mask 1).
Then please refer to Fig. 1 (B), on the substrate 100 that is formed with island structure 102a, 102b, 102c, form one first dielectric layer 104 and a conductor layer (not painting among the figure) in regular turn.Then define this conductor layer with the second road photo-marsk process (Mask 2) again, on island structure 102a, 102b, 102c, forming grid 106a, 106b, 106c respectively, and on the appropriate location of substrate 100, form the bottom electrode 108 of holding capacitor.
Then please refer to Fig. 1 (C),,, and in island structure 102c, form N+ doped region 112 with formation N+ doped region 110 in island structure 102a with the position of the 3rd road photo-marsk process (Mask 3) decision N+ doped region 110,112.Wherein, the N+ doped region 110 among the island structure 102a is the both sides that are distributed in grid 106a, and the N+ doped region 112 among the island structure 102c then is the both sides that are distributed in grid 106c.
Then please refer to Fig. 1 (D), then,, and in island structure 102c, form N-doped region 116 with formation N-doped region 114 in island structure 102a with the position of the 4th road photo-marsk process (Mask 4) decision N-doped region.Wherein, the N-doped region 114 among the island structure 102a is to be distributed between grid 106a and the N+ doped region 110, and the N-doped region 116 among the island structure 102c then is to be distributed between grid 106c and the N+ doped region 112.
Then please refer to Fig. 1 (E), with the position of the 5th road photo-marsk process (Mask 5) decision P+ doped region, in island structure 102b, to form P+ doped region 118.Wherein, the P+ doped region 110 among the island structure 102b is the both sides that are distributed in grid 106b.
Then please refer to Fig. 1 (F), forming one second dielectric layer 120 is covered on the substrate 100, then with the 6th road photo-marsk process (Mask 6) definition first dielectric layer 104 and second dielectric layer 120, to determine the pattern of first dielectric layer 104 and second dielectric layer 120.
Have opening 122a, opening 122b and opening 122c in first dielectric layer 104 and second dielectric layer 120.Wherein, opening 122a exposes N+ doped region 110, and opening 122b exposes P+ doped region 118, and opening 122c exposes N+ doped region 112.
Then please refer to Fig. 1 (G), form a conductor layer (not painting among the figure) and be covered on second dielectric layer 120, then define above-mentioned conductor layer to form source/drain 124 with the 7th road photo-marsk process (mask 7) again.Wherein, source/drain 124 is to expose with N+ doped region 110, P+ doped region 118 respectively by opening 122a, opening 122b and opening 122c and N+ doped region 112 electrically connects.
Then please refer to Fig. 1 (H), form a flatness layer 126 and be covered on the substrate 100 that is formed with source/drain 124, then again with the 8th road photo-marsk process (Mask 8) definition flatness layer 126, with the pattern of decision flatness layer 126.Wherein, flatness layer 126 has opening 128, and this opening 128 is in order to source/drain 124a is exposed.
After with the 8th road photo-marsk process (Mask 8) definition flatness layer 126, then can form a conductive layer (not painting among the figure) on substrate 100, this conductive layer is transparent material such as tin indium oxide normally.At last again with the above-mentioned conductive layer of the 9th road photo-marsk process (Mask 9) definition, to form pixel electrode 130.
Please refer to Fig. 1 (H) equally, can be learnt by Fig. 1 (H) left side, N-doped region 116 among the island structure 102c and N+ doped region 112, grid 106c and source/drain 124c constitute a N type metal oxide semiconductor (NMOS).P+ doped region 118 among the island structure 102b, grid 106b and source/drain 124b constitute a P-type mos (PMOS).And can constitute a complementary metal oxide semiconductors (CMOS) (CMOS) by above-mentioned N type metal oxide semiconductor (NMOS) and P-type mos (PMOS), this complementary metal oxide semiconductors (CMOS) (CMOS) institute's role on panel is a built-in drive circuit (driving circuit), in order to driving Fig. 1 H right side thin-film transistor (TFT), and then the demonstration of control pixel.
Can learn that by Fig. 1 (H) right side N-doped region 110 among the island structure 102a and N+ doped region 114, grid 106a and source/drain 124a are the thin-film transistors (Poly-TFT) that constitutes a polysilicon kenel.Wherein, thin-film transistor is controlled the data (data) that write pixel electrode 130 by the driving of above-mentioned complementary metal oxide semiconductors (CMOS) (CMOS).
Fig. 2 illustrates the making flow chart into existing thin film transistor (TFT) array and drive circuit.Please refer to Fig. 2, the making flow process of existing thin film transistor (TFT) array and drive circuit mainly is by definition polysilicon layer S200, definition Shan Ji ﹠amp; Pattern S210, the definition Yuan Ji/Lou Ji ﹠amp of the bottom electrode S202 of storage capacitance, definition N+ doped region S204, definition N-doped region S206, definition P+ doped region S208, definition first dielectric layer; The pattern S214 of the top electrode S212 of storage capacitance, definition second dielectric layer, and the steps such as pattern S216 of definition pixel electrode constitute.
Existing thin film transistor (TFT) array and driving circuit structure thereof, photomask number required on making is more, usually need eight roads (not comprising the making of N-doped region 114,116) or nine road photo-marsk processes to finish, make that the manufacturing process cost is difficult to reduce.In addition, because required photomask number is more, the time that makes panel make can't effectively shorten, and yield is difficult to promote.
Summary of the invention
The objective of the invention is to propose the manufacture method of a kind of thin film transistor (TFT) array and drive circuit thereof, it only needs can complete with six road photo-marsk processes.
For reaching above-mentioned purpose of the present invention, the manufacture method of a kind of thin film transistor (TFT) array and drive circuit is proposed, may further comprise the steps: a substrate is provided, and forms the doping film of the polysilicon layer and first conduction type successively; Carry out first photo-marsk process, with doping film composition to this polysilicon layer and first conduction type, formation comprises a plurality of island structures of the doping film of this polysilicon layer and this first conduction type, wherein, these a plurality of island structures comprise first island structure that is used to form thin film transistor (TFT) array and second island structure that is used to form drive circuit; Carry out second photo-marsk process, on the part or all of zone of described second island structure of at least a portion, in the doping film of first conduction type, to inject the doped region of second conduction type; On resulting structures, form first conductor layer, and carry out the 3rd photo-marsk process, with to this first conductor layer composition, doping film at this first conduction type of each island structure, form source electrode and drain electrode on the doped region of this second conduction type respectively, and on substrate, form the bottom electrode of holding capacitor, and in the 3rd photo-marsk process, with same photomask the doping film of this first conduction type of being positioned at this first conductor layer below and the doped region of second conduction type are carried out composition, thus this source electrode and this drain electrode with its below the doping film of this first conduction type or the doped region of second conduction type have identical pattern; On resulting structures, form first dielectric layer and second conductor layer, and carry out the 4th photo-marsk process, with to this first dielectric layer and this second conductor layer composition, on this polysilicon layer of each island structure, form the stacked structure of gate insulation layer and grid, simultaneously, form holding capacitor dielectric layer and top electrode in position corresponding to the bottom electrode of described holding capacitor; On resulting structures, form protective layer, and carry out the 5th photo-marsk process,, form the opening of the top electrode that exposes each described source electrode and drain electrode and holding capacitor with to this protective layer composition; On resulting structures, form conductive layer, and carry out the 6th photo-marsk process,, form lead and pixel electrode with to this conductive layer composition.
Membrane according to the invention transistor array and driving circuit structure thereof are suitable for being disposed on the substrate, and this structure comprises: a plurality of scan wirings are disposed on this substrate; A plurality of signal wirings are disposed on this substrate; A plurality of thin-film transistors, those thin-film transistors are to drive by those scan wirings and those signal wirings, and each those thin-film transistor comprises: a polysilicon layer is disposed on this substrate; Source is disposed at this polysilicon top; One N+ doping film is disposed between this polysilicon layer and this source/drain; One grid is disposed at this polysilicon top; One gate insulator is disposed between this polysilicon and this grid; A plurality of pixel electrodes, dispose corresponding to those thin-film transistors: a plurality of storage capacitances, corresponding to those pixel electrodes configurations; And a plurality of complementary metal oxide semiconductors (CMOS)s, each those complementary metal oxide semiconductors (CMOS) comprises a N type metal oxide semiconductor and a P-type mos, described gate insulator comprises: one first dielectric layer; And one second dielectric layer, be disposed on this first dielectric layer.
Membrane according to the invention transistor array and driving circuit structure thereof, be suitable for being disposed on the substrate, it is made of a plurality of scan wirings, a plurality of signal wiring, a plurality of thin-film transistor, a plurality of pixel electrode, a plurality of storage capacitance and a plurality of complementary gold oxygen semitransistor.
Among the present invention, thin-film transistor mainly is by a polysilicon layer, source, a N+ doping film, a grid and a gate insulator.Wherein, polysilicon layer is to be disposed on the substrate, and source/drain is disposed at the polysilicon top, and the N+ doping film is disposed between polysilicon layer and the source/drain, and gate configuration is in the polysilicon top, and gate insulator then is disposed between polysilicon and the grid.
Among the present invention, pixel electrode and storage capacitance are to be disposed on the substrate corresponding to thin-film transistor.
Among the present invention, complementary metal oxide semiconductors (CMOS) is made of a N type metal oxide semiconductor and a P-type mos.The N type metal oxide semiconductor is made of a polysilicon layer, source, a N+ doping film, a grid and a gate insulator.Wherein, polysilicon layer is disposed on the substrate, and source/drain is disposed at the polysilicon top, and the N+ doping film is disposed between polysilicon and the source/drain, and gate configuration is in the polysilicon top, and gate insulator then is disposed between polysilicon layer and the grid.
In addition, in the N type metal oxide semiconductor, more comprise a N-doped region in the polysilicon layer between grid and the source/drain.
P-type mos is made of a polysilicon layer, source, a P+ doping film, a grid and a gate insulator.Wherein, polysilicon layer is disposed on the substrate, and source/drain is disposed at the polysilicon top, and the P+ doping film is disposed between polysilicon and the source/drain, and gate configuration is in the polysilicon top, and gate insulator then is disposed between polysilicon layer and the grid.
Above-mentioned gate insulator is made of at least one first dielectric layer, and wherein, the material of first dielectric layer for example is silica, silicon nitride, hydrogeneous dielectric layer etc.In addition, gate insulator also can be made of at least one first dielectric layer and one second dielectric layer, and wherein, the material of first dielectric layer comprises silica, silicon nitride, hydrogeneous dielectric layer etc., and the material of second dielectric layer for example is a photoresist.
Among the present invention, the material of grid for example is aluminium/molybdenum, aluminium/titanium etc., and the material of source/drain for example is aluminium/molybdenum, molybdenum etc.
At the penetration panel, the material of conductor layer can be selected transparent conductors such as tin indium oxide for use.At reflective panel, the material of conductor layer can select for use metal etc. to have the material of good reflection characteristic.In addition, be example with reflective panel, the surface of conductor layer (being generally the metal with good reflection ability) below protective layer is a concavo-convex surface for example, to promote the effect of conductor layer reflection ray.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, especially exemplified by a preferred embodiment, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 (A) is to the profile of Fig. 1 (H) for existing thin film transistor (TFT) array and drive circuit manufacturing process;
Fig. 2 is the making flow chart of existing thin film transistor (TFT) array and drive circuit;
Fig. 3 (A) to Fig. 3 (I) be profile according to one embodiment of the present invention thin film transistor (TFT) array and drive circuit manufacturing process;
Fig. 4 is the making flow chart according to one embodiment of the present invention thin film transistor (TFT) array and drive circuit;
Fig. 5 is according to the layout of one embodiment of the present invention complementary metal oxide semiconductors (CMOS) (CMOS) (layout) schematic diagram; And
Fig. 6 is the schematic layout pattern according to one embodiment of the present invention pixel.
Embodiment
Fig. 3 (A) to Fig. 3 (I) be profile according to one embodiment of the present invention thin film transistor (TFT) array and drive circuit manufacturing process.Please refer to Fig. 3 (A), one substrate 300 at first is provided, and on substrate 300, form a polysilicon layer and a N+ doping film in regular turn, then above-mentioned polysilicon layer and the N+ doping film of one first road photo-marsk process (Mask 1) definition a plurality ofly piles up the island structure that forms by polysilicon layer 302a, 302b, 302c and N+ doping film 304a, 304b, 304c to form.
The generation type of above-mentioned polysilicon layer for example is to form an amorphous silicon membrane (a-Si) earlier on substrate 300, then again this amorphous silicon layer is carried out an excimer laser annealing process (Excimer LaserAnnealing, ELA), so that the amorphous silicon layer crystallization becomes polysilicon layer.And the formation method of N+ doping film for example is directly to deposit one in the mode of chemical vapour deposition (CVD) to have N+ doped amorphous silicon film on substrate 300; Or form earlier an amorphous silicon membrane on substrate 300, after again this amorphous silicon is carried out N type ion doping, to form the N+ doping film.
Then please refer to Fig. 3 (B) and Fig. 3 (C), with the position of the second road photo-marsk process (Mask 2) decision P+ doped region 306, by the action of the doping of P type ion in the Zone Full (illustrating) of N+ doping film 304b or formation P+ doped region 306 in the zone (illustrating) partly as Fig. 3 (C) as Fig. 3 (B).
Then please refer to Fig. 3 (D), on substrate 300, form one first conductor layer (not illustrating among the figure), then again with the first above-mentioned conductor layer of the 3rd road photo-marsk process (Mask 3) definition, on N+ doping film 304a, P+ doped region 306 and N+ doping film 304c, to form source/ drain 308a, 308b, 308c respectively.And on the appropriate location of substrate 300, form the bottom electrode 310 of holding capacitor.
Yet when definition first conductor layer, the 3rd road photo-marsk process can define N+ doping film 304a, 304b, 304c or the P+ doped region 306 (shown in Fig. 3 (B), 3 (C)) that is positioned at first conductor layer below simultaneously.Therefore, source/drain 308a can have identical pattern with the N+ doping film 304a under it; Source/drain 308b can have identical pattern with the P+ doped region 306 under it; And source/drain 308c also can have identical pattern with the N+ doping film 304c under it.
Then please refer to Fig. 3 (E), on substrate 300, form one first dielectric layer (not illustrating among the figure) and one second conductor layer (not illustrating among the figure) in regular turn, then with the 4th road photo-marsk process (Mask 4) the above-mentioned dielectric layer of definition and second conductor layer, on polysilicon layer 302a, 302b, 302c, to form the stacked structure of gate insulator 312a, 312b, 312c and grid 314a, 314b, 314c respectively.
In the present embodiment, gate insulator 312a, 312b, 312c for example can carry out a rapid hot technics (Rapid Thermal Process to gate insulator 312a, 312b, 312c after forming, RTP), so that the quality of gate insulator 312a, 312b, 312c more promotes.
Please refer to Fig. 3 (E) equally, can form a dielectric layer 316 and a top electrode 318 on bottom electrode 310 in the 4th road photo-marsk process (Mask 4), bottom electrode 310, dielectric layer 316 and top electrode 318 promptly constitute a holding capacitor.In addition, can on the appropriate location of substrate 300, form the stacked structure of dielectric layer 320 and distribution 322 in the 4th road photo-marsk process (Mask 4).
Yet, have the knack of the production order that should be able to understand grid 314a, 314b, 314c and source/ drain 308a, 308b, 308c easily of this technology and can adjust to some extent in response to manufacturing process.Just, do not limit the production order of source/ drain 308a, 308b, 308c and grid 314a, 314b, 314c in the present embodiment.
Then please refer to Fig. 3 (F), form a protective layer 324 on substrate 300, then again with the 5th road photo-marsk process (Mask 5) definition protective layer 324, with the pattern of decision protective layer 324.For example have opening 326a, 326b, 326c, 326d, 326e in the protective layer 324.Wherein, opening 326a is in order to source/drain 308a is exposed, opening 326b is in order to source/drain 308b is exposed, opening 326c is in order to source/drain 308c is exposed, opening 326d exposes in order to the top electrode 318 with holding capacitor, and opening 326e is in order to distribution 322 is exposed.
Then please refer to Fig. 3 (G), after with the 5th road photo-marsk process (Mask 5) definition protective layer 324, then form a conductive layer (not illustrating among the figure) on substrate 300, this conductive layer is transparent material such as tin indium oxide normally.At last again with the above-mentioned conductive layer of the 6th road photo-marsk process (Mask 6) definition, to form lead 328 and pixel electrode 330.
Then please refer to Fig. 3 (H) and Fig. 3 (I), it illustrates with Fig. 3 (F) and 3 (G) similar, and for its difference is that one is penetration panel (Fig. 3 (H) and Fig. 3 (I)), and another is reflective panel (Fig. 3 (F) and Fig. 3 (G)).Protective layer 324 among Fig. 3 (H) and Fig. 3 (I) has a convex-concave surface 332, and the pixel electrode 334 that is disposed on the convex-concave surface 332 for example is to select for use some to have the conductor of good result.Can promote the effect of pixel electrode 334 (reflecting electrode) reflection ray by the convex-concave surface on the protective layer 324 332.
Then please be simultaneously with reference to Fig. 3 (G) and Fig. 3 (I), can learn that by Fig. 3 (G) and Fig. 3 (I) left side polysilicon layer 302c, N+ doping film 304c, source/drain 308c, gate insulator 312c and grid 314c constitute a N type metal oxide semiconductor (NMOS).Polysilicon layer 302b, P+ doping film 306, source/drain 308b, gate insulator 312b and grid 314b constitute a P-type mos (PMOS).And can constitute a complementary metal oxide semiconductors (CMOS) (CMOS) by above-mentioned N type metal oxide semiconductor (NMOS) and P-type mos (PMOS), this complementary metal oxide semiconductors (CMOS) institute's role on panel is a built-in drive circuit, in order to driving Fig. 3 (G) and Fig. 3 (I) right side thin-film transistor, and then the demonstration of control pixel.
Can learn that by Fig. 3 (G) and Fig. 3 (I) right side polysilicon layer 302a, N+ doping film 304a, source/drain 308a, gate insulator 312a and grid 314a are the thin-film transistors that constitutes a polysilicon kenel.Wherein, thin-film transistor is to control the data that write in pixel electrode 330 or the pixel electrode 334 by the driving of above-mentioned complementary metal oxide semiconductors (CMOS).
Fig. 4 illustrates and is the making flow chart according to one embodiment of the present invention thin film transistor (TFT) array and drive circuit.Please refer to Fig. 4, the making flow process of present embodiment thin film transistor (TFT) array and drive circuit mainly is by definition polysilicon layer S400, definition P+ doped region S402, definition Yuan Ji/Lou Ji ﹠amp; N+ doping film Hui Shi ﹠amp; The bottom electrode S404 of storage capacitance, definition Shan Ji ﹠amp; The pattern S408 of the top electrode S406 of storage capacitance, definition protective layer, and definition Xiang Sudianji ﹠amp; Steps such as the pattern S410 of lead constitute.Need six road photo-marsk processes altogether by S400 to S410.Yet,, need to increase again one photo-marsk process if make N-doped region (lightly doped region) in the N type metal oxide semiconductor (NMOS) in drive circuit.
Fig. 5 illustrates and is the schematic layout pattern according to complementary metal oxide semiconductors (CMOS) in one embodiment of the present invention drive circuit.Please refer to Fig. 5, apply voltage Vin respectively, Vdd and Vss are in contact 504, on 506 and 508, because contact 504 electrically connects with grid 500 and grid 502, therefore in order to the conducting of control N type metal oxide semiconductor and P-type mos channel layer whether the Vin that puts on the contact 504 can be, and the conducting of N type metal oxide semiconductor and P-type mos channel layer with otherwise can directly have influence on the output Vout of complementary metal oxide semiconductors (CMOS) by contact 510, and by the Vout value of contact 510 output may for Vdd or Vss one of them.
Yet, the drive circuit that is illustrated among Fig. 5 only is the schematic layout pattern of one complementary metal oxide semiconductors (CMOS) unit, and the drive circuit that should be able to understand on the panel of haveing the knack of this technology can be arranged in pairs or groups other circuit or element and constituted by above-mentioned complementary metal oxide semiconductors (CMOS), to drive the pel array on the panel.
Fig. 6 illustrates and is the schematic layout pattern according to one embodiment of the present invention pixel.Please refer to Fig. 6, comprise mainly that to the produced dot structure of the six road photo-marsk processes of Fig. 3 (I) one scan distribution 600, a signal wiring 602, a thin-film transistor 604, a holding capacitor 606 and a pixel electrode 330 (334) are constituted by above-mentioned Fig. 3 (A).Wherein, thin-film transistor 604 is made of polysilicon layer 302a, grid 314a, N+ doping film 304a and source/drain 308a.In addition, scan wiring 600 is connected with grid 314a in the thin-film transistor 604, to control the switch of its lower channel layer (polysilicon layer 302a), the data of desiring to write then are to write in the pixel electrode 330 (334) via the control of signal wiring 602 transmission and thin-film transistor 604.
In sum, thin film transistor (TFT) array of the present invention and driving circuit structure thereof have following advantage at least:
1. thin film transistor (TFT) array of the present invention and driving circuit structure thereof only need six road photomasks to finish, and its cost of manufacture is significantly reduced.
2. thin film transistor (TFT) array of the present invention and driving circuit structure thereof, its employed photomask number is less, and the time that makes panel make shortens many.
3. thin film transistor (TFT) array of the present invention and driving circuit structure thereof, its employed photomask number is less, helps the lifting of panel acceptance rate.
Though the present invention discloses as above with a preferred embodiment, so it is not in order to limit the present invention.
Claims (12)
1. the manufacture method of thin film transistor (TFT) array and drive circuit may further comprise the steps:
One substrate is provided, and forms the doping film of the polysilicon layer and first conduction type successively;
Carry out first photo-marsk process, with doping film composition to this polysilicon layer and first conduction type, formation comprises a plurality of island structures of the doping film of this polysilicon layer and this first conduction type, wherein, these a plurality of island structures comprise first island structure that is used to form thin film transistor (TFT) array and second island structure that is used to form drive circuit;
Carry out second photo-marsk process, on the part or all of zone of described second island structure of at least a portion, in the doping film of first conduction type, to inject the doped region of second conduction type;
On resulting structures, form first conductor layer, and carry out the 3rd photo-marsk process, with to this first conductor layer composition, doping film at this first conduction type of each island structure, form source electrode and drain electrode on the doped region of this second conduction type respectively, and on substrate, form the bottom electrode of holding capacitor, and in the 3rd photo-marsk process, with same photomask the doping film of this first conduction type of being positioned at this first conductor layer below and the doped region of second conduction type are carried out composition, thus this source electrode and this drain electrode with its below the doping film of this first conduction type or the doped region of second conduction type have identical pattern;
On resulting structures, form first dielectric layer and second conductor layer, and carry out the 4th photo-marsk process, with to this first dielectric layer and this second conductor layer composition, on this polysilicon layer of each island structure, form the stacked structure of gate insulation layer and grid, simultaneously, form holding capacitor dielectric layer and top electrode in position corresponding to the bottom electrode of described holding capacitor;
On resulting structures, form protective layer, and carry out the 5th photo-marsk process,, form the opening of the top electrode that exposes each described source electrode and drain electrode and holding capacitor with to this protective layer composition;
On resulting structures, form conductive layer, and carry out the 6th photo-marsk process,, form lead and pixel electrode with to this conductive layer composition.
2. method according to claim 1, wherein, the step that forms polysilicon layer is included on this substrate and forms amorphous silicon membrane, and carries out quasi-molecule laser annealing technology, being polysilicon layer with the amorphous silicon membrane crystallization.
3. method according to claim 1, wherein, the step that forms the doping film of first conduction type comprises that the mode with chemical vapour deposition (CVD) deposits and has the first conduction type doped amorphous silicon film.
4. method according to claim 1, wherein, the step that forms the doping film of first conduction type comprises formation amorphous silicon membrane earlier, this amorphous silicon membrane is carried out the ion doping of first conduction type again.
5. according to the described method of one of claim 1-4, wherein said first conduction type is the N+ type, and described second conduction type is the P+ type.
6. method according to claim 1 wherein, after described the 4th photo-marsk process forms gate insulation layer, also comprises quick thermal treatment process.
7. method according to claim 1, wherein, described gate insulation layer is to be selected from the individual layer of silica, silicon nitride, hydrogeneous dielectric layer or the bilayer that is made of layer that is selected from silica, silicon nitride, hydrogeneous dielectric layer and photoresist.
8. method according to claim 1 wherein, comprises the indium tin oxide transparent conductive layer at the formed conductive layer of described the 6th photo-marsk process.
9. method according to claim 1, wherein, described protective layer forms convex-concave surface in the position corresponding to the pixel electrode above it.
10. method according to claim 9, wherein, described pixel electrode comprises reflecting electrode.
11. method according to claim 5, wherein, the drive circuit on described second island structure comprises N type metal oxide semiconductor transistor and P-type mos transistor, to constitute CMOS (Complementary Metal Oxide Semiconductor) transistor.
12. method according to claim 11, wherein, described CMOS (Complementary Metal Oxide Semiconductor) transistor drives the thin-film transistor that forms on described first island structure, to drive pixel electrode.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006101006496A CN100411153C (en) | 2003-01-10 | 2003-01-10 | Method for producing film tranistor array and its driving circuit |
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| CNB2006101006496A CN100411153C (en) | 2003-01-10 | 2003-01-10 | Method for producing film tranistor array and its driving circuit |
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| CNB031016332A Division CN1293632C (en) | 2003-01-10 | 2003-01-10 | Film transistor array and its driving circuit structure |
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| CN1901168A CN1901168A (en) | 2007-01-24 |
| CN100411153C true CN100411153C (en) | 2008-08-13 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI617029B (en) * | 2009-03-27 | 2018-03-01 | 半導體能源研究所股份有限公司 | Semiconductor device |
| KR102290831B1 (en) * | 2009-10-16 | 2021-08-19 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Liquid crystal display device and electronic apparatus having the same |
| CN103985716B (en) * | 2014-05-06 | 2018-03-27 | 深圳市华星光电技术有限公司 | Method for manufacturing thin film transistor array substrate and thin-film transistor array base-plate |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1098199A (en) * | 1996-06-28 | 1998-04-14 | Lg Electron Inc | Polysilicon thin-film transistor using silicide and its manufacture |
| US5913113A (en) * | 1997-02-24 | 1999-06-15 | Lg Electronics Inc. | Method for fabricating a thin film transistor of a liquid crystal display device |
| US6300174B1 (en) * | 1996-05-11 | 2001-10-09 | Lg Electronics Inc. | Liquid crystal panel having a thin film transistor for driver circuit and a method for fabricating thereof |
| US6403409B1 (en) * | 1999-08-30 | 2002-06-11 | Samsung Electronics Co., Ltd. | Method for fabricating top gate type polycrystalline silicon thin film transistor |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6300174B1 (en) * | 1996-05-11 | 2001-10-09 | Lg Electronics Inc. | Liquid crystal panel having a thin film transistor for driver circuit and a method for fabricating thereof |
| JPH1098199A (en) * | 1996-06-28 | 1998-04-14 | Lg Electron Inc | Polysilicon thin-film transistor using silicide and its manufacture |
| US5913113A (en) * | 1997-02-24 | 1999-06-15 | Lg Electronics Inc. | Method for fabricating a thin film transistor of a liquid crystal display device |
| US6403409B1 (en) * | 1999-08-30 | 2002-06-11 | Samsung Electronics Co., Ltd. | Method for fabricating top gate type polycrystalline silicon thin film transistor |
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