CN202423290U - Thin film transistor array substrate - Google Patents
Thin film transistor array substrate Download PDFInfo
- Publication number
- CN202423290U CN202423290U CN 201120544641 CN201120544641U CN202423290U CN 202423290 U CN202423290 U CN 202423290U CN 201120544641 CN201120544641 CN 201120544641 CN 201120544641 U CN201120544641 U CN 201120544641U CN 202423290 U CN202423290 U CN 202423290U
- Authority
- CN
- China
- Prior art keywords
- film transistor
- wiring
- electrode
- source
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The utility model relates to the technical field of display, in particular to a thin film transistor array substrate. The thin film transistor array substrate at least comprises a substrate which is provided with a first surface, and a first thin film transistor, a second thin film transistor, a memory capacitor and a gate insulating layer, which are formed on the first surface of the substrate, wherein the first thin film transistor and the second thin film transistor are thin film transistors of different types; the substrate comprises a first region, a second region and a third region; the first thin film transistor is positioned in the first region; the second thin film transistor is positioned in the second region; the memory capacitor is positioned in the third region; the first thin film transistor comprises a first gate, a first source, a first drain and a first channel region; the second thin film transistor comprises a second gate, a second source, a second drain, a second channel region and a lightly-doped source drain region; and the memory capacitor comprises a polycrystalline silicon heavily-doped region and an electrode.
Description
Technical field
The utility model relates to the Display Technique field, relates in particular to a kind of thin-film transistor array base-plate.
Background technology
Thin-film transistor (TFT) is widely used in flat-panel display device, such as present the most common LCD (LCD), and organic light emitting display (AMOLED).
In the flat panel display product based on the TFT technology of effective sale, the TFT device of use belongs to two types basically: amorphous silicon film transistor (a-Si TFT) and polycrystalline SiTFT at present.For the latter; Difference according to its manufacturing process; Low-temperature polysilicon film transistor (LTPS TFT) and high temperature polysilicon thin-film transistor (HTPS TFT) be can be divided into again, small-medium size display device and microsize display device (like the perspective view image source) etc. are applicable to respectively.
With respect to amorphous silicon film transistor; Low-temperature polysilicon film transistor has plurality of advantages; Like high two one magnitude of its mobility ratio amorphous silicon film transistor; Device that can reduced size is realized stronger driving force, improves the display device aperture opening ratio, and also more being applicable to needs the active matrix organic light-emitting diode of current drives display floater; And for example its threshold voltage is more stable, can satisfy the stability requirement of active matrix organic light-emitting diode display floater, and becomes the ideal selection that drives the active matrix organic light-emitting diode display floater; For another example; Amorphous silicon film transistor can only form N type device; And low-temperature polysilicon film transistor can form P type and two kinds of complementary thin-film transistors of N type; This makes that to utilize low-temperature polysilicon film transistor on glass substrate, to form circuit more flexible, the way on also coming true, thus reach the purpose of simplification peripheral drive circuit.Generally speaking, low-temperature polysilicon film transistor is because of having plurality of advantages, makes that it is integrated in high-resolution, circuit, display device has extensive use aspect integrated.
With respect to amorphous silicon film transistor; The manufacture craft more complicated of low-temperature polysilicon film transistor; Generally speaking; Amorphous silicon film transistor adopts 4 or 5 road mask plate photoetching processes, and low-temperature polysilicon film transistor need adopt 9 road mask plate photoetching processes usually, and the increase of its process complexity makes the cost of manufacture of the display device that the employing low-temperature polysilicon film transistor drives rise; Its yields descends, and has influenced the competitiveness of the display device of low temperature polycrystal film transistor silicon driving.
The utility model content
In view of this, be necessary to provide a kind of manufacture craft simple and help promoting the low-temperature polysilicon film transistor array base palte of yields.
A kind of thin-film transistor array base-plate comprises that at least one has the substrate of first surface and is formed at the first film transistor, second thin-film transistor, storage capacitance, the gate insulation layer on the first surface of said substrate; And the said the first film transistor and second thin-film transistor are dissimilar thin-film transistors; Said substrate comprises first area, second area, the 3rd zone; Said the first film transistor is positioned at said first area; Said second thin-film transistor is positioned at second area; Said storage capacitance is positioned at said the 3rd zone; Said the first film transistor comprises first grid, first source electrode, first drain electrode and first channel region, and said second thin-film transistor comprises second grid, second source electrode, second drain electrode, second channel region and low-doped source-drain area, and said storage capacitance comprises electrode; Said first source electrode and first drain electrode are processed by the ion of the polysilicon layer doping first kind; Said second source electrode and second drain electrode are processed by the mix ion of second type of polysilicon layer, and said first grid is processed in different photoetching processes by same grid conductive layer with second grid, and the electrode of said second grid and storage capacitance is processed in same photoetching process in the lump; The said first grid and first source electrode and first drain electrode are opened through said gate insulation layer insulation, and the said second grid and second source electrode and second drain electrode are opened through said gate insulation layer insulation; Said first channel region and second channel region are by not mixing or lightly doped polysilicon layer formation; Said first channel region is between said first source electrode and first drain electrode, under the said first grid, and said second channel region is between said second source electrode and second drain electrode, under the said second grid; Said low doping source drain region is between said second source electrode and said second channel region and between said second drain electrode and second channel region.
In the said thin-film transistor array base-plate that the utility model provides; Said thin-film transistor array base-plate at least also comprises second insulating barrier, first source wiring, first drain electrode wiring, second source wiring, second drain electrode wiring, the 3rd wiring; And said first source wiring and second drain electrode wiring electrically connect with said first source electrode and first drain electrode respectively; Said second source wiring and second drain electrode wiring electrically connect with said second source electrode and second drain electrode respectively; Said storage capacitance at least also comprises the polysilicon high-doped zone; This polysilicon high-doped zone is by polysilicon doping or part a kind of the processing in first, second type ion of mixing; The electrode of itself and said storage capacitance is opened through said gate insulation layer insulation, and said the 3rd wiring electrically connects with said polysilicon high-doped zone, and said the 3rd wiring is opened through said second insulating barrier insulation with the electrode of said storage capacitance; Open through said second insulating barrier insulation between said first source wiring and first drain electrode wiring and the first grid, open through said second insulating barrier insulation between said second source wiring and second drain electrode wiring and the second grid.
In the said thin-film transistor array base-plate that the utility model provides; Said thin-film transistor array base-plate at least also comprises pixel electrode, the 3rd insulating barrier; The said pixel electrode and said first or second drain electrode wiring electrically connect, and this pixel electrode is opened through said the 3rd insulating barrier and said the 3rd wiring insulation.
In the thin-film transistor array base-plate that the utility model provides, adopt 7 road photoetching processes, compared with prior art, its process complexity is low, can enhance productivity, and improves yield of products.In addition, high-concentration dopant zones such as the transistorized source electrode of said the first film, drain electrode all form through self-registered technology, and its parasitic capacitance is little; The source-drain area 202a of low concentration forms through self-registered technology, and its size is less, good uniformity.
Description of drawings
To combine accompanying drawing and embodiment that the utility model is described further below, in the accompanying drawing:
Fig. 1 a to 1j is the making schematic flow sheet of the preferred embodiments thin-film transistor array base-plate that provides of the utility model.
The making schematic flow sheet of another preferred embodiments thin-film transistor array base-plate that Fig. 2 provides for the utility model.
Fig. 3 a, 3b are the making schematic flow sheet of the thin-film transistor array base-plate of the 3rd preferred embodiments that provides of the utility model.
Embodiment
For the thin-film transistor array base-plate that explanation the utility model provides, set forth in detail below in conjunction with Figure of description.
Please consult Fig. 1 a to 1j simultaneously, the making schematic flow sheet of the thin-film transistor array base-plate of the preferred embodiments that it provides for the utility model.Thin-film transistor array base-plate generally includes a plurality of thin-film transistors; Be that example describes only in this execution mode to make two types thin-film transistor; In these two kinds of thin-film transistors; The first film transistor is a P type thin-film transistor, and second thin-film transistor is a N type thin-film transistor.Said thin-film transistor array base-plate 10 is shown in Fig. 1 a; It comprises the substrate 100 with first surface 109; This substrate 100 also comprises first area 101, second area 102 and the 3rd zone 103; Said first area 101 is the first film transistor area, and said second area 102 is second TFT regions, and said the 3rd zone 103 is the storage capacitance zone.This substrate 100 is processed by transparent material, and it can be a resin substrate, also can be glass substrate.
See also Fig. 1 b, on said resilient coating 110 and polysilicon layer 200, form gate insulation layer 300 and grid conductive layer 310.Said gate insulation layer 300 is processed by the oxide or the nitride of silicon, and said grid conductive layer 310 is by metal or metal alloy material (like molybdenum or molybdenum aluminium alloy) or owing to multiple layer metal, metal alloy, transparent conductive material are processed.Coating one second photoresist layer (not shown) on said grid conductive layer 310; And comprise that through one transmission region 922,920 pairs of said second photoresist layers of semi-transparent regional 923, light tight regional 921 second mask carry out photoetching, development; Grid wiring (not shown) described in the zone, silicon island of second thin-film transistor described in the grid wiring (not shown) in the transistorized first grid of the first film described in the said light tight regional 921 corresponding said first areas 101 and this first area 101, the said second area 102 and the grid wiring (not shown) in this second area 102, said the 3rd zone 103 in storage capacitance zone and the 3rd zone 103; The transistorized source drain region of the first film described in the said semi-transparent regional 923 corresponding said first areas 101, the remainder on the first surface of said transmission region 922 corresponding said substrates.Said second photoresist layer is through photoetching, the development of said second mask 920; Obtain the second photoresist pattern; In this second photoresist pattern; Be removed with said transmission region 922 corresponding part second photoresist layers; Part second photoresist layer corresponding with said semi-transparent regional 923 removed by part, be retained with said light tight regional 921 corresponding part second photoresist layers, and the thickness of part second photoresist layer corresponding with said semi-transparent regional 923 less than with the thickness of said light tight regional 921 corresponding part second photoresists.
The said interior grid conductive layer 310 in zone that is not coated with second photoresist layer is carried out etching; And gate insulation layer under it 300 and polysilicon layer 200 carried out etching, to define zone, the transistorized silicon island of the first film in the said first area 101, the zone, silicon island, storage capacitance zone and the grid wiring in the All Ranges in the 3rd zone 103 of second thin-film transistor in the said second area 102.Carry out the plasma reduction processing for the second photoresist pattern then; Second photoresist layer corresponding with semi-transparent regional 923 of said second mask 920 removed; And the thickness of second photoresist layer corresponding with light tight regional 921 of said second mask 920 is reduced; Be that second photoresist layer on the transistorized source drain region of said the first film is removed, the zone, silicon island of said second thin-film transistor and second photoresist layer on the storage capacitance zone are retained.
Said grid conductive layer 310 is carried out wet etching one time, define transistorized first grid 311 of said the first film and corresponding grid wiring, and the grid conductive layer 310 on the transistorized source drain region of said the first film is removed.Remove the zone, silicon island of said second thin-film transistor and second photoresist layer on the storage capacitance zone then; And the high concentration of carrying out a P type ion injects 380; Form the transistorized first source electrode 201s of the first film and the first drain electrode 201d in the said first area 101, and the polysilicon layer 200 that is covered by said first grid 311 forms the first channel region 201c.
See also Fig. 1 c; Side at the first surface 109 of said substrate 100 is coated with one the 3rd photoresist layer 370; The 3rd photoresist layer 370 covers and has been formed at all parts on the said first surface 109; And carry out a photoetching, development through 930 pairs of said the 3rd photoresist layers 370 of one the 3rd mask; Second grid and the grid wiring zone of the first film zone, transistorized silicon island and grid wiring zone in the said first area 101, second thin-film transistor in the said second area 102, the electrode and the grid wiring zone of the storage capacitance in said the 3rd zone 103 are covered by said the 3rd photoresist layer 370, and the 3rd photoresist layer 370 of remainder is removed.Then the grid conductive layer 310 that exposes is carried out wet etching one time; Grid conductive layer 310 on the source-drain electrode of said second thin-film transistor is removed, formed the second grid 312 of said second thin-film transistor, the electrode 313 and the corresponding grid wiring (not shown) of storage capacitance.Because the lateral etches characteristic of wet etching, the size of second grid 312 that makes said second thin-film transistor is less than the size of said the 3rd photoresist layer 370 of position part on it.Said polysilicon layer 200 is carried out the high concentration of a N type ion and inject 380; Form the second source electrode 202s and the second drain electrode 202d of second thin-film transistor in the said second area 102 and form the polysilicon high-doped zone 203s in the storage capacitance zone, and formed the second channel region 202c by second grid 312 region covered.
Because the second grid of the transistorized first grid 311 of said the first film and wiring (not shown) and said second thin-film transistor and wiring thereof are not processed in same technology in the lump; For guaranteeing that both are in the fabrication error allowed band; Can realize effective connection; Therefore, a splicing ear need be set in both junctions.See also Fig. 1 d, in the first area 101 with second area 102 intersections, second mask 920 has light tight regional 9211, and makes the grid wirings in the said first area 101 have splicing ear.Have light tight regional 9311 on said the 3rd mask 930; The size of light tight regional 9211 on said second mask 920 is greater than light tight regional 9311 on said the 3rd mask 930; And has surplus 92131; Promptly in said first area 101 and second area 102 intersections, the size of the grid wiring in the said first area 101 is greater than the size of the grid wiring in the said second area 102.
See also Fig. 1 e; Behind source electrode 202s that forms said second thin-film transistor and drain electrode 202d; Remove the 3rd remaining photoresist layer 370; The low concentration that carries out a N type ion then injects 381, and makes the polysilicon layer 200 that is not covered by said second grid 312 in the second area 102 form low-doped source-drain area 202a.
See also Fig. 1 f; Side at the first surface 109 of substrate 100 forms second insulating barrier 400; And this second insulating barrier 400 covers all elements on said first area 101, second area 102 and the 3rd zone 103, and on said second insulating barrier 400 coating one the 4th photoresist layer (not shown).Have light tight regional 941 through one and carry out photoetching, development with 940 pairs of said the 4th photoresist layers of the 4th mask of transmission region 942; Form the 4th photoresist layer pattern; And according to said second insulating barrier 400 of the 4th photoresist layer pattern etching and gate insulation layer 300; High-doped zone and grid wiring (not shown) in first area 101, second area 102, the 3rd zone 103 are come out; Even the polysilicon high-doped zone 203s in second source electrode 202s of second thin-film transistor in the transistorized first source electrode 201s of the first film in the said first area 101 and the first drain electrode 201d, the said second area 102 and the storage capacitance zone in the second drain electrode 202d and the 3rd zone 103 comes out, remove the 4th remaining photoresist layer then.Said second insulating barrier 400 adopts same material to be made with said gate insulation layer 300, therefore, in etching second insulating barrier 400, can accomplish the etching of the gate insulation layer 300 of correspondence position.
See also Fig. 1 g, metal level is leaked in the source that on said second insulating barrier 400, makes, and leaks coating one the 5th photoresist layer (not shown) on the metal level in this source.Have transmission region 952 through one and carry out photoetching, development with 950 pairs of said the 5th photoresist layers of the 5th mask of light tight regional 951; And the said source of etching leaks metal level, the second source wiring 412s that form the first source wiring 411s that links to each other with transistorized first source electrode of the first film and first drain electrode and the first drain electrode wiring 411d, links to each other with second source electrode and second drain electrode of second thin-film transistor and the second drain electrode wiring 412d, the 3rd 413s that connects up that links to each other with the polysilicon high-doped zone 203s of storage capacitance.Said source leakage metal level adopts with said grid conductive layer 310 identical materials such as metal molybdenum, aluminium etc. to be processed.
See also Fig. 1 h, form one the 3rd insulating barrier 500, and the 3rd insulating barrier 500 covers all elements in said first area 101, second area 102 and the 3rd zone 103 in a side of the first surface 109 of said substrate 100.Coating one the 6th photoresist layer (not shown) on said the 3rd insulating barrier 500; And carry out photoetching, development through 960 pairs of said the 6th photoresist layers of one the 6th mask; Then said the 3rd insulating barrier 500 is carried out etching, the said second drain electrode wiring 412d is come out.Said the 3rd insulating barrier 500 adopts with said gate insulation layer 300 and second insulating barrier, 400 identical materials to be processed.
See also Fig. 1 i, form a pixel electrode layer in a side of the first surface 109 of said substrate 100, this pixel electrode layer covers all elements in said first area 101, second area 102 and the 3rd zone 103.Coating one the 7th photoresist layer (not shown) on said pixel electrode layer; And carry out photoetching, development through 970 pairs of said the 7th photoresist layers of one the 7th mask; Then said pixel electrode layer is carried out etching, form pixel electrode 510 and local wiring (not shown).
See also Fig. 1 j; Because in above-mentioned manufacturing process; Be positioned at said polysilicon layer 200 parts to beginning under the electrode 313 of said first grid 311, second grid 312 and storage capacitance to existing eventually, cause the second channel region 202c of the transistorized first channel region 201c of said the first film and second thin-film transistor to extend outside said first, second thin-film transistor structure.For addressing this problem; Need be disconnected 200 quarters to the polysilicon layer outside said first, second thin-film transistor structure, under said first grid and the second grid; Be that first-selection need be carved said first grid and second grid disconnected; Carve the part polysilicon layer under it then, will carve the grid wiring connection corresponding of disconnected first grid, second grid through the bridging mode then with it.As the first grid that connects partition and the part of wiring thereof; Can in the process that forms first source wiring and first drain electrode wiring, process in the lump; Simultaneously; As the second grid that connects partition and the part of wiring thereof, also can in the process that forms first source wiring, first drain electrode wiring, process in the lump.
In the above-mentioned making flow process of the thin-film transistor array base-plate that the utility model provides, adopt 7 road photoetching processes, compared with prior art, its process complexity is low, can enhance productivity, and improves yield of products.In addition, high-concentration dopant zones such as the transistorized source electrode of said the first film, drain electrode all form through self-registered technology, and its parasitic capacitance is little; The source-drain area 202a of low concentration forms through self-registered technology, and its size is less, good uniformity.
See also Fig. 2; The making schematic flow sheet of the thin-film transistor array base-plate of another preferred embodiments that it provides for the utility model; In the making schematic flow sheet of the thin-film transistor of the preferred embodiments in Fig. 1 a to 1i; After accomplishing the said first source wiring 411s and the first drain electrode wiring 411d, the second source wiring 412s and the second drain electrode wiring 412d, the 3rd wiring 413s; Side at the first surface 109 of said substrate 100 forms said pixel electrode layer and is formed at the 8th photoresist layer on the said pixel electrode layer, and carries out photoetching, development through 970 pairs of said the 8th photoresist layers of said the 7th mask, and said pixel electrode layer is carried out etching; Form pixel electrode 510, the said pixel electrode 510 and the second drain electrode wiring 412d and the 3rd wiring 413s electrically connect.Therefore, in this execution mode, only need adopt 6 road photoetching processes, promptly can be made into thin-film transistor array base-plate, its process complexity further reduces, and helps further enhancing productivity and the product yields.
For need not to carry out the making that channel doping is adjusted the thin-film transistor array base-plate of threshold voltage; Can omit the photoetching process first time in the making schematic flow sheet of thin-film transistor of the preferred embodiments among Fig. 1 a to 1i, promptly only adopt 5 road photoetching processes to accomplish the making of said thin-film transistor array base-plate.
Or be; Shown in Fig. 3 a, 3b; In the making schematic flow sheet of the thin-film transistor of the preferred embodiments in Fig. 1 a to 1i; After the etching of accomplishing said second insulating barrier 400, form pixel electrode layer successively in a side of the first surface 109 of said substrate 100, metal level, the 9th photoresist layer 990 are leaked in the source, and carry out photoetching, development through 980 pairs of said the 9th photoresist layers 990 of one the 8th mask; Said the 8th mask 980 has light tight regional 981, transmission region 982, semi-transparent regional 983; The zone at the said light tight regional 981 corresponding above-mentioned first source wiring 411s and the first drain electrode wiring 411d, the second source wiring 412s and second drain electrode wiring 412d place, the zone at said semi-transparent regional 983 corresponding pixel electrodes 510 places, all the other corresponding light tight zones, zone.Therefore; After carrying out photoetching through 980 pairs of said the 9th photoresist layers 990 of said the 8th mask and developing, the thickness of the 9th photoresist layer 990 on the zone at the said first source wiring 411s and the first drain electrode wiring 411d, the second source wiring 412s and second drain electrode wiring 412d place is greater than the thickness of the 9th photoresist layer 990 on the zone at said pixel electrode 510 places.Then, said source leakage metal level and the pixel electrode layer that does not cover the 9th photoresist layer 990 carried out etching, form the said first source wiring 411s and the first drain electrode wiring 411d, the second source wiring 412s and the second drain electrode wiring 412d.
Said the 9th photoresist layer 990 is carried out the reduction processing of plasma; The 9th photoresist layer on the pixel electrode is removed; And the thickness of the 9th photoresist layer on the said first source wiring 411s and the first drain electrode wiring 411d, the second source wiring 412s and the second drain electrode wiring 412d is reduced; Then metal level is leaked in said source and carry out etching, and can not etch into said pixel electrode layer, and then form said pixel electrode 510.In this execution mode, only adopt 5 road photoetching processes can accomplish the making of said thin-film transistor array base-plate, can effectively enhance productivity and the product yields.If for need not to carry out the making that channel doping is adjusted the thin-film transistor array base-plate of threshold voltage; Can omit the photoetching process first time in the making schematic flow sheet of thin-film transistor of the preferred embodiments among Fig. 1 a to 1i, promptly only adopt 4 road photoetching processes to accomplish the making of said thin-film transistor array base-plate.
The preferred embodiments of the thin-film transistor array base-plate that more than provides for the utility model; Can not be interpreted as restriction to the utility model rights protection scope; Those skilled in the art should know, and under the prerequisite that does not break away from the utility model design, also can do multiple improvement or replacement; These all improvement or replacement all should be in the rights protection scopes of the utility model, and promptly the rights protection scope of the utility model should be as the criterion with claim.
Claims (3)
1. thin-film transistor array base-plate; At least comprise that one has the substrate of first surface and is formed at the first film transistor, second thin-film transistor, storage capacitance, the gate insulation layer on the first surface of said substrate; And the said the first film transistor and second thin-film transistor are dissimilar thin-film transistors; Said substrate comprises first area, second area, the 3rd zone; Said the first film transistor is positioned at said first area; Said second thin-film transistor is positioned at second area, and said storage capacitance is positioned at said the 3rd zone, and said the first film transistor comprises first grid, first source electrode, first drain electrode and first channel region; Said second thin-film transistor comprises second grid, second source electrode, second drain electrode, second channel region and low-doped source-drain area; Said storage capacitance comprises electrode, and said first source electrode and first drain electrode are processed by the ion of the polysilicon layer doping first kind, and said second source electrode and second drain electrode are processed by the mix ion of second type of polysilicon layer; Said first grid is processed in different photoetching processes by same grid conductive layer with second grid, and the electrode of said second grid and storage capacitance can be processed in same photoetching process in the lump; The said first grid and first source electrode and first drain electrode are opened through said gate insulation layer insulation, and the said second grid and second source electrode and second drain electrode are opened through said gate insulation layer insulation; Said first channel region and second channel region are by not mixing or lightly doped polysilicon layer formation; Said first channel region is between said first source electrode and first drain electrode, under the said first grid, and said second channel region is between said second source electrode and second drain electrode, under the said second grid; Said low doping source drain region is between said second source electrode and said second channel region and between said second drain electrode and second channel region.
2. thin-film transistor array base-plate as claimed in claim 1; It is characterized in that: said thin-film transistor array base-plate at least also comprises second insulating barrier, first source wiring, first drain electrode wiring, second source wiring, second drain electrode wiring, the 3rd wiring; And said first source wiring and second drain electrode wiring electrically connect with said first source electrode and first drain electrode respectively; Said second source wiring and second drain electrode wiring electrically connect with said second source electrode and second drain electrode respectively; Said storage capacitance at least also comprises the polysilicon high-doped zone; This polysilicon high-doped zone is by polysilicon doping or part a kind of the processing in first, second type ion of mixing; The electrode of itself and said storage capacitance is opened through said gate insulation layer insulation, and said the 3rd wiring electrically connects with said polysilicon high-doped zone, and said the 3rd wiring is opened through said second insulating barrier insulation with the electrode of said storage capacitance; Open through said second insulating barrier insulation between said first source wiring and first drain electrode wiring and the first grid, open through said second insulating barrier insulation between said second source wiring and second drain electrode wiring and the second grid.
3. thin-film transistor array base-plate as claimed in claim 2; It is characterized in that: thin-film transistor array base-plate at least also comprises pixel electrode, the 3rd insulating barrier; The pixel electrode and said first or second drain electrode wiring electrically connect, and this pixel electrode is opened through said the 3rd insulating barrier and said the 3rd wiring insulation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120544641 CN202423290U (en) | 2011-12-22 | 2011-12-22 | Thin film transistor array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120544641 CN202423290U (en) | 2011-12-22 | 2011-12-22 | Thin film transistor array substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202423290U true CN202423290U (en) | 2012-09-05 |
Family
ID=46748022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201120544641 Expired - Fee Related CN202423290U (en) | 2011-12-22 | 2011-12-22 | Thin film transistor array substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202423290U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522410A (en) * | 2011-12-22 | 2012-06-27 | 深圳莱宝高科技股份有限公司 | TFT array substrate and manufacturing method thereof |
-
2011
- 2011-12-22 CN CN 201120544641 patent/CN202423290U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522410A (en) * | 2011-12-22 | 2012-06-27 | 深圳莱宝高科技股份有限公司 | TFT array substrate and manufacturing method thereof |
| CN102522410B (en) * | 2011-12-22 | 2016-03-02 | 深圳莱宝高科技股份有限公司 | A kind of thin-film transistor array base-plate and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102522410B (en) | A kind of thin-film transistor array base-plate and preparation method thereof | |
| US20200212153A1 (en) | Array substrate, manufacturing method thereof, and display apparatus | |
| US7985636B2 (en) | Method for fabricating low temperature poly-silicon thin film transistor substrate | |
| JPH07335903A (en) | Active matrix circuit | |
| US11355519B2 (en) | Array substrate, manufacturing method thereof, and display device | |
| CN105470197A (en) | Production method of low temperature poly silicon array substrate | |
| US20200321475A1 (en) | Manufacturing method for ltps tft substrate | |
| CN102651403A (en) | Thin film transistor, array substrate and manufacturing method of array substrate and display panel | |
| CN106098699A (en) | A kind of array base palte, its manufacture method, display floater and preparation method thereof | |
| US9735186B2 (en) | Manufacturing method and structure thereof of TFT backplane | |
| CN110620119A (en) | Array substrate and preparation method thereof | |
| JP4675680B2 (en) | Method for manufacturing thin film transistor substrate | |
| US6365444B2 (en) | Process for forming polycrystalline thin film transistor liquid crystal display | |
| CN105097552A (en) | Manufacturing methods of thin film transistor and array substrate, array substrate and display device | |
| US11869976B2 (en) | Thin film transistor and manufacturing method therefor, array substrate, and display device | |
| TWI375282B (en) | Thin film transistor(tft)manufacturing method and oled display having tft manufactured by the same | |
| CN101789434B (en) | Image display system and manufacturing method thereof | |
| US10957606B2 (en) | Manufacturing method of complementary metal oxide semiconductor transistor and manufacturing method of array substrate | |
| US10629746B2 (en) | Array substrate and manufacturing method thereof | |
| CN101740524A (en) | Method for manufacturing thin film transistor array substrate | |
| CN102522411B (en) | Thin film transistor (TFT), the array base palte using this thin film transistor (TFT) and preparation method thereof | |
| CN105551967B (en) | The production method of N-type TFT | |
| CN101834189A (en) | Image display system | |
| CN202423290U (en) | Thin film transistor array substrate | |
| KR20090103553A (en) | Method of manufacturing thin film transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120905 Termination date: 20201222 |