CN102522410B - A kind of thin-film transistor array base-plate and preparation method thereof - Google Patents
A kind of thin-film transistor array base-plate and preparation method thereof Download PDFInfo
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Abstract
The present invention relates to Display Technique field, particularly relate to a kind of thin-film transistor array base-plate.This thin-film transistor array base-plate at least comprises a substrate with first surface and the first film transistor be formed on the first surface of substrate, second thin-film transistor, storage capacitance, one gate insulation layer, and described the first film transistor and the second thin-film transistor are dissimilar thin-film transistor, described substrate comprises first area, second area, 3rd region, described the first film transistor is positioned at described first area, described second thin-film transistor is positioned at second area, described storage capacitance is positioned at described 3rd region, described the first film transistor comprises first grid, first source electrode, first drain electrode and the first channel region, described second thin-film transistor comprises second grid, second source electrode, second drain electrode, second channel region and low-doped source-drain area, described storage capacitance comprises polysilicon high-doped zone, electrode.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of thin-film transistor array base-plate and preparation method thereof.
Background technology
Thin-film transistor (TFT) is widely used in flat-panel display device, such as common at present liquid crystal display (LCD), and organic light emitting display (AMOLED).
Current effective sale based in the flat panel display product of TFT technology, the TFT device of use belongs to two classes substantially: amorphous silicon film transistor (a-SiTFT) and polycrystalline SiTFT.For the latter, according to the difference of its manufacturing process, low-temperature polysilicon film transistor (LTPSTFT) and high temperature polysilicon silicon thin film transistor (HTPSTFT) can be divided into again, be applicable to small-medium size display device and microsize display device (as perspective view image source) etc. respectively.
Relative to amorphous silicon film transistor, low-temperature polysilicon film transistor has plurality of advantages, two orders of magnitude as high in its mobility ratio amorphous silicon film transistor, the device of reduced size can realize stronger driving force, improve display device aperture opening ratio, be also more suitable for the active matrix organic light-emitting diode display floater needing current drives; And for example its threshold voltage is more stable, can meet the stability requirement of active matrix organic light-emitting diode display floater, and becomes the ideal chose driving active matrix organic light-emitting diode display floater; For another example, amorphous silicon film transistor can only form N-type device, and low-temperature polysilicon film transistor can form P type and N-type two kinds of complementary thin-film transistors, it is more flexible that this makes to utilize low-temperature polysilicon film transistor to form circuit on the glass substrate, also the way on coming true, thus reach the object simplifying peripheral drive circuit.Generally speaking, low-temperature polysilicon film transistor because having plurality of advantages, make that it is integrated at high-resolution, circuit, display device integrated in there is extensive use.
Relative to amorphous silicon film transistor, the manufacture craft more complicated of low-temperature polysilicon film transistor, generally speaking, amorphous silicon film transistor adopts 4 or 5 road mask plate photoetching processes, and low-temperature polysilicon film transistor needs employing 9 road mask plate photoetching process usually, the increase of its process complexity makes the cost of manufacture of the display device adopting low-temperature polysilicon film transistor to drive rise, its yields declines, and have impact on the competitiveness of the display device that low-temperature polysilicon thin-film transistor silicon drives.
Summary of the invention
In view of this, be necessary to provide a kind of manufacture craft simple and be conducive to promoting the low-temperature polysilicon film transistor array base palte of yields.
In addition, there is a need to provide a kind of manufacture craft simple and be conducive to promoting the many manufacture methods through thin-film transistor array base-plate of low temperature of yields.
A kind of thin-film transistor array base-plate at least comprises a substrate with first surface and the first film transistor be formed on the first surface of described substrate, second thin-film transistor, storage capacitance, one gate insulation layer, and described the first film transistor and the second thin-film transistor are dissimilar thin-film transistor, described substrate comprises first area, second area, 3rd region, described the first film transistor is positioned at described first area, described second thin-film transistor is positioned at second area, described storage capacitance is positioned at described 3rd region, described the first film transistor comprises first grid, first source electrode, first drain electrode and the first channel region, described second thin-film transistor comprises second grid, second source electrode, second drain electrode, second channel region and low-doped source-drain area, described storage capacitance comprises electrode, described first source electrode and the first drain electrode are made up of the ion of the doping polycrystalline silicon layer first kind, described second source electrode and the second drain electrode are made up of the ion of doping polycrystalline silicon layer Second Type, described first grid and second grid are made up in different photoetching process of same grid conductive layer, the electrode of described second grid and storage capacitance is made in the lump in same photoetching process, described first grid and the first source electrode and first are drained to be insulated by described gate insulation layer and open, and described second grid and the second source electrode and second are drained to be insulated by described gate insulation layer and open, described first channel region and the second channel region are by not adulterating or lightly doped polysilicon layer formation, described first channel region is between described first source electrode and the first drain electrode, under described first grid, and described second channel region is between described second source electrode and the second drain electrode, under described second grid, described low doping source drain region is between described second source electrode and described second channel region and described second to drain and between the second channel region, described storage capacitance at least also comprises polysilicon high-doped zone, this polysilicon high-doped zone is made up of polysilicon doping or the part one of adulterating in first, second types of ion, and the electrode of itself and described storage capacitance is insulated by described gate insulation layer and opens.
In described thin-film transistor array base-plate provided by the invention, described thin-film transistor array base-plate at least also comprises the second insulating barrier, first source wiring, first drain electrode wiring, second source wiring, second drain electrode wiring, 3rd wiring, and described first source wiring and the second drain electrode wiring drain with described first source electrode and first respectively and are electrically connected, described second source wiring and the second drain electrode wiring drain with described second source electrode and second respectively and are electrically connected, described storage capacitance at least also comprises polysilicon high-doped zone, this polysilicon high-doped zone is by polysilicon doping or part doping first, one in Second Type ion is made, the electrode of itself and described storage capacitance is insulated by described gate insulation layer and opens, and described 3rd wiring is electrically connected with described polysilicon high-doped zone, and described 3rd wiring is insulated by described second insulating barrier with the electrode of described storage capacitance and is opened, described first source wiring and being insulated by described second insulating barrier between the first drain electrode wiring and first grid is opened, described second source wiring and being insulated by described second insulating barrier between the second drain electrode wiring and second grid is opened.
In described thin-film transistor array base-plate provided by the invention, described thin-film transistor array base-plate at least also comprises pixel electrode, the 3rd insulating barrier, described pixel electrode and the described first or second drain electrode wiring are electrically connected, and this pixel electrode is opened by described 3rd insulating barrier and the described 3rd insulation of connecting up.
The manufacture method of thin-film transistor array base-plate comprises the following steps: provide the substrate that has a first surface, and it comprises first area, second area, the 3rd region; Form resilient coating and amorphous silicon layer successively at the first surface of described substrate, and described amorphous silicon layer is converted into polysilicon layer by an annealing process; Described polysilicon layer is formed a gate insulation layer, grid conductive layer, and one second photoresist layer is coated with on described grid conductive layer, by one comprise transmission region, semi-transparent region, light tight region the second mask photoetching is carried out to described second photoresist layer, obtain one second photoetching agent pattern; The grid conductive layer do not covered in the region of the second photoresist layer is etched, and the gate insulation layer under it and polysilicon layer are etched, define the storage capacitance region in the region, silicon island of the second thin-film transistor in the region, silicon island of the first film transistor in first area, described second area and the 3rd region; Carry out plasma reduction processing to the second photoresist layer, second photoresist layer corresponding with the semi-transparent region of the second mask is removed, and the thickness of second photoresist layer corresponding with described light tight region reduces; The grid conductive layer not covering described second photoresist layer is etched, define first grid and the grid wiring of described the first film transistor, remove remaining second photoresist layer, and the high concentration of carrying out the ion of a first kind is injected, form the first source electrode of described the first film transistor, the first drain electrode and the first channel region between the first source electrode and the first drain electrode; At the first side coating one the 3rd photoresist layer of the first surface of substrate, 3rd photoresist layer covers all elements in first, second and third region, and by one the 3rd mask, a photoetching is carried out to the 3rd photoresist layer, the region, silicon island of described the first film transistor, the second grid of the second thin-film transistor, the electrode in described storage capacitance region are covered by the 3rd photoresist layer, and the 3rd photoresist layer of remainder is removed; The grid conductive layer exposed is etched, the grid conductive layer on the source-drain electrode of the second thin-film transistor is removed, forms the grid wiring of the second grid of the second thin-film transistor, the electrode of storage capacitance and correspondence; The high concentration of described polysilicon layer being carried out to the ion of a Second Type is injected, the second source electrode and second forming described second thin-film transistor drains and forms the polysilicon high-doped zone in storage capacitance region, and is formed the second channel region by the region that described second grid covers; Remove the 3rd unnecessary photoresist layer, and the low concentration carrying out the ion of a Second Type injects, and makes not formed low-doped source-drain area by the polysilicon layer that described second grid covers in the second thin-film transistor; Form the second insulating barrier in the first surface side of substrate, this second insulating barrier covers all elements in first, second and third region described, and is coated with one the 4th photoresist layer over the second dielectric; By one the 4th mask, photoetching is carried out to described 4th photoresist layer, form the 4th photoresist layer pattern, and according to the 4th photoresist layer pattern described second insulating barrier of etching and gate insulation layer, high-doped zone in first, second and third region and wiring thereof are come out, even if come out in the first source electrode of described the first film transistor and the first drain electrode, the second source electrode of described second thin-film transistor and the polysilicon high-doped zone in the second drain electrode and described storage capacitance region, then remove the 4th remaining photoresist layer.
In the above-mentioned Making programme of thin-film transistor array base-plate provided by the invention, adopt 7 road photoetching processes, compared with prior art, its process complexity is low, can enhance productivity, and improves the yields of product.In addition, source electrode, the contour doped regions that drains of described the first film transistor are all formed by self-registered technology, and its parasitic capacitance is little; The source-drain area 202a of low concentration is formed by self-registered technology, and its size is less, and uniformity is good.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:
Fig. 1 a to 1j is the Making programme schematic diagram of a better embodiment thin-film transistor array base-plate provided by the invention.
Fig. 2 is the Making programme schematic diagram of another better embodiment thin-film transistor array base-plate provided by the invention.
Fig. 3 a, 3b are the Making programme schematic diagram of the thin-film transistor array base-plate of the 3rd better embodiment provided by the invention.
Fig. 4 is the manufacture method schematic flow sheet of the thin-film transistor array base-plate shown in Fig. 1 a to 1i.
Embodiment
For thin-film transistor array base-plate provided by the invention and preparation method thereof is described, be described in detail below in conjunction with Figure of description.
Please refer to Fig. 1 a to 1j, it is the Making programme schematic diagram of the thin-film transistor array base-plate of a better embodiment provided by the invention.Thin-film transistor array base-plate generally includes multiple thin-film transistor, only be described for the thin-film transistor making two types in present embodiment, in these two kinds of thin-film transistors, the first film transistor is a P-type TFT, and the second thin-film transistor is a N-type TFT.Described thin-film transistor array base-plate 10 as shown in Figure 1a, it comprises the substrate 100 with first surface 109, this substrate 100 also comprises first area 101, second area 102 and the 3rd region 103, described first area 101 is the first film transistor area, described second area 102 is the second TFT regions, and described 3rd region 103 is storage capacitance region.This substrate 100 is made up of transparent material, and it can be resin substrate, also can be glass substrate.
Resilient coating 110 and amorphous silicon layer is formed successively at the first surface 109 of this substrate 100.Described resilient coating 110 is made up of the oxide of silicon or nitride, and described amorphous silicon layer is converted into polysilicon layer 200 by annealing process, and this annealing process can be Ultra-Violet Laser scanning, Solid State Laser scanning, thermal anneal process or other annealing processs.Described polysilicon layer 200 is coated with one first photoresist layer 170, and utilize one first mask 910 to carry out photoetching, development to this first photoresist layer 170, the first photoresist layer 170 in second area 102 is removed, and retains the first photoresist layer 170 in first area 101 and the 3rd region 103.Then, described second area 102 is carried out to the P type ion implantation 180 of a low concentration, form channel doping; And after completing the P type ion doping of described low concentration, remove the first photoresist layer 170 on described first area 101 and the 3rd region 103.
Refer to Fig. 1 b, described resilient coating 110 and polysilicon layer 200 are formed gate insulation layer 300 and grid conductive layer 310.Described gate insulation layer 300 is made up of the oxide of silicon or nitride, and described grid conductive layer 310 is made by metal or metal alloy material (as molybdenum or molybdenum aluminium alloy) or due to multiple layer metal, metal alloy, transparent conductive material.Described grid conductive layer 310 is coated with one second photoresist layer (not shown), and comprise transmission region 922 by one, semi-transparent region 923, second mask 920 in light tight region 921 carries out photoetching to described second photoresist layer, development, grid wiring (not shown) in the first grid of the first film transistor described in corresponding described first area 101, described light tight region 921 and this first area 101, grid wiring (not shown) in the region, silicon island of the second thin-film transistor described in described second area 102 and this second area 102, grid wiring (not shown) in storage capacitance region described in described 3rd region 103 and the 3rd region 103, the source drain region of the first film transistor described in corresponding described first area 101, described semi-transparent region 923, remainder on the first surface of the corresponding described substrate of described transmission region 922.Described second photoresist layer is by the photoetching of described second mask 920, development, obtain the second photoetching agent pattern, in this second photoetching agent pattern, part second photoresist layer corresponding with described transmission region 922 is removed, part second photoresist layer corresponding with described semi-transparent region 923 is partially removed, part second photoresist layer corresponding with described light tight region 921 is retained, and the thickness of part second photoresist layer corresponding with described semi-transparent region 923 is less than the thickness of part second photoresist corresponding with described light tight region 921.
Grid conductive layer 310 in the described region not being coated with the second photoresist layer is etched, and the gate insulation layer 300 under it and polysilicon layer 200 are etched, to define the storage capacitance region in the region, silicon island of the second thin-film transistor in the region, silicon island of the first film transistor in described first area 101, described second area 102, the 3rd region 103 and the grid wiring in all regions.Then plasma reduction processing is carried out for the second photoetching agent pattern, second photoresist layer corresponding with the semi-transparent region 923 of described second mask 920 is removed, and the thickness of second photoresist layer corresponding with the light tight region 921 of described second mask 920 is reduced, the second photoresist layer in the source drain region of i.e. described the first film transistor is removed, and the second photoresist layer on the region, silicon island of described second thin-film transistor and storage capacitance region is retained.
A wet etching is carried out to described grid conductive layer 310, defines the first grid 311 of described the first film transistor and corresponding grid wiring, and the grid conductive layer 310 in the source drain region of described the first film transistor is removed.Then the second photoresist layer on the region, silicon island of described second thin-film transistor and storage capacitance region is removed, and the high concentration of carrying out a P type ion injects 380, form the first source electrode 201s and first drain electrode 201d of the first film transistor in described first area 101, and formed the first channel region 201c by the polysilicon layer 200 that described first grid 311 covers.
Refer to Fig. 1 c, at the side of the first surface 109 of described substrate 100 coating one the 3rd photoresist layer 370, 3rd photoresist layer 370 covers all parts be formed on described first surface 109, and by one the 3rd mask 930, a photoetching is carried out to described 3rd photoresist layer 370, development, make region, silicon island and the grid wiring region of the first film transistor in described first area 101, the second grid of the second thin-film transistor in described second area 102 and grid wiring region, the electrode of the storage capacitance in described 3rd region 103 and grid wiring region are covered by described 3rd photoresist layer 370, 3rd photoresist layer 370 of remainder is removed.Then a wet etching is carried out to the grid conductive layer 310 exposed, grid conductive layer 310 on the source-drain electrode of described second thin-film transistor is removed, forms the grid wiring (not shown) of the second grid 312 of described second thin-film transistor, the electrode 313 of storage capacitance and correspondence.Due to the lateral etches characteristic of wet etching, the size of the second grid 312 of described second thin-film transistor is made to be less than the size of described 3rd photoresist layer 370 of the part be located thereon.The high concentration of described polysilicon layer 200 being carried out to a N-type ion injects 380, the second source electrode 202s and the second drain electrode 202d forming the second thin-film transistor in described the second area 102 and polysilicon high-doped zone 203s formed in storage capacitance region, and formed the second channel region 202c by the region that second grid 312 covers.
Because the first grid 311 of described the first film transistor and the second grid and connecting up of wiring (not shown) and described second thin-film transistor thereof are not made in the lump in same technique, for guaranteeing that both are in fabrication error allowed band, effective connection can be realized, therefore, need to arrange a splicing ear in both junctions.Refer to Fig. 1 d, in first area 101 and second area 102 intersection, the second mask 920 has light tight region 9211, and makes the grid wiring in described first area 101 have splicing ear.Described 3rd mask 930 has light tight region 9311, the size in the light tight region 9211 on described second mask 920 is greater than the light tight region 9311 on described 3rd mask 930, and there is surplus 92131, namely in described first area 101 and second area 102 intersection, the size of the grid wiring in described first area 101 is greater than the size of the grid wiring in described second area 102.
Refer to Fig. 1 e, after the source electrode 202s forming described second thin-film transistor and drain electrode 202d, remove the 3rd remaining photoresist layer 370, then the low concentration carrying out a N-type ion injects 381, and makes not formed low-doped source-drain area 202a by the polysilicon layer 200 that described second grid 312 covers in second area 102.
Refer to Fig. 1 f, the second insulating barrier 400 is formed in the side of the first surface 109 of substrate 100, and this second insulating barrier 400 covers all elements on described first area 101, second area 102 and the 3rd region 103, and be coated with one the 4th photoresist layer (not shown) on described second insulating barrier 400.The 4th mask 940 having light tight region 941 and transmission region 942 by one carries out photoetching to described 4th photoresist layer, development, form the 4th photoresist layer pattern, and according to the 4th photoresist layer pattern described second insulating barrier 400 of etching and gate insulation layer 300, make first area 101, second area 102, high-doped zone in 3rd region 103 and grid wiring (not shown) come out, even if the first source electrode 201s of the first film transistor in described first area 101 and first drain electrode 201d, second source electrode 202s of the second thin-film transistor in described second area 102 and second drain electrode 202d, and the 3rd the polysilicon high-doped zone 203s in storage capacitance region in region 103 come out, then the 4th remaining photoresist layer is removed.Described second insulating barrier 400 adopts same material to be made with described gate insulation layer 300, therefore, while etching second insulating barrier 400, can complete the etching of the gate insulation layer 300 of correspondence position.
Refer to Fig. 1 g, described second insulating barrier 400 makes a source and drain metal level, and be coated with one the 5th photoresist layer (not shown) on this source and drain metal level.The 5th mask 950 having transmission region 952 and light tight region 951 by one carries out photoetching, development to described 5th photoresist layer, and etch described source and drain metal level, formed with the first film transistor the first source electrode and first to drain the first source wiring 411s of being connected and the first drain electrode wiring 411d, to drain with second source electrode and second of the second thin-film transistor the second source wiring 412s of being connected and the second drain electrode wiring 412d, the 3rd connecting up 413s of being connected with the polysilicon high-doped zone 203s of storage capacitance.Described source and drain metal level adopts material such as metal molybdenum, the aluminium etc. identical with described grid conductive layer 310 to make.
Refer to Fig. 1 h, form one the 3rd insulating barrier 500 in the side of the first surface 109 of described substrate 100, and the 3rd insulating barrier 500 covers all elements in described first area 101, second area 102 and the 3rd region 103.Described 3rd insulating barrier 500 is coated with one the 6th photoresist layer (not shown), and by one the 6th mask 960, photoetching, development are carried out to described 6th photoresist layer, then described 3rd insulating barrier 500 is etched, described second drain electrode wiring 412d is come out.Described 3rd insulating barrier 500 adopts the material identical with the second insulating barrier 400 with described gate insulation layer 300 to make.
Refer to Fig. 1 i, form a pixel electrode layer in the side of the first surface 109 of described substrate 100, this pixel electrode layer covers all elements in described first area 101, second area 102 and the 3rd region 103.Described pixel electrode layer is coated with one the 7th photoresist layer (not shown), and by one the 7th mask 970, photoetching, development are carried out to described 7th photoresist layer, then described pixel electrode layer is etched, form pixel electrode 510 and local wiring (not shown).
Refer to Fig. 1 j, due in above-mentioned manufacturing process, described polysilicon layer 200 part be positioned under the electrode 313 of described first grid 311, second grid 312 and storage capacitance exists to beginning to whole, causes the first channel region 201c of described the first film transistor and the second channel region 202c of the second thin-film transistor to extend outside first, second thin-film transistor structure described.For solving this problem, need to break quarter to the polysilicon layer 200 outside first, second thin-film transistor structure described, under described first grid and second grid, namely described first grid and second grid are carved disconnected by first-selected needs, then carve the partial polysilicon layer under it, then will carve the first grid broken, the grid wiring connection that second grid is corresponding with it by bridging mode.As the part connecting first grid and the wiring thereof cut off, can make in the lump in the process of formation first source wiring and the first drain electrode wiring, simultaneously, as the part connecting second grid and the wiring thereof cut off, also can make in the lump in the process of formation first source wiring, the first drain electrode wiring.
In the above-mentioned Making programme of thin-film transistor array base-plate provided by the invention, adopt 7 road photoetching processes, compared with prior art, its process complexity is low, can enhance productivity, and improves the yields of product.In addition, source electrode, the contour doped regions that drains of described the first film transistor are all formed by self-registered technology, and its parasitic capacitance is little; The source-drain area 202a of low concentration is formed by self-registered technology, and its size is less, and uniformity is good.
Refer to Fig. 2, it is the Making programme schematic diagram of the thin-film transistor array base-plate of another better embodiment provided by the invention, in the Making programme schematic diagram of the thin-film transistor of the better embodiment in Fig. 1 a to 1i, when completing described first source wiring 411s and the first drain electrode wiring 411d, second source wiring 412s and the second drain electrode wiring 412d, after 3rd wiring 413s, form described pixel electrode layer in the side of the first surface 109 of described substrate 100 and be formed at the 8th photoresist layer on described pixel electrode layer, and by described 7th mask 970, photoetching is carried out to described 8th photoresist layer, development, and described pixel electrode layer is etched, form pixel electrode 510, described pixel electrode 510 and the second drain electrode wiring 412d and the 3rd 413s that connects up is electrically connected.Therefore, in present embodiment, only need employing 6 road photoetching process, namely can be made into thin-film transistor array base-plate, its process complexity reduces further, is conducive to enhancing productivity further and product yields.
For the making carrying out the thin-film transistor array base-plate of regulating valve threshold voltage without the need to carrying out channel doping, the first time photoetching process in the Making programme schematic diagram of the thin-film transistor of the better embodiment in Fig. 1 a to 1i can be omitted, namely only adopt 5 road photoetching processes to complete the making of described thin-film transistor array base-plate.
Or be, as Fig. 3 a, shown in 3b, in the Making programme schematic diagram of the thin-film transistor of the better embodiment in Fig. 1 a to 1i, when after the etching completing described second insulating barrier 400, pixel electrode layer is formed successively in the side of the first surface 109 of described substrate 100, source and drain metal level, 9th photoresist layer 990, and by one the 8th mask 980, photoetching is carried out to described 9th photoresist layer 990, development, described 8th mask 980 has light tight region 981, transmission region 982, semi-transparent region 983, the corresponding above-mentioned first source wiring 411s and the first drain electrode wiring 411d in described light tight region 981, the region at the second source wiring 412s and the second drain electrode wiring 412d place, the region at corresponding pixel electrodes 510 place, described semi-transparent region 983, corresponding light tight region, all the other regions.Therefore, after carrying out photoetching and development by described 8th mask 980 to described 9th photoresist layer 990, the thickness of the 9th photoresist layer 990 on the region at described first source wiring 411s and the first drain electrode wiring 411d, the second source wiring 412s and the second drain electrode wiring 412d place is greater than the thickness of the 9th photoresist layer 990 on the region at described pixel electrode 510 place.Then, the described source and drain metal level and pixel electrode layer not covering the 9th photoresist layer 990 is etched, form described first source wiring 411s and the first drain electrode wiring 411d, the second source wiring 412s and the second drain electrode wiring 412d.
Described 9th photoresist layer 990 is carried out to the reduction processing of plasma, the 9th photoresist layer on pixel electrode is removed, and the thickness of the 9th photoresist layer on described first source wiring 411s and the first drain electrode wiring 411d, the second source wiring 412s and the second drain electrode wiring 412d is reduced, then described source and drain metal level is etched, and described pixel electrode layer can not be etched into, and then form described pixel electrode 510.In the present embodiment, only adopt 5 road photoetching processes can complete the making of described thin-film transistor array base-plate, can effectively enhance productivity and product yields.If for the making carrying out the thin-film transistor array base-plate of regulating valve threshold voltage without the need to carrying out channel doping, the first time photoetching process in the Making programme schematic diagram of the thin-film transistor of the better embodiment in Fig. 1 a to 1i can be omitted, namely only adopt 4 road photoetching processes to complete the making of described thin-film transistor array base-plate.
As shown in Fig. 4 a, 4b, it is the manufacture method schematic flow sheet of the thin-film transistor array base-plate shown in Fig. 1 a to 1i.The manufacture method of described thin-film transistor array base-plate comprises the following steps:
Step S1: provide the substrate that has a first surface, and this substrate comprises first area, second area, the 3rd region.Described substrate can be resin substrate, also can be glass substrate.
Step S2: form resilient coating and amorphous silicon layer successively at the first surface of described substrate, and described amorphous silicon layer is converted into polysilicon layer by an annealing process.Described annealing process can be Ultra-Violet Laser scanning, Solid State Laser scanning, thermal anneal process or other annealing processs.
Step S3: be coated with one first photoresist layer on described polysilicon layer, and by one first mask, photoetching is carried out to described photoresist layer, the first photoresist layer being positioned at second area is removed, retains the first photoresist layer being positioned at first area, the 3rd region.
Step S4: the P type ion doping polysilicon layer in described second area being carried out to low concentration, then removes the first photoresist layer in first area and the 3rd region.
Step S5: form a gate insulation layer, grid conductive layer on described polysilicon layer, and one second photoresist layer is coated with on described grid conductive layer, by one comprise transmission region, semi-transparent region, light tight region the second mask photoetching is carried out to described second photoresist layer, obtain one second photoetching agent pattern.Grid wiring in grid wiring in grid wiring in corresponding first area, described light tight region in the first grid of a first film transistor and this first area, second area in the region, silicon island of one second thin-film transistor and this second area and the 3rd region in a storage capacitance region and the 3rd region, the source drain region of described the first film transistor in corresponding described first area, described semi-transparent region, the remainder on the corresponding described first surface of described transmission region.Described gate insulation layer is made up of the oxide of silicon or nitride, described grid conductive layer by metal material as molybdenum, aluminium are made.In this second photoetching agent pattern, part second photoresist layer corresponding with described transmission region is removed, part second photoresist layer corresponding with described semi-transparent region is partially removed, part second photoresist layer corresponding with described light tight region is retained, and the thickness of part second photoresist layer corresponding with described semi-transparent region is less than the thickness of part second photoresist corresponding with described light tight region.
Step S6: the grid conductive layer do not covered in the region of the second photoresist layer is etched, and the described gate insulation layer under it and polysilicon layer are etched, define the storage capacitance region in the region, silicon island of the second thin-film transistor in the region, silicon island of the first film transistor in described first area, described second area, the 3rd region and the grid wiring in all regions.
Step S7: carry out plasma reduction processing to described second photoresist layer, second photoresist layer corresponding with the semi-transparent region of described second mask is removed, and the thickness of second photoresist layer corresponding with described light tight region reduces.The second photoresist layer in the source drain region of i.e. the first film transistor is removed, and the second photoresist layer on the region, silicon island of described second thin-film transistor and storage capacitance region is retained.
Step S8: the grid conductive layer not covering described second photoresist layer is etched, define first grid and the grid wiring of described the first film transistor, then, remove remaining second photoresist layer, and the high concentration of carrying out a P type ion is injected, form the first source electrode of described the first film transistor, the first drain electrode and the first channel region between the first source electrode and the first drain electrode.
Step S9: at the first side coating one the 3rd photoresist layer of the first surface of described substrate, 3rd photoresist layer covers all elements in first, second and third region, and by one the 3rd mask, a photoetching is carried out to described 3rd photoresist layer, the region, silicon island of described the first film transistor, the second grid of the second thin-film transistor, the electrode in described storage capacitance region are covered by the 3rd photoresist layer, and the 3rd photoresist layer of remainder is removed.
Step S10: etch the grid conductive layer exposed, makes the grid conductive layer on the source-drain electrode of described second thin-film transistor remove, forms the grid wiring of the described second grid of the second thin-film transistor, the electrode of storage capacitance and correspondence.Due to the lateral etches characteristic of wet etching, the size of the second grid of described second thin-film transistor is made to be less than the size of described 3rd photoresist layer of the part be located thereon.
Step S11: the high concentration of described polysilicon layer being carried out to a N-type ion is injected, the second source electrode and second forming described second thin-film transistor drains and forms the polysilicon high-doped zone in storage capacitance region, and is formed the second channel region by the region that described second grid covers.Because the first grid of described the first film transistor and wiring thereof and the second grid of described second thin-film transistor and connecting up is not made in the lump in same technique, for both guaranteeing in fabrication error allowed band, effective connection can be realized.Therefore, need to arrange a splicing ear in both junctions.In first area and second area intersection, described second mask has light tight region, and makes the grid wiring in described first area have splicing ear.Described 3rd mask has light tight region, the size in the light tight region on described second mask is greater than the light tight region on described 3rd mask, and there is a surplus, namely in described first area and second area intersection, the size of the grid wiring in described first area is greater than the size of the grid wiring in described second area.
Step S12: remove the 3rd unnecessary photoresist layer, and the low concentration carrying out a N-type ion injects, and makes not formed low-doped source-drain area by the polysilicon layer that described second grid covers in the second thin-film transistor.
Step S13: form the second insulating barrier in the first surface side of substrate, this second insulating barrier covers all elements in first, second and third region described, and is coated with one the 4th photoresist layer over the second dielectric.
Step S14: photoetching is carried out to described 4th photoresist layer by one the 4th mask, form the 4th photoresist layer pattern, and according to the 4th photoresist layer pattern described second insulating barrier of etching and gate insulation layer, high-doped zone in first, second and third region and wiring thereof are come out, even if come out in the first source electrode of described the first film transistor and the first drain electrode, the second source electrode of described second thin-film transistor and the polysilicon high-doped zone in the second drain electrode and described storage capacitance region, then remove the 4th remaining photoresist layer.Described second insulating barrier and described gate insulation layer adopt same material to be made, and therefore, while described second insulating barrier of etching, can complete the etching of the gate insulation layer of correspondence position.
Step S15: make a source and drain metal level on described second insulating barrier, and one the 5th photoresist layer is coated with on this source and drain metal level, by one the 5th mask, photoetching is carried out to described 5th photoresist layer, form one the 5th photoetching agent pattern, and etch described source and drain metal level according to the 5th photoetching agent pattern, formed with the first film transistor the first source electrode and first to drain the first source wiring and the first drain electrode wiring that are connected, to drain the second source wiring and the second drain electrode wiring that are connected with second source electrode and second of the second thin-film transistor, be connected with the polysilicon high-doped zone of storage capacitance the 3rd connects up.Described source and drain metal level adopts material such as metal molybdenum, the aluminium etc. identical with described grid conductive layer to make.
Step S16: form one the 3rd insulating barrier in the side of the first surface of described substrate, and the 3rd insulating barrier covers all elements in first, second and third region described, described 3rd insulating barrier is coated with one the 6th photoresist layer, and by one the 6th mask, photoetching is carried out to described 6th photoresist layer, form one the 6th photoetching agent pattern, and according to described 6th photoetching agent pattern, described 3rd insulating barrier is etched, described second drain electrode wiring is come out.Described 3rd insulating barrier adopts the material identical with the second insulating barrier 400 with described gate insulation layer to make.
Step S17: form a pixel electrode layer in the side of the first surface of described substrate, this pixel electrode layer covers all elements in first, second and third region described, described pixel electrode layer is coated with one the 7th photoresist layer, and by one the 7th mask, photoetching is carried out to described 7th photoresist layer, form one the 7th photoetching agent pattern, and according to the 7th photoetching agent pattern, described pixel electrode layer is etched, form pixel electrode and local wiring.
The above-mentioned manufacture method of thin-film transistor array base-plate provided by the invention adopts 7 road photoetching processes, and compared with prior art, its process complexity is low, can enhance productivity, and improves the yields of product.In addition, source electrode, the contour doped regions that drains of described the first film transistor are all formed by self-registered technology, and its parasitic capacitance is little; The source-drain area 202a of low concentration is formed by self-registered technology, and its size is less, and uniformity is good.
In other embodiments, the manufacture method of described thin-film transistor array base-plate comprises the following steps:
Step S1 to S15 in L1: Fig. 4 a and 4b.
L2: form described pixel electrode layer in the side of the first surface of described substrate and be formed at the 8th photoresist layer on described pixel electrode layer, and by described 7th mask, photoetching is carried out to described 8th photoresist layer, form one the 8th photoetching agent pattern, and accordingly described pixel electrode layer is etched, form pixel electrode, described pixel electrode and the second drain electrode wiring and the 3rd connect up and are electrically connected.
In present embodiment, only need employing 6 road photoetching process, namely can be made into thin-film transistor array base-plate, its process complexity reduces further, is conducive to enhancing productivity further and product yields.
Or be that the manufacture method of described thin-film transistor comprises the following steps:
Step S1 to S14 in M1: Fig. 4 a and 4b.
M2: form pixel electrode layer, source and drain metal level, the 9th photoresist layer in the side of the first surface of described substrate successively, and by one the 8th mask, photoetching is carried out to described 9th photoresist layer, form one the 9th photoetching agent pattern.Described 8th mask has light tight region, transmission region, semi-transparent region, the region at corresponding above-mentioned first source wiring in described light tight region and the first drain electrode wiring, the second source wiring and the second drain electrode wiring place, the region at corresponding pixel electrodes place, described semi-transparent region, corresponding light tight region, all the other regions.Therefore, after by described 8th mask described 9th photoresist layer being carried out to photoetching and development, the thickness of the 9th photoresist layer on the region at described first source wiring and the first drain electrode wiring, the second source wiring and the second drain electrode wiring place is greater than the thickness of the 9th photoresist layer on the region at described pixel electrode place.
M3: the described source and drain metal level and pixel electrode layer that do not cover the 9th photoresist layer are etched, forms described first source wiring and the first drain electrode wiring, the second source wiring and the second drain electrode wiring.
M4: the reduction processing of described 9th photoresist layer being carried out to plasma, the 9th photoresist layer on pixel electrode is removed, and the thickness of the 9th photoresist layer on described first source wiring and the first drain electrode wiring, the second source wiring and the second drain electrode wiring is reduced, then described source and drain metal level is etched, and described pixel electrode layer can not be etched into, and then form described pixel electrode and local wiring.
In the present embodiment, only adopt 5 road photoetching processes can complete the making of described thin-film transistor array base-plate, can effectively enhance productivity and product yields.If for the making carrying out the thin-film transistor array base-plate of regulating valve threshold voltage without the need to carrying out channel doping, the step S3 in Fig. 4 a, 4b, S4 can be omitted, 4 road photoetching processes are namely only adopted to complete the making of described thin-film transistor array base-plate.
It is more than the better embodiment of thin-film transistor array base-plate provided by the invention and preparation method thereof; the restriction to rights protection scope of the present invention can not be interpreted as; those skilled in the art should know; without departing from the inventive concept of the premise; also can do multiple improvement or replacement; these all improvement or replacement all should in the scope of the present invention, and namely the scope of the present invention should be as the criterion with claim.
Claims (10)
1. a thin-film transistor array base-plate, at least comprise a substrate with first surface and the first film transistor be formed on the first surface of described substrate, second thin-film transistor, storage capacitance, one gate insulation layer, and described the first film transistor and the second thin-film transistor are dissimilar thin-film transistor, described substrate comprises first area, second area, 3rd region, described the first film transistor is positioned at described first area, described second thin-film transistor is positioned at second area, described storage capacitance is positioned at described 3rd region, described the first film transistor comprises first grid, first source electrode, first drain electrode and the first channel region, described second thin-film transistor comprises second grid, second source electrode, second drain electrode, second channel region and low-doped source-drain area, described storage capacitance comprises electrode, described first source electrode and the first drain electrode are made up of the ion of the doping polycrystalline silicon layer first kind, described second source electrode and the second drain electrode are made up of the ion of doping polycrystalline silicon layer Second Type, described first grid and second grid are made up in different photoetching process of same grid conductive layer, the electrode of described second grid and storage capacitance is made in the lump in same photoetching process, described first grid and the first source electrode and first are drained to be insulated by described gate insulation layer and open, and described second grid and the second source electrode and second are drained to be insulated by described gate insulation layer and open, described first channel region and the second channel region are by not adulterating or lightly doped polysilicon layer formation, described first channel region is between described first source electrode and the first drain electrode, under described first grid, and described second channel region is between described second source electrode and the second drain electrode, under described second grid, described low doping source drain region is between described second source electrode and described second channel region and described second to drain and between the second channel region, described storage capacitance at least also comprises polysilicon high-doped zone, this polysilicon high-doped zone is made up of polysilicon doping or the part one of adulterating in first, second types of ion, and the electrode of itself and described storage capacitance is insulated by described gate insulation layer and opens.
2. thin-film transistor array base-plate as claimed in claim 1, it is characterized in that: described thin-film transistor array base-plate at least also comprises the second insulating barrier, first source wiring, first drain electrode wiring, second source wiring, second drain electrode wiring, 3rd wiring, and described first source wiring and the second drain electrode wiring drain with described first source electrode and first respectively and are electrically connected, described second source wiring and the second drain electrode wiring drain with described second source electrode and second respectively and are electrically connected, described 3rd wiring is electrically connected with described polysilicon high-doped zone, and described 3rd wiring is insulated by described second insulating barrier with the electrode of described storage capacitance and is opened, described first source wiring and being insulated by described second insulating barrier between the first drain electrode wiring and first grid is opened, described second source wiring and being insulated by described second insulating barrier between the second drain electrode wiring and second grid is opened.
3. thin-film transistor array base-plate as claimed in claim 2, it is characterized in that: thin-film transistor array base-plate at least also comprises pixel electrode, the 3rd insulating barrier, pixel electrode and the described first or second drain electrode wiring are electrically connected, and this pixel electrode is opened by described 3rd insulating barrier and the described 3rd insulation of connecting up.
4. a manufacture method for thin-film transistor array base-plate, comprises the following steps:
There is provided the substrate that has a first surface, and it comprises first area, second area, the 3rd region;
Form resilient coating and amorphous silicon layer successively at the first surface of described substrate, and described amorphous silicon layer is converted into polysilicon layer by an annealing process;
Described polysilicon layer is formed a gate insulation layer, grid conductive layer, and one second photoresist layer is coated with on described grid conductive layer, by one comprise transmission region, semi-transparent region, light tight region the second mask photoetching is carried out to described second photoresist layer, obtain one second photoetching agent pattern;
The grid conductive layer do not covered in the region of the second photoresist layer is etched, and the gate insulation layer under it and polysilicon layer are etched, define the storage capacitance region in the region, silicon island of the second thin-film transistor in the region, silicon island of the first film transistor in first area, described second area and the 3rd region and the grid wiring in all regions;
Carry out plasma reduction processing to the second photoresist layer, second photoresist layer corresponding with the semi-transparent region of the second mask is removed, and the thickness of second photoresist layer corresponding with described light tight region reduces;
The grid conductive layer not covering described second photoresist layer is etched, define first grid and the grid wiring of described the first film transistor, remove remaining second photoresist layer, and the high concentration of carrying out the ion of a first kind is injected, form the first source electrode of described the first film transistor, the first drain electrode and the first channel region between the first source electrode and the first drain electrode;
At the first side coating one the 3rd photoresist layer of the first surface of substrate, 3rd photoresist layer covers all elements in first, second and third region, and by one the 3rd mask, a photoetching is carried out to the 3rd photoresist layer, the region, silicon island of described the first film transistor, the second grid of the second thin-film transistor, the electrode in described storage capacitance region are covered by the 3rd photoresist layer, and the 3rd photoresist layer of remainder is removed;
The grid conductive layer exposed is etched, the grid conductive layer on the source-drain electrode of the second thin-film transistor is removed, forms the grid wiring of the second grid of the second thin-film transistor, the electrode of storage capacitance and correspondence;
The high concentration of described polysilicon layer being carried out to the ion of a Second Type is injected, the second source electrode and second forming described second thin-film transistor drains and forms the polysilicon high-doped zone in storage capacitance region, and is formed the second channel region by the region that described second grid covers;
Remove the 3rd unnecessary photoresist layer, and the low concentration carrying out the ion of a Second Type injects, and makes not formed low-doped source-drain area by the polysilicon layer that described second grid covers in the second thin-film transistor;
Form the second insulating barrier in the first surface side of substrate, this second insulating barrier covers all elements in first, second and third region described, and is coated with one the 4th photoresist layer over the second dielectric;
By one the 4th mask, photoetching is carried out to described 4th photoresist layer, form the 4th photoresist layer pattern, and according to the 4th photoresist layer pattern described second insulating barrier of etching and gate insulation layer, high-doped zone in first, second and third region and wiring thereof are come out, even if come out in the first source electrode of described the first film transistor and the first drain electrode, the second source electrode of described second thin-film transistor and the polysilicon high-doped zone in the second drain electrode and described storage capacitance region, then remove the 4th remaining photoresist layer.
5. the manufacture method of thin-film transistor array base-plate as claimed in claim 4, is characterized in that: the manufacture method of described thin-film transistor array base-plate is further comprising the steps of:
Make a source and drain metal level over the second dielectric, and be coated with one the 5th photoresist layer thereon; By one the 5th mask, photoetching is carried out to described 5th photoresist layer, form one the 5th photoetching agent pattern, and etch described source and drain metal level according to the 5th photoetching agent pattern, formed with the first film transistor the first source electrode and first to drain the first source wiring of being connected and the first drain electrode wiring, the second source wiring that is connected of draining with second source electrode and second of the second thin-film transistor and the second drain electrode wiring, the 3rd wiring that is connected with the polysilicon high-doped zone of storage capacitance;
One the 3rd insulating barrier is formed in the side of the first surface of substrate, and the 3rd insulating barrier covers described first source wiring, the first drain electrode wiring, the second source wiring, the second drain electrode wiring, the 3rd wiring, 3rd insulating barrier is coated with one the 6th photoresist layer, and by one the 6th mask, photoetching is carried out to described 6th photoresist layer, form one the 6th photoetching agent pattern, and according to described 6th photoetching agent pattern, described 3rd insulating barrier is etched, the second drain electrode wiring is come out;
A pixel electrode layer is formed in the side of the first surface of substrate, this pixel electrode layer covers all elements in first, second and third region described, described pixel electrode layer is coated with one the 7th photoresist layer, and by one the 7th mask, photoetching is carried out to described 7th photoresist layer, form one the 7th photoetching agent pattern, and according to the 7th photoetching agent pattern, described pixel electrode layer is etched, form pixel electrode and local wiring.
6. the manufacture method of thin-film transistor array base-plate as claimed in claim 5, is characterized in that: the manufacture method of described thin-film transistor array base-plate is further comprising the steps of:
Make a source and drain metal level over the second dielectric, and be coated with one the 5th photoresist layer thereon; By one the 5th mask, photoetching is carried out to described 5th photoresist layer, form one the 5th photoetching agent pattern, and etch described source and drain metal level according to the 5th photoetching agent pattern, formed with the first film transistor the first source electrode and first to drain the first source wiring of being connected and the first drain electrode wiring, the second source wiring that is connected of draining with second source electrode and second of the second thin-film transistor and the second drain electrode wiring, the 3rd wiring that is connected with the polysilicon high-doped zone of storage capacitance;
Form described pixel electrode layer in the side of the first surface of described substrate and be formed at the 8th photoresist layer on described pixel electrode layer, and by described 7th mask, photoetching is carried out to described 8th photoresist layer, form one the 8th photoetching agent pattern, and accordingly described pixel electrode layer is etched, form pixel electrode, described pixel electrode and the second drain electrode wiring and the 3rd connect up and are electrically connected.
7. the manufacture method of thin-film transistor array base-plate as claimed in claim 4, is characterized in that: the manufacture method of described thin-film transistor array base-plate is further comprising the steps of:
Described polysilicon layer is coated with one first photoresist layer, and by one first mask, photoetching is carried out to described photoresist layer, the first photoresist layer being positioned at second area is removed, retains the first photoresist layer being positioned at first area, the 3rd region;
Polysilicon layer in described second area is carried out to the ion doping of the first kind of low concentration, then remove the first photoresist layer in first area and the 3rd region.
8. the manufacture method of thin-film transistor array base-plate as claimed in claim 4, is characterized in that: the manufacture method of described thin-film transistor array base-plate is further comprising the steps of:
Form pixel electrode layer, source and drain metal level, the 9th photoresist layer in the side of the first surface of substrate successively, and by one the 8th mask, photoetching is carried out to described 9th photoresist layer, form one the 9th photoetching agent pattern;
The described source and drain metal level and pixel electrode layer that do not cover the 9th photoresist layer are etched, forms described first source wiring and the first drain electrode wiring, the second source wiring and the second drain electrode wiring;
Described 9th photoresist layer is carried out to the reduction processing of plasma, the 9th photoresist layer on pixel electrode is removed, and the thickness of the 9th photoresist layer on described first source wiring and the first drain electrode wiring, the second source wiring and the second drain electrode wiring is reduced, then described source and drain metal level is etched, and described pixel electrode layer can not be etched into, and then form described pixel electrode and local wiring.
9. the manufacture method of thin-film transistor array base-plate as claimed in claim 8, it is characterized in that: described 8th mask has light tight region, transmission region, semi-transparent region, corresponding above-mentioned first source wiring in described light tight region and the first drain electrode wiring, the region at the second source wiring and the second drain electrode wiring place, the region at corresponding pixel electrodes place, described semi-transparent region, corresponding light tight region, all the other regions, after photoetching and development being carried out to described 9th photoresist layer by described 8th mask, described first source wiring and the first drain electrode wiring, the thickness of the 9th photoresist layer on the region at the second source wiring and the second drain electrode wiring place is greater than the thickness of the 9th photoresist layer on the region at described pixel electrode place.
10. the manufacture method of thin-film transistor array base-plate as claimed in claim 4, it is characterized in that: in described second mask, the first grid of a first film transistor in corresponding first area, described light tight region, a storage capacitance region in the region, silicon island of one second thin-film transistor and the 3rd region in second area, the source drain region of described the first film transistor in corresponding described first area, described semi-transparent region, part between the region, silicon island of the second thin-film transistor in the region, silicon island of the described the first film transistor in the corresponding described first area of described transmission region and described second area, part between storage capacitance region in the region, silicon island of the second thin-film transistor in described second area and the 3rd region.
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| KR101486038B1 (en) * | 2012-08-02 | 2015-01-26 | 삼성디스플레이 주식회사 | Organic light emitting diode display |
| CN104008999B (en) * | 2014-05-26 | 2017-09-19 | 昆山国显光电有限公司 | Thin film transistor array arrangement, its manufacture method and array base palte |
| CN105225953A (en) * | 2014-06-16 | 2016-01-06 | 上海和辉光电有限公司 | The manufacture method of thin-film transistor and the manufacture method of array base palte |
| CN104143533B (en) * | 2014-08-07 | 2017-06-27 | 深圳市华星光电技术有限公司 | High-res AMOLED backboard manufacture methods |
| CN105355631A (en) * | 2015-10-10 | 2016-02-24 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method therefor, display apparatus and mask plate |
| CN105552027B (en) * | 2016-02-14 | 2018-08-14 | 武汉华星光电技术有限公司 | The production method and array substrate of array substrate |
| CN106449518A (en) * | 2016-10-14 | 2017-02-22 | 武汉华星光电技术有限公司 | Manufacturing method of LTPS (low temperature poly-silicon) array substrate and array substrate |
| CN106449655A (en) * | 2016-10-18 | 2017-02-22 | 武汉华星光电技术有限公司 | Thin film transistor array substrate and manufacturing method thereof |
| CN112470278A (en) * | 2018-07-04 | 2021-03-09 | 深圳市柔宇科技股份有限公司 | Array substrate, manufacturing method thereof and display device |
| KR20200047898A (en) * | 2018-10-26 | 2020-05-08 | 삼성디스플레이 주식회사 | Scan driver and display device including the same |
| CN111583793B (en) * | 2020-05-12 | 2021-09-24 | 武汉华星光电半导体显示技术有限公司 | Flexible display screen |
| CN113488543B (en) * | 2021-06-29 | 2022-07-12 | 惠科股份有限公司 | Thin film transistor, preparation method thereof and display panel |
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