GB2297379A

GB2297379A - Inspection of semiconductor device for defective leads

Info

Publication number: GB2297379A
Application number: GB9601846A
Authority: GB
Inventors: Tomoyuki Kida
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1995-01-30
Filing date: 1996-01-30
Publication date: 1996-07-31
Also published as: JPH08204096A; CN1138213A; GB9601846D0; KR960030361A

Description

METHOD OF AND APPARATUS FOR VISUALLY INSPECTING LEADS OF SEMICONDUCTOR DEVICE BACKGROUND OF THE INVENTION 1. Field of the Invention: The present invention relates to a method of and an apparatus for visually inspecting leads of a semiconductor device in the form of a flat-pack package, and more particularly to a method of and an apparatus for visually inspecting leads of a semiconductor device based on not only measurements of the leads but also the dimensions of the overall semiconductor device.

2. Description of the Related Art: Semiconductor devices in the form of flat-pack packages are mounted on printed wiring boards with lead ends soldered to pads on the printed wiring boards.

Because semiconductor devices available in recent years have many functions, they tend to have an increased number of leads, resulting in a high packaging density.

The high packaging density necessarily reduces the interval of-leads and the pitch or interval between pads on printed wiring boards. If leads of a semiconductor device were unduly bent or positionally displaced, then it would be impossible to mount the semiconductor device on a printed wiring board. To avoid such a drawback, there have been strict requirements for the elimination of undue lead bends and positional displacements, and it has been customary to visually inspect leads of semiconductor devices for undue lead bends and positional displacements in the process of fabricating semiconductor devices.

One conventional apparatus for visually inspecting semiconductor device leads is known from Japanese laid-open patent publication No. 4-80937 (1992), for example. Fig. 1 of the accompanying drawings shows in block form such a conventional apparatus for visually inspecting semiconductor device leads. Fig. 2 of the accompanying drawings shows in perspective major components of the conventional apparatus for visually inspecting semiconductor device leads, and Fig. 3 of the accompanying drawings shows an optical path in the major components shown in Fig. 2.

As shown in Figs. 2 and 3, a semiconductor device 303 is placed on the upper surface of an inspection stage 302. The inspection stage 302 comprises a block 304 of electrically conductive, slightly opaque diffusion resin whose sides are covered with a layer 322 of electrically conductive, highly opaque diffusion resin.

The inspection stage 302 diffuses light emitted from a light source 321 which is positioned below the inspection stage 302. The block 304 of electrically conductive, slightly opaque diffusion resin has on its upper surface a plurality of ridges 307 each serving as an optical prism for dividing light, directed toward leads 324 extending laterally from an outer casing of the semiconductor device 303, into a ray of light oriented in the direction in which the leads 324 extend and a ray of light oriented perpendicularly to that direction, the rays of light producing different luminances.

Projected images of the leads 324 which are formed by the respective rays of light are captured by CCD (charge-coupled device) cameras 301 through mirrors 305 and a prism 306.

The block 304 of electrically conductive, slightly opaque diffusion resin and the layer 322 of electrically conductive, highly opaque diffusion resin have different degrees of turbidity. The light from the light source 321 passes upwardly through these two regions having different degrees of turbidity, and produces different luminances on the upper surface of the inspection stage 302. Specifically, if the ray of light traveling horizontally parallel to the upper surface of the inspection stage 302 were less bright than the ray of light traveling upwardly from the inspection stage 302, then the horizontal ray of light would be subject to diffused reflection under the influence of the upward ray of light. The horizontal ray of light, which is used to measure the flatness of the leads 324, would then be lost, causing an error in the measurement of the flatness of the leads.To circumvent such a shortcoming, the turbidity of the block 304 and the layer 322 is designed for causing the horizontal ray of light to produce greater luminance.

A metallic light shield plate 323 is mounted on an outer surface of the layer 322 of electrically conductive, highly opaque diffusion resin to prevent unwanted light from being scattered around laterally from the layer 322. Each of the ridges 307 is of such a vertical shape that it enters in a space defined between the outer casing of the semiconductor device 303 and curved portions of the leads 324, so that the semiconductor device 303 can be placed in position on the inspection stage 302.

As shown in Fig. 1, the conventional apparatus for visually inspecting semiconductor device leads has an image reader 308 for reading projected images that have been captured by the CCD cameras 301, an image memory 309 for temporarily storing projected image data, a binary data generator 308a for converting the image data into binary image data, a profile generator 312 for generating a projected profile of the leads 324 based on the binary image data, and a CPU (central processing unit) 332.

The CPU 332 comprises a coplanarity calculating unit 313 for calculating the planarity of a plane which is made up of the tip ends of the leads 324 from the binary image data of a projected profile in the direction in which the leads 324 extend, a lead bend calculating unit 333 for calculating a lead bend in the direction in which the leads 324 extend from the binary image data of a projected profile in a direction perpendicular to the direction in which the leads 324 extend, and a decision unit 314 for determining whether the inspected leads 324 are acceptable or not based on the calculated results from the coplanarity calculating unit 313 and the lead bend calculating unit 333. The lead bend calculating unit 333 is composed of a central value calculator 310 and a trigonometric calculator 311.

To the CPU 332, there are connected external storage devices 315, 316 for storing calculated and determined results through I/O interfaces 317a, 317b, respectively, a CRT (cathode-ray tube) 318 and a printer 318 for outputting the calculated and determined results stored in the external storage devices 315, 316 through I/O. interfaces 317c, 317c, and a keyboard 320 for entering decision standards into the external storage device 316 through the I/O interface 317d prior to an inspection process.

A measuring procedure and a process of calculating measured values according to the apparatus for visually inspecting semiconductor device leads as shown in Figs.

1 through 3 will be described below. Fig. 4 of the accompanying drawings is illustrative of an algorithm for calculating a lateral lead bend with the apparatus for visually inspecting semiconductor device leads as shown in Fig. 1. Figs. 5(a) through 5(c) of the accompanying drawings are flowcharts of the process of calculating measured values. Fig. 6 of the accompanying drawings is illustrative of a process of calculating the planarity of leads.

Projected images formed by light that has passed through the inspection stage 302 are captured by the respective CCD cameras 301. The captured projected images are read by the image reader 308 and processed thereby into 6-bit, 64-gradation multivalued data, which are then stored in the image memory 309. The stored multivalued data are then converted into binary image data by the binary data generator 308a, and the binary image data are stored again in the image memory 309.

To measure the planarity of leads, images produced by the four CCD cameras 301 that are positioned laterally of the semiconductor device 303 are used. As shown in Fig. 6, a window W405 is established for each of the leads 324. The profile of the lead 324 and the light shield plate 323 in each of the windows W405 are stored as a group of dark spots in the image memory 309, and an area between the lead 324 and the upper surface of the inspection stage 302 is stored as a group of bright spots in the image memory 309. Then, the profile generator 312 generates a bright-spot-group profile 335 composed of a group of bright spots for each of the windows W405.Then, the coplanarity calculating unit 313 searches each of the windows W405 for the minimum value of vertical heights of the brightspot-group profile 335, calculates the maximum value of the minimum values in all the windows W405, and establishes the calculated maximum value as a value of planarity. The value of planarity is stored through the I/O interface 317a into the external storage device 315, and also sent to the decision unit 314. The decision unit 314 compares the value of planarity with a reference value of planarity which is stored in the external storage device 316, for thereby determining whether the inspected leads 324 are acceptable or not.

A process of measuring a lateral bend of a lead 324 will bedescribed below with reference to Figs.

5(a) through 5(c). As shown in Fig. 4, two windows W401, W402 are established from imaged regions of the four CCD cameras 301 which are positioned above the semiconductor device 303 in a step S501. Then, the central value calculator 310 determines, from the binary image data, points "a", "b" of intersection between a side LW1, whose y coordinate is WGly, of the window 401 and the lead 324, and points "c", "d" of intersection between a side LW2, whose y coordinate is WG2y, of the window 402 and the lead 324 in a step S502.

Thereafter, the central value calculator 310 determines middle points WG1 (WGlx, WGly), WG2 (WG2x, WG2y) of the lead 324 on the sides LW1, LW2 of the windows W401, W402 from the points "a", "b", "c", "d" of intersection in a step S503, and then determines a bend angle ( based on the determined middle points WG1, WG2 according to the following equation (1):

in a step S504.

Then, the coordinates STP of a middle point of the lead 324 at its tip end are determined according to a process shown in Fig. 5(b) in a step S505, and also the coordinates SBP of a middle point of the lead 324 at its proximal end are determined according to a process shown in Fig. 5(c) in a step S506. These coordinates STP, SBP are calculated from the bend angle ( using a trigonometric function by the trigonometric calculator 311. The trigonometric calculator 311 then calculates the amount of bend of the lead 324 by subtracting the x coordinate SBPx of the middle point coordinates SBP from the x coordinate STPx of the middle point coordinates STP in a step S507.

The amount of bend of each lead 324 thus determined is stored through the I/O interface 317a into the external storage device 315. The maximum value of the amounts of bend of the leads 324 is sent to the decision unit 314.

The decision unit 314 compares the amount of bend and planarity of the leads 324 which are sent from the trigonometric calculator 311 and the coplanarity calculating unit 313, with reference values that are delivered from the external storage device 316 through the I/O interface 317b, thereby to determine whether the inspected leads 324 are acceptable or not. The decision data are then stored into the external storage device 315. The CRT 318 and the printer 319 output the data and measured results from the external storage devices 315, 316 through the I/O interfaces 317c, 317d.

The conventional apparatus for visually inspecting semiconductor device leads as described above determines whether each of the individual leads is acceptable or not with respect to its bend. Japanese laidopen patent publication No. 1-236700 (1989) reveals another process of determining the central position of a semiconductor device and inspecting the amount of bend of a lead in relation to the determined central position.

According to the process revealed in this publication, projected images which are produced by light applied to leads of a semiconductor device are captured by CCD cameras, and obtained image data are processed to visually inspect the leads.

Specifically, projected images of leads of a semiconductor device are captured by CCD cameras, and produced image data are converted into binary image data, which are then stored into an image memory. From the stored binary image data, there are found positions where the luminance level is inverted, which are representative of edges of the leads. The positions of leads and the number of leads are determined from the positions of inverted luminance level thus determined.

If the number of leads thus determined is not equal to a predetermined number, then the semiconductor device is rejected as containing broken leads or unduly large lead positional displacements. If the number of leads thus determined is equal to a predetermined number, then an inter-lead pitch or interval is calculated from lead positions that are set at the centers of the leads, and stored into a memory. In the event that the semiconductor device is in an angularly dis placed position, the inter-lead pitch is larger than normal. In this case, central positions of lead sides are calculated from a plurality of laterally spaced lead positions where inter-lead pitches are equal to each other. Lead positions and inter-lead pitches are calculated based on the binary image data. The above process is carried out with respect to each of the sides of the semiconductor device.If the semiconductor device has four lead sides, then the central position and angular displacement of the overall semiconductor device with respect to the leads are calculated from the centers of the four lead sides. The central position can be given as a point of intersection between two straight lines that each interconnect the centers of two confronting lead sides of the four lead sides. The angular displacement can be given as an angle of the above straight lines with respect to an orthogonal coordinate system whose origin is at the central position of the semiconductor device that is free of any undue positional displacements.

It is determined from the angular displacement whether the previously calculated inter-lead pitch on each of the lead sides falls in a prescribed range or not. If it falls outside of the prescribed range, then the semiconductor device is rejected as containing bent leads. If is falls in the prescribed range, then the lead positions are corrected. Finally, binary image data are obtained with respect to one or each lead side, and it is determined whether the lead positions on both ends and their corrections are good or not.

The above conventional apparatus for and method of visually inspecting semiconductor device leads suffer the following problems: According to Japanese laid-open patent publication No. 4-80937 (1992), each individual lead is inspected particularly for a lateral lead bend. Therefore, it is not possible to recognize the bend of all leads of a semiconductor device as it is mounted on a printed wiring board. Furthermore, since the coordinates of the central position of the tip end of a lead are used to determine any bend of the lead, the lead is determined as being bent even when the lead simply has a varying width.

The above problems will be quantitatively discussed below with reference to Fig. 7 of the accompanying drawings. Fig. 7 schematically shows a semiconductor device having 128 leads with a lead pitch of 0.8 mm, the semiconductor device being of a square shape each having a side 28 mm long (corresponding to the profile type QFP128-P-2828-0.80 by Japan Electronic Device Industry Society). In Fig. 7, only the leads on both ends of each side of the semiconductor device are illustrated.

It is assumed in Fig. 7 that all the leads on the upper lower, and left sides of the semiconductor device suffer a lead bend of 0.15 mm, and the uppermost lead on the right side has a lead bend of 0.15 mm and a lead width of 0.50 mm in excess of the lead width (in the range of 0.30 - 0.45 mm: a reference value of 0.37 mm) according to the profile type QFP128-P-2828-0.80. If the leads of the semiconductor device are inspected by the above conventional apparatus using a reference value of 0.15 mm for lead bends (no coplanarity inspection made in this example), then the semiconductor device shown in Fig. 7 is judged as being acceptable.

On printed wiring boards for mounting a semiconductor devices, the width of a mount pad is designed based on a reference value for lead bends as follows: Mount pad width = Lead width + 2 x Reference value for lead beads (2) When the semiconductor device shown in Fig. 7 is mounted on a printed wiring board, since the uppermost lead on the right side has a lead bend of 0.15 mm and a lead width exceeding the reference lead width by 0.13 mm, the uppermost lead is displaced off the corresponding mount pad by a distance equivalent to the excess of the lead width, resulting in a mount failure. Stated otherwise, the semiconductor device, which should be rejected when mounted on the printed wiring board, is judged as being acceptable by the conventional apparatus.

Conversely, even when a lead has a lead bend in excess of a reference value, it may cause no problem when the semiconductor device is mounted on a printed wiring board, depending on the position of the proximal end of the lead. Such a condition arises, for example, if the uppermost lead on the right side has a lead bend of 0.17 mm and the proximal end of the lead is displaced 0.1 mm to the left in Fig. 7. The semiconductor device is judged as being defective because the lead bend is greater than the reference value. Actually, however, the semiconductor device as mounted on a printed wiring board does not suffer a mount failure because the position of the tip end of the lead is displaced 0.07 mm to the right off the reference position. Therefore, the semiconductor device is judged as being defective though it actually poses no problem when mounted.

According to the process disclosed in Japanese laid-open patent publication No. 1-236700 (1989), a displacement of the central position and the angular displacement of a semiconductor device are determined, and it is determined whether an inter-lead pitch falls within a prescribed range or not based on the deter mined angular displacement. Therefore, it is possible to determine the position of a lead with respect to the profile of the semiconductor device. The inter-lead pitch is used to determine a lead bend, and such a lead bend is eventually used as a reference for determining whether the semiconductor device is acceptable or not.

Accordingly, the disclosed process does tak into account varying widths of leads.

SUMMARY OF THE INVENTION It is therefore an object of at least an embodiment of the present invention to provide a method of and an apparatus for visually inspecting leads of a semiconductor device to reliably detect a lead bend which will cause a mount failure when the semiconductor device is be mounted on a printed wiring board and also to refrain from judging as being defective a lead which will not bring about an actual mount failure when the semiconductor device is be mounted on a printed wiring board.

There is provided in accordance with one aspect of the present invention a method of visually inspecting leads of a semiconductor device, comprising the steps of: defining profile design image data of the semiconductor device and a reference value therefor; producing a captured image of the semiconductor device as profile image data; determining the extent of an area in which said profile image data and said profile design image data are not superimposed on each other, when the profile image data and the profile design image data are oriented in the same direction and have respective centers in alignment with each other; and comparing the determined extent with said reference value to determine whether said semiconductor device is acceptable or not with respect to bends of the leads.

In accordance with a second aspect of the invention there is provided a method of visually inspecting leads of a semiconductor device in the form of a flat-pack package, comprising the steps of: storing design dimensional data and a reference value with respect to leads of the semiconductor device in an external storage device; storing a captured image representing a profile of the semiconductor device as profile image data, and storing the design dimensional data as profile design image data; superimposing the profile image data and the profile design image data on each other such that the profile image data and the profile design image data are oriented in the same direction and have respective centers in alignment with each other; ; shifting the profile design image data on the profile image data and searching for a position in which the profile design image data are not superimposed on the profile image data with respect of tip ends of the leads for thereby determining an error of the profile image data with respect to the profile design image data; and comparing the error with the reference value to determine whether the semiconductor device is accept able or not with respect to bends of the leads.

In the above method, design dimensional data and a reference value with respect to leads of the semicon ductor device, which is in the form of a flat-pack package, are stored in the external storage device. A profile of the semiconductor device is stored as pro file image data based on a captured image of the semi conductor device, and the design dimensional data are stored as profile design image data. The design dimensional data are thus converted into image data similar to the profile image data based on the captured image.

The profile image data and the profile design image data are superimposed on each other such that the profile image data and the profile design image data are oriented in the same direction and have respective centers in alignment with each other. Then, the profile design image data are shifted on the profile image data and a position in which the profile design image data are not superimposed on the profile image data with respect to tip ends of the leads is searched for.

An error of the positions of the leads with respect to the profile design image data is now determined with reference to the center of the semiconductor device.

The error is compared with the reference value to determine whether the semiconductor device is acceptable or not with respect to bends of the leads.

Because the individual leads are not judged for their bends, but the tip ends of the leads are judged for their positions with respect to the center of the semiconductor device, the semiconductor device is judged in a manner similar to the condition in which it is mounted on a printed wiring board. Semiconductor devices which will cause no problem when mounted on printed wiring boards are prevented from being judged as defective, and conversely semiconductor devices which will cause trouble when mounted on printed wiring boards are prevented from being judged as acceptable.

Since an error is determined by searching for a position in which the profile design image data are not superimposed on the profile image data with respect to the tip ends of the leads, it can properly be determined whether the semiconductor device is acceptable or not regardless of varying widths of the leads.

In the above method, it is important to determine accurately the center of the semiconductor device. The center of the semiconductor device may be determined by approximating an outer periphery of the semiconductor device with a rectangular shape, and regarding a point of intersection between the diagonal lines of the rectangular shape as the center of the semiconductor device. The rectangular shape can accurately be determined, without being affected by individual bends of the leads, by regressing, with straight lines, toward representative points of the tip ends of the leads of the profile image data on each side of the semiconductor device, and constructing the rectangular shape of the straight lines.

When the profile design image data are shifted on the profile image data, the number of times that the profile design image data are shifted may be counted, and the error may easily be determined with the counted number of times.

According to the present invention, there is also provided an apparatus for visually inspecting leads of a semiconductor device in the form of a flat-pack package, comprising: imaging means for capturing an image of a profile of the semiconductor device; a first memory for storing the image captured by the imaging means as profile image data; an external storage device for storing design dimensional data and a reference value which have been entered in advance with respect to leads of the semiconductor device; a second memory for storing the design dimensional data as profile design image data; profile image data correcting means for converting the profile image data such that the profile image data and the profile design image data are oriented in the same direction; a third memory for storing the profile image data as converted by the profile image data correcting means;; error calculating means for superimposing the profile image data stored in the second memory and the profile design image data stored in the third memory such that the profile image data and the profile design image data have respective centers in alignment with each other, thereafter shifting the profile design image data on the profile image data and searching for a position in which the profile design image data are not superimposed on the profile image data with respect to tip ends of the leads for thereby determining an error of the profile image data with respect to the profile design image data; and a decision unit for comparing the error with the reference value to determine whether the semiconductor device is acceptable or not with respect to bends of the leads.

The external storage device stores design dimensional data and a reference value which have been entered in advance with respect to leads of the semiconductor device. An image representing the profile of the semiconductor device is captured by the imaging means, and stored as profile image data in the first memory. The design dimensional data stored in the external storage device are stored as profile design image data, similar to the profile image data, in the second memory.

The profile image data are converted by the profile image data correcting means such that the profile image data and the profile design image data are oriented in the same direction, and the converted profile image data are stored in the third memory.

The error calculating means superimposes the profile image data and the profile design image data such that the profile image data and the profile design image data have respective centers in alignment with each other, thereafter shifts the profile design image data on the profile image data and searches for a position in which the profile design image data are not superimposed on the profile image data with respect to tip ends of the leads for thereby determining an error of the positions of the leads with respect to the profile design image data with reference to the center of the semiconductor device. The error is compared with the reference value stored in the external storage device to determine whether the semiconductor device is acceptable or not with respect to bends of the leads.

If the image captured by the imaging means is a transmitted image of the semiconductor device, then the profile image data contain less noise as a result of image processing and hence are more accurate than profile image data generated as reflected image data.

The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.

BRIEF DESCRIPTION OF THE DRAWING Fig. 1 is a block diagram of a conventional apparatus for visually inspecting semiconductor device leads; Fig. 2 is a perspective view of major components of the apparatus for visually inspecting semiconductor device leads as shown in Fig. 1; Fig. 3 is a view showing an optical path in the major components shown in Fig. 2; Fig. 4 is a fragmentary diagram illustrative of an algorithm for calculating a lateral lead bend with the apparatus for visually inspecting semiconductor device leads as shown in Fig. 1; Figs. 5(a) through S(c) are flowcharts of a process of calculating measured values which is carried out by the apparatus for visually inspecting semiconductor device leads as shown in Fig. 1;; Fig. 6 is a fragmentary diagram illustrative of a process of calculating the planarity of leads which is carried out by the apparatus for visually inspecting semiconductor device leads as shown in Fig. 1; Fig. 7 is a fragmentary view of a semiconductor device, quantitatively showing lead bends; Fig. 8 is a block diagram of an apparatus for visually inspecting semiconductor device leads according to a first embodiment of the present invention; Fig. 9 is a diagram showing a visual representation of profile image data stored in a first frame memory in the apparatus for visually inspecting semiconductor device leads as shown in Fig. 8; Fig. 10 is a diagram showing a visual representation of profile design image data stored in a second frame memory in the apparatus for visually inspecting semiconductor device leads as shown in Fig. 8;; Fig. 11 is a flowchart of an overall operation sequence or main routine of the apparatus for visually inspecting semiconductor device leads as shown in Fig.

8; Fig. 12 is a flowchart of a subroutine for calculating representative values of the tip ends of leads; Fig. 13 is a fragmentary diagram illustrative of a procedure for calculating representative values of the tip ends of leads; Fig. 14 is a flowchart of a subroutine for calculating a regression line of representative values of the tip ends of leads; Fig. 15 is a diagram showing a regression line in one window; Fig. 16 is a diagram showing a visual representa tion of regression lines with respect to all windows; Fig. 17 is a flowchart of a subroutine for calculating a profile center; Fig. 18 is a flowchart of a subroutine for an affine transformation; Fig. 19 is a diagram illustrative of a procedure of an affine transformation; Fig. 20 is a diagram showing a visual representation of profile image data after being subjected to an affine transformation;; Figs. 21(a) and 21(b) are flowchart of a subroutine for calculating a terminal central position error; Fig. 22 is a diagram showing a visual representation of profile image data and profile design image data that are superimposed and image extracting regions and matching windows that are established against the image data in the subroutine for calculating a terminal central position error as shown in Fig. 21; Fig. 23 is a diagram showing a visual representation similar to Fig. 22, with the matching windows shifted to the left in the subroutine for calculating a terminal central position error as shown in Fig. 21; Fig. 24 is a diagram showing a visual representation similar to Fig. 22, with the matching windows shifted to the right in the subroutine for calculating a terminal central position error as shown in Fig. 21;; Fig. 25 is a diagram showing a visual representation similar to Fig. 22, with the matching windows shifted upwardly in the subroutine for calculating a terminal central position error as shown in Fig. 21; Fig. 26 is a diagram showing a visual representation similar to Fig. 22, with the matching windows shifted downwardly in the subroutine for calculating a terminal central position error as shown in Fig. 21; Figs. 27(a) and 27(b) are flowcharts of left side searching subroutines in the subroutine for calculating a terminal central position error as shown in Fig. 21; Figs. 28(a) and 28(b) are flowcharts of right side searching subroutines in the subroutine for calculating a terminal central position error as shown in Fig. 21;; Figs. 29(a) and 29(b) are flowcharts of upper side searching subroutines in the subroutine for calculating a terminal central position error as shown in Fig. 21; Figs. 30(a) and 30(b) are flowcharts of lower side searching subroutines in the subroutine for calculating a terminal central position error as shown in Fig. 21; and Fig. 31 is a block diagram of an apparatus for visually inspecting semiconductor device leads according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 1st Embodiment: Fig. 8 shows in block form an apparatus for visually inspecting semiconductor device leads according to a first embodiment of the present invention.

As shown in Fig. 8, a plurality of semiconductor devices 1 in the form of flat-pack packages to be inspected are placed in respective regions, divided complementarily to the profiles of the semiconductor devices 1, on a tray 2. A CCD camera 7 as an imaging means for imaging one of the semiconductor devices 1 on the tray 2 is positioned above the tray 2.

The tray 2 is movable by a tray actuating system 4, and the CCD camera 7 is movable by a camera actuating system 5. The tray actuating system 4 and the camera actuating system 5 are controlled in their operation by a mechanism controller 8 which is con trolled by a CPU 23 through an I/O interface 24. The mechanism controller 8 operates the tray actuating system 4 to position one of the semiconductor devices 1 on the tray 2 within a field of view of the CCD camera 7. If it is impossible to position the semiconductor device 1 within the field of view of the CCD camera 7 with only the tray actuating system 4, then the mechanism controller 8 operates the camera actuating system 5 to move the CCD camera 7 to bring the semiconductor device 1 within the field of view of the CCD camera 7.

A ring illumination source 6 is disposed between the CCD camera 7 and the tray 2. Within the field of view of the CCD camera 7, the semiconductor device 1 is illuminated by light from the ring illumination source 6. The CCD camera 7 captures an image of the semiconductor device 1 which is represented by the light that is emitted from the ring illumination source 6 and reflected by the semiconductor device 1.

The CCD camera 7 produces an output signal, which represents the image of the semiconductor device 1, and an amplifier 9 amplifies the output signal from the CCD camera 7 up to a level capable of being supplied to an analog-to-digital (A/D) converter 10. The A/D converter 10 converts the amplified signal from the amplifier 9 into 8-bit, 256-gradation digital data, which are stored into a first frame memory 11. Specifically, the reflected image of the semiconductor device 1 which is captured by the CCD camera 7 is stored as multivalued profile image data 271 (see Fig. 9) into the first frame memory 11. Based on the profile image data 271 stored in the first frame memory 11, a lead tip end representative value calculating unit 12 calculates representative values of the respective tip ends of leads of the semiconductor device 1.

A terminal 20 serves to enter predetermined data prior to a visual inspection process for the semicon ductor device 1, and displays a decision result produced by a decision unit 22 in the CPU 23. The predetermined data to be entered by the terminal 20 include profile design data 19b which are dimensional design data with respect to the leads of the semiconductor device 1, established image processing condition data l9c such as of established values for windows to be used in subsequent image processing and the resolution of an image processing system, and reference data 19d such as of reference values for determining whether the semiconductor device 1 is acceptable or not. These data entered from the terminal 20 are stored in an external storage device 19.

A CAD (computer-aided design) data converter 17 generates profile design image data 281 as shown in Fig. 10 based on the profile design data 19b stored in the external storage device 19. In Fig. 10, the profile design data 19b entered from the terminal 20 represent a lead width "b", a total width HE, a total length HD, a lead length L1, a lead pitch "e", and the number of leads on each side. The profile design image data 281 generated by the CAD data converter 17 are stored into a second frame memory 16.

The CPU 23 comprises a regression line calculating unit 13, a profile center calculating unit 14, an affine transformation unit 15, a terminal central position error calculating unit 21, a decision unit 22, and a counter 25. Actually, the counter 25 comprises four counters as described later on.

The regression line calculating unit 13 regresses toward the representative points or values of the respective tip ends of leads on each side, which have been calculated by the lead tip end representative value calculating unit 12, thereby determining four straight lines that define the outer periphery of the semiconductor device 1. The profile center calculating unit 14 determines a point of intersection between diagonal lines of a rectangular shape that is made up of the four straight lines determined by the regression line calculating unit 13, i.e., a central point of the profile image data 271. The affine transformation unit 15 effects an affine transformation on the profile image data 271 with its central point determined. The profile image data 271 after it has been subjected to an affine transformation are stored into a third frame memory 18.The affine transformation is a coordinate transformation by which the positions of coordinates are transformed and shifted into other positions in a linear direction, an angular direction, or a direction that is symmetric with respect to any optional straight axis.

The regression line calculating unit 13, the profile center calculating unit 14, the affine transformation unit 15, and the lead tip end representative value calculating unit 12 jointly make up profile image data correcting means for converting the profile image data 271 into data having the same orientation as the profile design image data 281.

The terminal central position error calculating unit 21 calculates a terminal central position error which corresponds to the positions that the leads of the semiconductor device 1 are to occupy from the profile design image data 281 stored in the second frame memory 16 and the profile image data 271 stored in the third frame memory 18. The terminal central position error calculating unit 21 calculates such a central position error by shifting the image data one bit at a time, and counting the number of times that the image data are shifted, with the counter 25. The decision unit 22 compares the central position error calculated by the terminal central position error calculating unit 21 with the reference data 19d stored in the external storage device 19, thereby to determine whether the semiconductor device 1 is acceptable or not.A decision result made by the decision unit 22 is displayed by the terminal 20.

Depending on the decision result, the decision unit 22 sends a command through the I/O interface 24 to the mechanism controller 8. Specifically, if the decision unit 22 judges the semiconductor device 1 as acceptable, then it operates the camera actuating system 5 or the tray actuating system 4 to inspect a next semiconductor device 1. If the decision unit 22 judges the semiconductor device 1 as being defective, it operates a vacuum suction arm 3 to remove the defective semiconductor device 1 from the tray 2, and thereafter operates the camera actuating system 5 or the tray actuating system 4 to inspect a next semiconductor device 1.

Operation of the apparatus for visually inspecting semiconductor device leads according to the first embodiment will be described in detail below with reference to Fig. 11.

Prior to a visual inspection process, the operator enters profile design dimensional data 19b of a semiconductor device 1 to be inspected, established image processing condition data l9c, and reference data 19d through the terminal 20, and the entered data are stored into the external storage device 19.

Thereafter, the tray 2 or the CCD camera 7 is moved to bring the semiconductor device 1 into a position where it can be imaged by the CCD camera 7 in a step S101. After the semiconductor device 1 has been positioned, the CCD camera 7 captures a reflected image of the semiconductor device 1, and profile image data 271 generated from the captured image are stored into the first frame memory 11 in a step S102.

Then, based on the established image processing condition data l9c, four windows Wa, Wb, Wc, Wd (see FIG. 9) are established with respect to the profile image data 271 stored in the first frame memory 11 in a step S103. The windows Wa, Wb, Wc, Wd accommodate therein the tip end portions of the leads on the respective sides of the profile image data 271. The semiconductor device 1 placed on the tray 2 is not positionally displaced out of a range that is allowed within the corresponding divided region on the tray 2.

Therefore, the windows Wa, Wb, Wc, Wd can be fixedly established with respect to the absolute addresses of the first frame memory 11 at least for the type of the semiconductor device 1.

After the windows Wa, Wb, Wc, Wd have been established, the lead tip end representative value calculating unit 12 calculates representative values of the tip ends of the leads in each of the windows Wa, Wb, Wc, Wd in a step S104.

A subroutine for calculating representative values of the tip ends of the leads in the step S104 will be described below with reference to Fig. 12.

First, one of the established windows Wa, Wb, Wc, Wd is selected in a step S121. Based on window information defined in the established image processing condition data l9c, the corresponding window Wi (i = a, b, c, d) is extracted from the first frame memory 11 in a step S122. It is assumed that the window Wa is selected. Since the profile image data 271 are multivalued data and hence the data in the extracted window Wa are also multivalued data, the data in the extracted window Wa are converted into binary data in a step S123. The data of regions representing the leads, i.e., regions where the reflected light has a higher level, are of a level "1", and the data of other regions are of a level "0". A threshold level for converting the data in the extracted window into binary data is given by the established image processing condition data 19c. The binary data in the window Wa are then subjected to a noise process in a step S124.

In the noise process, with respect to addresses where the data level in the window Wa is "1", a cluster of bits less than a certain unit and not forming a group is regarded as noise, and the data of the cluster of bits are rewritten with "0".

After the noise process, a data scan line Sla(n) indicated by the dot-and-dash line in Fig. 13 is established on the outermost side of the window Wa in a step S125. The letter n in the data scan line Sla(n) indicates the number of steps, and is incremented by "1" each time the data scan line Sla(n) is shifted one step inward from the outermost side of the window Wa.

The data scan line Sla(n) moves one bit at a time from the left to the right in Fig. 13 along the longer side of the window Wa from an origin OWa (0, 0) of the window Wa, thereby reading data in a step S127. If there exist groups of data of "1" while thus reading data in a step S129, the number of groups of data, i.e., the number of leads, is counted in a step S130.

After one line of data is read, then the data scan line Sla(n) is shifted one step inward in a step S126, and data are read again.

The above cycle of operations is repeated until the counted number of leads becomes equal to the number "j" of leads which is given by the profile design dimensional data 19b in a step S131.

If the counted number of leads does not become equal to the design number "j" of leads even after the data scan line Sla(n) has scanned data up to a maximum step number nmax (corresponding to the innermost side of the window Wa) given by the established image processing condition data 19c in a step S128, then the semiconductor device 1 is short of leads, and is judged as suffering a lack of leads in a step S138.

At the time the counted number of leads becomes equal to the design number j of leads, the scanning process is temporarily stopped, the widths of the respective leads are calculated in a step 5132. For example, if all the leads are counted at the nth step as counted from the outermost side of the window Wa, then the width of each of the leads is expressed by the following equation: Lead width bj = pj (xlj, n) - qj (x2j, n)| n) x (3) where pj represents an address immediately before the data change from "0" to "1", qj represents an address where the data have changed from "0" to "1" (j indicates the lead number), and ss represents the resolution of the image processing system which is given by the established image processing condition data 19c.

After the widths bj of the respective leads have been calculated, each of the calculated lead widths bj is compared with the lead width "b" which is given by the profile design dimensional data 19b in a step S133.

If the calculated lead width bj is smaller than the design lead width "b", then it is determined that only a portion of the tip ends of the leads has been scanned due to a lead bend or the like, and the steps S126 through S132 are repeated until the calculated lead width bj becomes equal to or greater than the design lead width "b".

When satisfactory lead widths bj are obtained with respect to all the leads, a middle point mj of the lead width bj of each of the leads is calculated in a step S134. The middle point mj of the lead width bj can be determined according to the following equation (4): Middle point mj (x, y) = (pj (x, y) + qj (x, y))/2 "' (4) Then, a vertical scan line laj which passes through the middle point mj on each of the leads perpendicularly to the data scan line Sla(n) is determined in a step S135. The data on the vertical scan line laj are successively read from the innermost side to outermost side of the window Wa, and a point taj where the data change from "1" to "0" is determined in a step S136. The determined point taj is referred to as a lead tip end representative point.

The above process is carried out also with respect to the remaining windows Wb, Wc, Wd. If the lead tip end representative points tij (i = a, b, c, d) with respect to all the windows Wi are determined in a step S137, then the coordinate system of the lead tip end representative points tij is converted from the relative coordinate system in each of the windows Wi into the absolute coordinate system in the first frame memory 11 which takes into account the relative relationship between all the windows Wi in a step S139.

The procedure for calculating representative values of the tip ends of the leads is now finished, and the processing goes back to the operation sequence or main subroutine shown in Fig. 11.

The regression line calculating unit 13 calculates a regression line of the representative values tij of the tip ends of the leads in each of the windows Wi from the representative values tij that have been converted into the absolute coordinate system in a step S105.

A subroutine or procedure for calculating a regression line of representative values of the tip ends of leads in each of the windows in the step S105 will be described below with reference to Fig. 14.

First, one of the four windows Wi is selected in a step S141. Then, a regression line Li (i = a, b, c, d) is calculated from the representative values tij of the tip ends of the leads in the selected window Wi according to the method of least squares in a step S142. For example, if the window Wa is selected, then, as shown in Fig. 15, a regression line La based on the representative values tal, ta2, ta3, ta4 of the tip ends of the leads is determined. This process is carried out with respect to the remaining windows Wi.

Fig. 16 shows a visual representation of the regression lines Li that are determined with respect to all the windows Wi. As shown in Fig. 16, the four straight lines, i.e., regression lines La, Lb, Lc, Ld, jointly make up a rectangular shape that represents the profile of the profile image data 271 which is defined by straight lines interconnecting the tip ends of the leads.

Since the straight lines regress toward the representative values tij of the tip ends of the leads on each of the sides and make up a rectangular shape representing the profile of the profile image data 271, the rectangular shape is accurate and not affected by bends of individual leads. If the regression lines Li are determined with respect to all the windows Wi in a step S143, then the procedure for calculating a regression line of representative values of the tip ends of leads in each of the windows is finished, and the processing returns to the main routine shown in Fig.

11.

After the regression lines Li have been determined, a profile center of the profile image data 271 is calculated based on the determined regression lines Li in a step S106.

A subroutine or procedure for calculating a profile center of the profile image data 271 in the step S106 will be described below with reference to Figs. 16 and 17.

First, four points KA, KB, KC, KD of intersection between the regression lines La, Lb, Lc, Ld are determined in a step S145. Then, two straight lines interconnecting the points of intersection that are not adjacent to each other, i.e., diagonal lines LF, LE of a rectangular shape made up of the regression lines La, Lb, Lc, Ld, are determined in a step S146. Thereafter, a point 0' of intersection between these two diagonal lines LF, LE is determined in a step S147. The point O' of intersection thus determined serves as the profile center of the profile image data 271.

After the profile center 0' of the profile image data 271 has been determined, the process goes back again to the main routine shown in Fig. 11, and the profile image data 271 are subjected to an affine transformation in a step S107.

A subroutine for such an affine transformation in the step S107 is shown in Fig. 18, and a procedure of such an affine transformation will be described below with reference to Figs. 18, 19, and 20.

The total width HD and the total length HE are read from the profile design dimensional data 19b in a step S151, and divided into bit lengths by the resolution ss defined by the established image processing condition data 19c. Based on the total width HD and the total length HE which have been thus converted into bit lengths, design (ideal) profile straight lines A, AB, AC, 1D are determined in a step S152. These profile straight lines XA, XB, ;1C, XD correspond respectively to the regression lines La, Lb, Lc, Ld (see Fig. 16) which have been determined by the regression line calculating unit 13.

Then, diagonal lines XE, XF of a rectangular shape made up of the profile straight lines XA, XE, XC, AD are determined in a step S153, and a point of intersection between the diagonal lines #E, #F, i.e., an ideal profile center 0, is determined in a step S154. The ideal profile center 0 is the same as the profile center of the profile design image data 281.

After the ideal profile center 0 has been determined, the ideal diagonal lines XE, XF are positioned to bring the ideal profile center 0 into alignment with the profile center O' of the profile image data 271.

The ideal diagonal lines XE, XF thus positioned are shown in Fig. 19. In Fig. 19, the profile image data 271 are angularly displaced with respect to the profile design image data 281 which are ideal.

An angle el formed between the diagonal lines LE, XE and an angle 02 formed between the diagonal lines LF, XF are determined in a step S156, and a corrective angle OC is calculated according to the following equation (5): o C = (01 + 02)/2 (5) After the corrective angle OC has been calculated, the profile image data 271 are angularly displaced in conformity with the corrective angle OC about the profile center 0 (= O'), i.e., are subjected to an affine transformation which is represented by the following equation (6):

where x, y represent coordinates prior to the affine transformation and X, Y represent coordinates subsequent to the affine transformation.The profile image data 271 after being subjected to the affine transformation are shown in Fig. 20.

In the above example, the ideal profile center 0 is determined based on the diagonal lines XE, XF, and then brought into alignment with the profile center 0' of the profile image data 271 in order to determine the angles 82. 2. However, another process may be employed to determine the angles 01, 2. For example, the profile image data 271 are surrounded by two line segments (corresponding to XA, 1C) parallel to the xaxis of the absolute coordinate system in the first frame memory 11 and spaced the total length HE from the profile image data 271, and also two line segments (corresponding to XE, XC) parallel to the y-axis of the absolute coordinate system in the first frame memory 11 and spaced the total width HD from the profile image data 271. These line segments are positioned such that the distances from the profile center O' of the profile image data 271 to the ends of the line segments are equal to each other. Two diagonal lines of a rectangular shape which is made up of those line segments are in conformity with the lines XE, XF, and a point of intersection between those two diagonal lines is also in conformity with the profile center 0' of the profile image data 271.

After the profile image data 271 have been processed by the affine transformation, the profile image data 271 are stored into the third frame memory 18 in a step S108 shown in Fig. 11.

The CAD data converter 17 generates the profile design image data 182 shown in Fig. 10 based on the profile design dimensional data 19b. The generated profile design image data 281 are stored into the second frame memory 16 in a step S109.

The terminal central position error calculating unit 21 calculates a terminal central position error of the semiconductor device 1 with respect to the positions that the leads of the semiconductor device 1 are to occupy, using the profile design image data 281 stored in the second frame memory 16 and the profile image data 271 stored in the third frame memory 18 in a step S110.

A subroutine or procedure for calculating a terminal central position error in the step S110 will be described below with reference to Figs. 21(a) and 21(b).

First, the profile center 0 (see Fig. 10) of the profile design image data 281 stored in the second frame memory 16 and the profile center 0' (see Fig. 20) of the profile image data 271 stored in the third frame memory 18 are superimposed in a step S161. Such a superimposed condition is an initial condition.

Then, image extracting regions çSi (i = a, b, c, d) indicated by the broken lines in Fig. 22, similar to the windows Wi (see Fig. 9) established for calculating the representative points of the tip ends of the leads, are established on outer edges of the profile design image data 281 in a step S162. A plurality of matching windows Xij (i = a, b, c, d, j = lead number) are established in each of the image extracting regions The positions and regions of the matching windows Xij are the positions and regions where the leads are to be present. After the matching windows % ij have been established, the counter 25 is reset in a step S164. The counter 25 actually comprises four counters for searching upper, lower, left, and right sides as described below.

In order to search for the positions of left and right ends of the profile image data 271, two confronting image extracting regions fa, fc are selected from the established image extracting regions fi in a step S165. Then, data that are one bit left of all the matching windows Xaj, Xcj present in the selected image extracting regions fa, 4)c are scanned in a step S166 as shown in Fig. 23. It is determined whether even one bit of data having a level of "1" is present or not as a result of the data scanning in a step S167.

If present, then a first left side searching subroutine is carried out in a step S168, and if not present, then a second left side searching subroutine is carried out in a step S169.

These two left side searching subroutines are shown respectively in Figs. 27(a) and 27(b).

In the first left side searching subroutine shown in Fig. 27(a), the image extracting regions 4)a, 4)c are shifted one bit to the left in a step S191, and then data that are one bit left of all the matching windows Xaj, Xcj present in the image extracting regions fa, 4)c are scanned in a step S192. It is determined whether even one bit of data having a level of "1" is present or not as a result of the data scanning in a step S193. If present, then the count of the counter for searching the left side is decremented by "1" in a step S194. This cycle is repeated until the scanned data no longer contain data having a level of "1".If the scanned data do not contain data having a level of "1", then the count of the counter for searching the left side is decremented by "1' in a step S195, and the first left side searching subroutine shown in Fig.

27(a) is finished.

In the second left side searching subroutine shown in Fig. 27(b), the image extracting regions fa, 4)c are shifted one bit to the right in a step S201, and then data that are one bit left of all the matching windows xaj, Xcj present in the image extracting regions fa, 4)c are scanned in a step S202. It is determined whether even one bit of data having a level of "1 is present or not as a result of the data scanning in a step S203. If not present, then the count of the counter for searching the left side is incremented by "1" in a step S204. This cycle is repeated until the scanned data contain data having a level of "1".If the scanned data contain data having a level of "1", then the seeond left side searching subroutine shown in Fig. 27(b) is finished.

In the first and second left side searching subroutines, the counts of the counter for searching the left side is decremented and incremented, respectively.

This is to define a unified set of directions of movement of the matching windows Xij from the origin where the matching windows xij are originally established, with the rightward and upward directions being positive directions.

When the first and second left side searching subroutines are finished, the profile center 0 of the profile design image data 281 stored in the second frame memory 16 and the profile center 0' of the profile image data 271 stored in the third frame memory 18 are superimposed again, returning to the initial condition in a step S170.

Then, data that are one bit right of all the matching windows Xaj, Xcj present in the previously selected image extracting- regions fa, 4)c are scanned in a step S171 as shown in Fig. 24. It is determined whether even one bit of data having a level of "1" is present or not as a result of the data scanning in a step S172. If present, then a first right side searching subroutine is carried out in a step S173, and if not present, then a second right side searching subroutine is carried out in a step S174.

These two right side searching subroutines are shown respectively in Figs. 28(a) and 28(b). The right side searching subroutines shown respectively in Figs.

28(a) and 28(b) are similar to the left side searching subroutines shown respectively in Figs. 27(a) and 27(b) except that the terms "left" and "right" are switched around and the count is decremented and incremented inversely, and hence will not be described in detail below.

When the first and second right side searching subroutines are finished, the positional relationship between the profile design image data 281 and the profile image data 271 is returned to the initial condition in a step S175. The processes of searching for the left and right ends of the image extracting regions fa, 4)c are now finished.

Thereafter, the remaining image extracting regions fb, fd are selected, and a process of searching for an upper end (steps S177 S180) and a process of searching for a lower end (steps S181 - S185) are successively carried out with respect to the image extracting regions fb, 4)d. These processes of searching for upper and lower ends are similar to the processes of searching for the left and right ends, described above, except that the terms "left" and "right" are replaced with "upper" and "lower", and will not be described in detail below.

Fig. 25 shows the matching windows shifted upwardly to search for an upper end, and Fig. 26 shows the matching windows shifted upwardly to search for a lower end. Figs. 29(a) and 29(b) show upper side searching subroutines to be executed for the process of searching for an upper end, and Figs. 30(a) and 30(b) show lower side searching subroutines to be executed for the process of searching for a lower end.

After the processes of searching for left, right, upper, and lower ends are finished, the counts in the respective directions, i.e., the numbers of bit shifts in the respective directions, are read in a step S186.

Then, the resolution ss of the image processing system is read from the established image processing condition data 19c in a step S187, and the counts are multiplied by the resolution ss, thereby determining the positions of the leads at the left, right, upper, and lower ends of the profile design dimensional data 19b. For example, when the count reached in the process of searching for a left hand is multiplied by the resolution ss, it can be determined how far a lead of the semiconductor device 1 is present from the leftmost end of a region where that lead is'to exist, with respect to all the leads present in the image extracting regions 4)a, fc.

The value thus determined in each of the directions serves as a terminal central position error in the direction in a step S188.

Referring back to Fig. 11, the determined terminal central position error is compared with a reference value for the inspected semiconductor device 1 by the decision unit 22 in a step S111. The reference value is read from the reference data 19d stored in the external storage device 19.

If the terminal central position error is equal to or smaller than the reference value, then the decision unit 22 judges the semiconductor device 1 as being acceptable, and displays an acceptance message on the terminal 20 in a step S112. If the terminal central position error is greater than the reference value, then the decision unit 22 displays a defect message on the terminal 20 in a step S113, and operates the vacuum suction arm 3 to remove and reject the inspected semiconductor device 1 in a step S114.

The overall process of visually inspecting one semiconductor device 1 is now finished. If a next semiconductor device 1 is to be visually inspected, the entire process is repeated from the step S101 shown in Fig. 11.

According to this embodiment, as described above, design dimensions relative to the leads of the semiconductor device 1 are converted into profile design image data 281, similar to profile image data 271 produced when the semiconductor device 1 is imaged, and the profile design image data 281 and the profile image data 271 are matched. The profile design image data 281 are shifted upwardly, downwardly, leftwardly, and rightwardly on the profile image data 271 to determine an error of the profile image data 271 with respect to the profile design image data 281. Therefore, the semiconductor device 1 is judged in a manner similar to the condition in which it is mounted on a printed wiring board.Semiconductor devices which will cause no problem when mounted on printed wiring boards are prevented from being judged as defective, and conversely semiconductor devices which will cause trouble when mounted on printed wiring boards are prevented from being judged as acceptable. Since an error is determined by searching for a position in which the profile design image data 281 are not superimposed on the profile image data 271 with respect to the tip ends of the leads, it can properly be determined whether the semiconductor device is acceptable or not regardless of varying widths of the leads.

A rectangular shape is created based on the representative values of the tip ends of leads of the profile image data 271, and a center of the profile image data 271 is.determined as a point of intersection between the diagonal lines of the created rectangular shape. Consequently, the center of the profile image data 271 can accurately be determined.

For example, it is assumed in Fig. 7 that the semiconductor device has a size of 40 mm on each side, the leads have a length of 1.7 mm, and all the leads on the upper side are uniformly bent by 1 mm. If the center of the semiconductor device were determined by the process disclosed in Japanese laid-open patent publication No. 1-236700 (1989), then since the positions of the leads on the upper side would be displaced as a whole, the determined center would be displaced 0.5 mm in the direction of the x-axis from the actual center. According to the process of the present embodiment, inasmuch as the positions of the tip ends of the leads on the upper side are displaced, the determined center is also displaced from the actual center by a distance of 1.7 mm.The distance by which the determined center is also displaced from the actual center is much smaller than the distance produced according to the conventional process. Thus, the center of the semiconductor device can be determined more accurately according to the process of the present embodiment.

According to the process disclosed in Japanese laid-open patent publication No. 1-236700 (1989), furthermore, the semiconductor device is judged as acceptable because the bent leads have a constant pitch. According to the process of the present embodiment, however, since any displacement from the profile design image data 281 is determined with respect to the tip ends of the leads and the semiconductor device is judged based on the determined displacement, the semiconductor device can reliably be rejected as a defective product.

2nd Embodiment: Fig. 31 shows in block form an apparatus for visually inspecting semiconductor device leads according to a second embodiment of the present invention.

As shown in Fig. 31, the apparatus according to the second embodiment includes an inspection stage 81 comprising an electrically conductive, transparent glass sheet in addition to a tray 52 for supporting a plurality of semiconductor devices 51. The inspection stage 81 supports one of the semiconductor devices 51 which has been picked up from the tray 52 by a vacuum suction arm 53, and the semiconductor device 51 placed on the inspection stage 81 is visually inspected.

A light source 56 is disposed below the inspection stage 81. A CCD camera 57 captures a transmitted image of the semiconductor device 51 which is produced when light emitted from the light source 56 is transmitted through the.inspection stage 81. The transmitted image is stored as profile image data into a first frame memory 61. In the second embodiment, the inspection stage 81 is not actuated, but the CCD camera 57 is two-dimensionally movable by a camera actuating system 55 for positioning the semiconductor device 51 placed on the inspection stage 81 into its field of view.

Other structural details of the apparatus according to the second embodiment and a procedure thereof from the calculation of a terminal central position error to the judgment of the semiconductor device 51 are the same as those of the apparatus according to the first embodiment, and hence will not be described in detail below. However, because the image captured by the CCD camera 57 is a transmitted image and the leads represented by the transmitted image are indicated by dark spots (whose level is of "0" in the frame memory) unlike the leads represented by the reflected image according to the first embodiment, it is necessary to process the data of dark and bright spots in a manner which is a reversal of the data processing according to the first embodiment.

If the semiconductor device 51 is judged as acceptable, then it is picked up by the vacuum suction arm 53, and returned from the inspection stage 81 to the tray 52. If the semiconductor device 51 is judged as defective, then it is picked up by the vacuum suction arm 53, and rejected.

Generally, it is known that reflective optical systems can produce stabler images than transmissive optical systems when they are used as measurement optical systems for measuring objects based on images produced thereby. Therefore, profile image data that are generated from transmitted images by the apparatus according to the second embodiment contain less noise as a result of image processing and hence are more accurate than profile image data generated by the apparatus according to the first embodiment.

While preferred embodiments of the present invention have been described using specific terms, such description is for illustrative purposes only, and it is to be understood that changes and variations may be made without departing from the spirit or scope of the following claims.

Each feature disclosed in the specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.

The text of the abstract filed herewith is hereby deemed to be repeated here in full as part of the specification.

Claims

CLAIMS:

1. A method of visually inspecting leads of a semiconductor device, comprising the steps of: defining profile design image data of the semiconductor device and a reference value therefor; producing a captured image of the semiconductor device as profile image data; determining the extent of an area in which said profile image data and said profile design image data are not superimposed on each other, when the profile image data and the profile design image data are oriented in the same direction and have respective centers in alignment with each other; and comparing the determined extent with said reference to value to determine whether said semiconductor device is acceptable or not with respect to bends of the leads.

2. A method of visually inspecting leads of a semiconductor device in the form of a flat-pack package, comprising the steps of: storing design dimensional data and a reference value with respect to leads of the semiconductor device in an external storage device; storing a captured image representing a profile of the semiconductor device as profile image data, and storing said design dimensional data as profile design image data; superimposing said profile image data and said profile design image data on each other such that the profile image data and the profile design image data are oriented in the same direction and have respective centers in alignment with each other;; shifting said profile design image data on said profile image data and searching for a position in which said profile design image data are not superimposed on said profile image data with respect to tip ends of the leads for thereby determining an error of said profile image data with respect to said profile design image data; and comparing said error with said reference value to determine whether said semiconductor device is acceptable or not with respect to bends of the leads.

3. A method according to Claim 2, further comprising the steps of approximating an outer periphery of said profile image data with a rectangular shape, and determining the center of said profile image data as a point of intersection of diagonal lines of said rectangular shape.

4. A method according to Claim 3, further comprising the steps of regressing, with straight lines, toward representative points of the tip ends of the leads of said profile image data on each side of the semiconductor device, and constructing said rectangular shape of said straight lines.

5. A method according to Claim 2 or 3, further comprising the steps of counting the number of times that said profile design image data are shifted, and determining said error with the counted number of times.

6. An apparatus for visually inspecting leads of a semiconductor device in the form of a flat-pack package, comprising: imaging means for capturing an image of a profile of the semiconductor device; a first memory for storing the image captured by said imaging means as profile image data; an external storage device for storing design dimensional data and a reference value which have been entered in advance with respect to leads of the semiconductor device; a second memory for storing the design dimensional data as profile design image data; profile image data correcting means for converting said profile image data such that the profile image data and the profile design image data are oriented in the same direction; a third memory for storing the profile image data as converted by said profile image data correcting means;; error calculating means for superimposing the profile image data stored in said second memory and the profile design image data stored in said third memory such that the profile image data and the profile design image data have respective centers in alignment with each other, thereafter shifting said profile design image data on said profile image data and searching for a position in which said profile design image data are not superimposed on said profile image data with respect to tip ends of the leads for thereby determining an error of said profile image data with respect to said profile design image data; and a decision unit for comparing said error with said reference value to determine whether said semiconductor device is acceptable or not with respect to bends of the leads.

7. An apparatus according to claim 6, wherein said profile image data correcting means comprises: a lead tip end representative value calculating unit for calculating representative points of the tip ends of the leads of said profile image data on each side of the semiconductor device; a regression line calculating unit for regressing toward said representative points on each side of the semiconductor device with a straight line; a profile center calculating unit for determining a center of said profile image data as a point of intersection between diagonal lines of a rectangular shape which is composed of straight lines generated by said regression line calculating unit; and an affine transformation unit for effecting an affine transformation on the profile image data with the center thereof determined by said center calculating unit.

8. An apparatus according to Claim 6, further comprising a counter for counting the number of times that said profile design image data are shifted.

9. An apparatus according to Claim 6, wherein said image captured by said imaging means is a transmitted image of the semiconductor device.

10. A method substantially as herein described with respect to Figures 8 to 31.

11. An apparatus substantially as herein described with respect to Figures 8 to 30.

12. An apparatus substantially as herein described with respect to Figures 9 to 31.