GB2202673B - The semi-conductor fabrication - Google Patents

The semi-conductor fabrication

Info

Publication number
GB2202673B
GB2202673B GB8707249A GB8707249A GB2202673B GB 2202673 B GB2202673 B GB 2202673B GB 8707249 A GB8707249 A GB 8707249A GB 8707249 A GB8707249 A GB 8707249A GB 2202673 B GB2202673 B GB 2202673B
Authority
GB
United Kingdom
Prior art keywords
semi
conductor fabrication
fabrication
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB8707249A
Other versions
GB8707249D0 (en
GB2202673A (en
Inventor
Haroon Ahmed
Andrew Hopper
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to GB8707249A priority Critical patent/GB2202673B/en
Publication of GB8707249D0 publication Critical patent/GB8707249D0/en
Publication of GB2202673A publication Critical patent/GB2202673A/en
Application granted granted Critical
Publication of GB2202673B publication Critical patent/GB2202673B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147Semiconductor insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
GB8707249A 1987-03-26 1987-03-26 The semi-conductor fabrication Expired - Lifetime GB2202673B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB8707249A GB2202673B (en) 1987-03-26 1987-03-26 The semi-conductor fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8707249A GB2202673B (en) 1987-03-26 1987-03-26 The semi-conductor fabrication

Publications (3)

Publication Number Publication Date
GB8707249D0 GB8707249D0 (en) 1987-04-29
GB2202673A GB2202673A (en) 1988-09-28
GB2202673B true GB2202673B (en) 1990-11-14

Family

ID=10614700

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8707249A Expired - Lifetime GB2202673B (en) 1987-03-26 1987-03-26 The semi-conductor fabrication

Country Status (1)

Country Link
GB (1) GB2202673B (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2224600B (en) * 1988-10-29 1992-03-18 Stc Plc Circuit assembly
FR2666173A1 (en) * 1990-08-21 1992-02-28 Thomson Csf HYBRID INTERCONNECTION STRUCTURE FOR INTEGRATED CIRCUITS AND MANUFACTURING METHOD.
FR2667443A1 (en) * 1990-09-28 1992-04-03 Thomson Csf METHOD FOR PRODUCING A HYBRID MODULE
FR2672427A1 (en) * 1991-02-04 1992-08-07 Schiltz Andre METHOD AND DEVICE FOR INSERTING CHIPS INTO HOUSINGS OF A SUBSTRATE BY INTERMEDIATE FILM.
US5844810A (en) * 1995-05-30 1998-12-01 General Electric Company Scaled adaptive lithography
US5866952A (en) * 1995-11-30 1999-02-02 Lockheed Martin Corporation High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate
EP1387394A3 (en) * 1997-04-15 2004-04-07 STMicroelectronics S.r.l. Process of final passivation of integrated circuit devices
WO2000002247A1 (en) * 1998-07-06 2000-01-13 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Method and device for producing an interconnection between a carrier element and at least one component contained therein
SE515032C2 (en) * 1998-09-09 2001-06-05 Ericsson Telefon Ab L M Electronic device comprising a component carrier as well as such component carrier and a method of manufacturing the device
US6281114B1 (en) * 2000-02-07 2001-08-28 Infineon Technologies Ag Planarization after metal chemical mechanical polishing in semiconductor wafer fabrication
DE102005007423B3 (en) * 2005-02-18 2006-06-14 Atmel Germany Gmbh Integration of electronic component (8) into substrate by formation of dielectric insulating layers on substrate front side useful in structural element modelling in semiconductor flip-chip technology with photoresistive layer in cavity
FR2904472B1 (en) * 2006-07-28 2008-10-31 Microcomposants De Haute Secur METHOD FOR MANUFACTURING ENCAPSULE INTEGRATED CIRCUIT AND INTEGRATED ENCAPSULE INTEGRATED CIRCUIT
FR2917234B1 (en) * 2007-06-07 2009-11-06 Commissariat Energie Atomique MULTI-COMPONENT DEVICE INTEGRATED IN A SEMICONDUCTOR MATRIX
FR2934082B1 (en) 2008-07-21 2011-05-27 Commissariat Energie Atomique MULTI-COMPONENT DEVICE INTEGRATED IN A MATRIX
FR2947948B1 (en) 2009-07-09 2012-03-09 Commissariat Energie Atomique HANDLE PLATE HAVING VISUALIZATION WINDOWS
GB2582382B (en) * 2019-03-22 2023-10-25 Cirrus Logic Int Semiconductor Ltd Semiconductor structures

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1044689A (en) * 1962-09-21 1966-10-05 Standard Telephones Cables Ltd Improvements in or relating to mountings for semi-conductor devices
GB1073910A (en) * 1965-06-23 1967-06-28 Ibm Improvements in and relating to electrical connections to a solid state device
US3570115A (en) * 1968-05-06 1971-03-16 Honeywell Inc Method for mounting electronic chips
US3903590A (en) * 1973-03-10 1975-09-09 Tokyo Shibaura Electric Co Multiple chip integrated circuits and method of manufacturing the same
GB2130794A (en) * 1982-11-27 1984-06-06 Prutec Ltd Electrical circuit assembly
US4466181A (en) * 1981-12-04 1984-08-21 Clarion Co., Ltd. Method for mounting conjoined devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1044689A (en) * 1962-09-21 1966-10-05 Standard Telephones Cables Ltd Improvements in or relating to mountings for semi-conductor devices
GB1073910A (en) * 1965-06-23 1967-06-28 Ibm Improvements in and relating to electrical connections to a solid state device
US3570115A (en) * 1968-05-06 1971-03-16 Honeywell Inc Method for mounting electronic chips
US3903590A (en) * 1973-03-10 1975-09-09 Tokyo Shibaura Electric Co Multiple chip integrated circuits and method of manufacturing the same
US4466181A (en) * 1981-12-04 1984-08-21 Clarion Co., Ltd. Method for mounting conjoined devices
GB2130794A (en) * 1982-11-27 1984-06-06 Prutec Ltd Electrical circuit assembly

Also Published As

Publication number Publication date
GB8707249D0 (en) 1987-04-29
GB2202673A (en) 1988-09-28

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