GB2202673A - Multiplechip assembly - Google Patents
Multiplechip assembly Download PDFInfo
- Publication number
- GB2202673A GB2202673A GB08707249A GB8707249A GB2202673A GB 2202673 A GB2202673 A GB 2202673A GB 08707249 A GB08707249 A GB 08707249A GB 8707249 A GB8707249 A GB 8707249A GB 2202673 A GB2202673 A GB 2202673A
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- chips
- wafer
- lands
- chip
- tracks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
A plurality of chips are mounted on a substrate consisting of a thick silicon wafer having chip-receiving apertures (58 to 62). Conductive tracks are formed between contact pads on the lands between the apertures. The chips (64 to 68) are inserted with front surfaces coplanar with the tracks on the lands (Fig. 2d) and electronic beam lithography apparatus is employed to map required interconnecting paths between the land contact pads and contact pads on the chips and to form the required interconnection paths in accordance with the map. <IMAGE>
Description
DESCRIPTION
Title: The Semi-Coriductor Fabrication
Field of invention
This invention concerns the fabrication of integrated circuits typically in silicon and is concerned with the mounting and interconnection of a plurality of devices on a single substrate without sacrificing the advantages of single chip integration to a wafer scale of integration.
Background to the invention
Integrated circuits are conventionally fabricated in silicon or other semi-conductor materials. Typical dimensions of the active part of such devices commonly referred to as the chip, are of the order of 5mm x Smm and each chip either contains a number of circuit blocks such as memory, logic, interface sections etc. or has a single specialised function. Generally chips cannot be made very much larger because of the increase chance of failure in some element which would make the -whole circuit inoperable. Many advantages are gained if chips could be made larger but these advantages are lost if several chips have to be interconnected by bonding wires from one set of pads on one,rhip to another set of pads on a separate chip.It is an object of the present invention to provide a method of mounting and interconnecting chips mounted on a common substrate without sacrificing the advantages of single chip integration, to a wafer scale of integration.
The invention also enables devices having different functions and elements such as sensors to be mounted on a single substrate and interconnected.
Summary of the invention
According to one aspect of the present invention in a method of mounting a plurality of chips on a substrate, apertures are formed in a thick silicon wafer which comprises the substrate leaving lands therebetween, a pattern of electrically conductive tracks is applied to the lands, using one or more levels if required, the interconnecting tracks so formed terminating in contact pads arranged in lines along the edges of the apertures, the selected chips are fitted in the apertures and sealed in position with the front surface of the chips in the same plane as the contact pads of the interconnecting tracks on the lands, any gap between chip and land is filled and the wafer is inserted in to the vacuum chamber of an electron beam lithography apparatus and a map of the contact points on the wafers and surrounding lands is made using the electron beam in an inspection mode and the coordinates of the contact points are computed and stored in a memory associated with the control apparatus of the electron beam lithography apparatus, the wafer and chips are covered with a resist and conductive internal is laid down to interconnect the contact points on the lands and the chips using electron beam lithographic techniques.
In one arrangement lift off is used to make aluminium interconnecting tracks.
Alternatively a layer of aluminium is placed to cover and overlap the contact and etching is used to define the interconnections and the ends of the aluminium tracks are sintered to the contact points for good electrical contact.
An advantage of the invention is that each individual chip or other device such as sensor can be tested before it is inserted into an aperture in the wafer and after interconnection, the completed device can be tested and if there is any failure, it will almost certainly arise from a breakdown in fabrication of the interconnections which can then be repaired in some circumstances by focused ion beam lithography or by a repeat of the electron beam process.
A significant advantage of the invention is that the degree of alignment between chip born contact pads and corresponding pads on the surrounding lands of the wafer is much less critical than has hitherto been necessary since the unique position of each contact pad which is to be interconnected with another contact pad is determined during the inspection mode and the co-ordinate information subsequently used to accurately position the electron beam during subsequent steps in which the interconnecting tracks are to be laid down.
Interconnection between interconnecting tracks on different levels can be achieved using vias or crossovers.
The invention thus enables the interconnection of misaligned pads on chips and lands without a mask.
The invention also enables a planarising of the chips relative to the surrounding land material and furthermore enables the pre-testing of the chips and where appropriate the interconnecting tracks on the lands.
The invention also lies in a semi-conductor device carrying two or more chips interconnected in accordance with the invention.
The invention will now be described by way of example with reference to the accompanying drawings in which:
Figure 1 illustrates to an enlarged scale two adjoining chips mounted in a wafer and interconnected with connecting pads in accordance with the invention,
Figure 2 illustrates step by step how different chips can be mounted within a wafer in accordance with the invention,
Figure 3 illustrates to an enlarged scale how a pair of power line interconnects can be provided on a land of a support substrate and
Figure 4 illustrates how signal interconnects can overlay power line interconnects.
Figure 1 illustrates part of the top surface of a support substrate having chips such as 10 and 12 mounted therein and interconnected in accordance with the invention by means of land tracks such as 14 to 24 which are connected to conductive pads such as 26, 28 etc. on the lands. The latter are generally designated 30 and are themselves, connected to conductive pads such as 32 to 38 on the two chips 10 and 12 respectively, by means of conductive tracks such as 40, 42, 44 and 46 respectively, which are laid down in accordance with the invention.
The land tracks 14 to 24 etc. are fabricated after the chip positions have been decided on and marked out, but before the holes for the chips are cut.
In accordance with the invention, the chip-land interconnects 40, 42, 44 and 46 are formed using electron beam lithographic techniques after the chips 10, 12 etc.
have been secured in place and the chip and land surfaces planarised.
Where land tracks have to overlap this can be achieved using bridging techniques or vias. Two such vias are shown in Figure 1 at 48 and 50.
The land tracks are typically in the range 10 microns to 20 microns width and a spacing of approximately 10 microns.
Figures 2a to 2d illustrate how chips can be mounted in a silicon wafer.
As shown in Figure 2a a thick silicon wafer 52 having a thickness which is greater than the thickest chip to be mounted therein, is prepared to a particular design to accommodate the chips to be mounted. Thus the chip positions are marked as required by the design but the apertures within which the chips are to be fitted are not cut at that stage. The design of the interconnections between the chips is decided on and implemented using masking or electron beam lithography techniques. Thus conductive pads such as 26, 28 etc. together with conductive interconnect tracks such as 14, 16, 18 etc.
are formed on the surface of the wafer, in several layers where appropriate, insulation between one layer and another being achieved using layers of silicon dioxide or some other suitable insulating material.
It is an advantage of the present invention that the land interconnects can at this stage be checked for conformity with the design, continuity, current carrying capacity and high frequency performance as appropriate. The interconnects on the wafer can thus be proved before chips are committed thereto and this helps to reduce the number of rejects after the chips have been mounted in the wafers. Any land interconnect systems which do not come up to specification can be rejected before chips are fitted. A thin layer 54 of protecting material such as resist or PMMA is applied to the surface of the wafer and holes are made in the wafer at the previously marked chip positions. The holes 58, 60 and 62 into which chips are to be fitted are made slightly oversize as compared with the actual dimensions of the chips to be fitted therein.
The wafer 52 is shown in Figure 2b mounted face down on another resist coated silicon wafer 56.
The chips such as 64, 66 and 68 are inserted into the holes 58, 60 and 62 respectively, face downwards, and pressed against the resist surface 54 in order to achieve maximum planarisation. Pressure clamps may be used to ensure a perfectly plane surface if desired. The direction of the applied pressure is shown by way of the arrows 70 and resin is then poured into the openings containing the chips to seal the chips in position, the resin penetrating to seal any gaps between the chips and the holes in the wafer. The remainder of the volume above each chip in each hole is then back filled with a suitable compound which preferably has a good thermal conductivity to assist in conducting heat away from the back surface of each chip. The back fill material is designated by reference numeral 72 in the case of chip 64, 74 in the case of chip 66 and 76 in the case of chip 68.
The planarising resist 54 also serves to prevent resin from penetrating to the surface. After the back fill material 72 etc. has set, the wafer can be removed from the supporting wafer 56 and the planarising resist layer 54 on the wafer 52 can be removed to leave a wafer-chip composite as shown in Figure 2d in which the upper surfaces of the lands of wafer and the upper surfaces of the chips are co-planer.
Since land interconnects such as 14, 16 and 18 etc. have already been formed on the upper surfaces of the lands such as 70, 78, 80, 82 and 84 of Figure 2d, the contact pads such as 26 and 28 etc. are also formed on the lands and chip interconnect pads such as 32, 34 also exist on the chips 64, 66 etc., it is now only necessary to form conductive tracks such as 40 between the chip pads 32, 34 etc. and the land conductive pads 26, 28 etc. to achieve full fabrication.
Since the pads 32, 34 and 26, 28 etc. are all in the same plane it is possible to use electron beam lithography techniques to lay down the conductive tracks such as 4O, 42 etc. in accordance with the invention.
It is to be understood that at this juncture, the pads 32, 34 etc. and the pads 26, 28 etc. are not necessarily perfectly aligned. Indeed there will be some degree of random misalignment due to the fact that the holes within which the chips are fitted are of a necessity slightly oversize. The difference between the misalignment in one wafer structure and another constructed in the same way as described in to Figures 2a to 2d, will be small, but the particular pattern of misalignment pattern applicable to one wafer/chip assembly will not necessarily be the same as the misalignment pattern of another wafer/chip assembly and it is for this reason that the invention provides for individual "chip to land" interconnections using electron beam lithography techniques.
It will be appreciated that any conventional mask solution to produce the interconnecting links between the chip pads and the land pads, would require inspection to determine the positions and a new mask to be made for each wafer/chip assembly.
In accordance with the invention the wafer/chip assembly of Figure 2d is fitted in an electron beam lithography system and the co-ordinates of all the contact points for each chip both on the chip and on the land surrounding it are found by reflected electrons and stored in a computer memory. The wafer/chip assembly is then removed, coated with resist and the tracks between contact points are opened using positive resist. Lift-off is used to make aluminium interconnecting tracks.
In an alternative method, a layer of aluminium is placed so as to cover and overlap the contacts and etching is used to define the interconnecting paths. After etching the aluminium strips are sintered to the chip and land contacts to ensure good electrical connections.
Whether a resist or an etching technique is used, the completed wafer/chip assembly can then be tested. Since the land interconnects have been proved before the chips are fitted, any electrical failure in the overall fabrication can be attributed to faulty chip/land interconnects and these can either be repaired or a fresh set of conductive links fabricated by a repeat electron beam process.
The method of forming the chip to land interconnects such as 40, 42 etc. involves:1. Inspecting the surface of the wafer/chip composite using an electron beam and determining the position of each conductive pad such as 32, 34 on each chip and the respective pads such as 26 28 on the adjoining land and inserting co-ordinate information relating to the positions of the pads found by the inspection process into a computer memory. The information within the memory allows a mapping of the co-ordinate locations during a subsequent electron beam scanning process providing a bench mark or other starting position is marked or determined during the initial scanning. No mention has been made of this hitherto since the use of bench marks is well known in the art.
2. The wafer is then removed from the electron beam vacuum chamber and covered with resist. The resist coated wafer is then inserted once again into the electron beam vacuum chamber and the latter evacuated and each contact point such as 32, 26 etc. is located during a subsequent mapping operation using the electron beam. As each contact point is found the electron beam removes the resist material to expose each conductive region therebelow and resist is also removed along the preferred lines of the conductive tracks which are to be laid down between the pairs of conductive pads such as 32 and 26 to enable them to be electrically connected together. Metal is then applied for example by deposition, after which surplus resist can be removed.Alternatively aluminium foil may be applied to the resist covered surface and sintered to the conductive pads such as 32 and 26 using electron beam sintering and then etched, using the electron beam to define the tracks such as 40, whereupon surplus resist and surplus are foil are removed.
A protective coating may be applied to the final wafer/chip assembly in known manner in the form of a varnish or the like.
It is to be understood that the reference to chips includes within that term any semi-conductor device which may be an integrated circuit or sensor and the invention is of particular application in the fabrication of devices incorporating sensors such as heat, light, humidity, strain and the like sensing devices where hitherto discreet connections have had to be made to the sensors mounted on printed circuits boards and the like. To this end sensor related circuits can now be micro fabricated in exactly the same way and to the same density as integrated circuits.
The primary advantage of the invention however is the elimination of accurate alignment of chips and lands and the avoidance of the need to create specific one-off masks if lithography is to be used for generating the conductive tracks between the conductive pads on the lands and chips of an array in which the alignment cannot be sufficiently guaranteed to allow a common mask to be employed.
Figure 3 illustrates how conductive tracks of some one micron thickness designated by reference numerals 86 to 88 can be applied to an insulating layer such as silicon dioxide 90 on the upper surface of a land of a wafer such as 92. Typically the metallic tracks are a metal oxide material.
Where it is desired that further tracks overlay the tracks 86 and 88, this can be achieved by forming a further layer of insulant such as 94 also of silicon dioxide or the like over the first conductive tracks 86 and 88 and using lithographic techniques or masking techniques to overlay further metallic oxide layers in the form of further tracks 96 and 98 over the silicon dioxide layer 94.
Further protective silicon dioxide layer 100 may be applied to the outer tracks 96 and 94.
Claims (12)
1. A method of mounting a plurality of chips on a
substrate, according to which apertures are formed in a
thick silicon wafer which comprises the substrate leaving
lands therebetween, a pattern of electrically conductive
tracks is applied to the lands, the interconnecting tracks
so formed terminating in contact pads arranged in lines
along the edges of the apertures, the selected chips are
fitted in the apertures and sealed in position with the -front surface of the chips in the same plane as the
contact pads of the interconnecting tracks on the lands,
any gap between a chip and a land is filled and the wafer
is inserted in to the vacuum chamber of an electron beam
lithography apparatus, whereupon a map of the contact
points on the wafers and surrounding lands is made using
the electron beam in an inspection mode and the co
ordinates of the contact points are computed and stored in
a memory associated with the control apparatus of the
electron beam lithography apparatus, the wafer and chips
are covered with a resist, and conductive material is laid
down to interconnect the contact points on the lands and
the chips by use of the electron beam lithography
apparatus.
2. A method according to claim 1, wherein the pattern of
conductive tracks on the lands is applied in a plurality
of levels, using vias or cross-overs.
3. A method according to claim 1 or claim 2, wherein the
land/chip interconnections are made by metal deposition after using the lithography apparatus to remove the applied resist layer from the interconnection paths defined by the stored map.
4. A method according to claim 1 or claim 2, wherein the land/chip interconnections are made by using the lithography apparatus to etch a metal layer along the interconnection paths defined by the stored map, the metal layer having been initially applied over the resist layer.
5. A method according to claim 4, wherein the land/chip interconnections are made by etching aluminium foil applied over the layer of resist and sintered to the contact pads at the contact points.
6. A method according to any of claims 1 to 5, wherein the conductive tracks on the lands are made before inserting the chips into the apertures, preferably before the apertures are formed in the wafer.
7. A method according to claim 6, wherein the conductive tracks on the lands are tested before committing the chips to the wafer.
8. A method according to any of claims 1 to 7, in which, before insertion of the chips into the wafer, a layer of resist is applied to serve as a planarising layer against which the front surfaces of the chips are pressed to ensure coplanarity of said surfaces with the contact pads of the conductive tracks on the lands.
9. A method according to any of claims 1 to 8, wherein the holes in the wafer one made slightly oversize and a material of good thermal conductivity is employed to seal the chips in position from the back and also to fill in gaps between the holes and the chips.
10. A method according to any of claims 1 to 9, wherein a protective coating is applied to the completed wafer/chip assembly.
11. A method of mounting chips on a substrate, substantially as hereinbefore described with reference to the accompanying drawings.
12. A semi-conductor device carrying two or more chips, when produced by the method of any of clams 1 to 11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8707249A GB2202673B (en) | 1987-03-26 | 1987-03-26 | The semi-conductor fabrication |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8707249A GB2202673B (en) | 1987-03-26 | 1987-03-26 | The semi-conductor fabrication |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8707249D0 GB8707249D0 (en) | 1987-04-29 |
| GB2202673A true GB2202673A (en) | 1988-09-28 |
| GB2202673B GB2202673B (en) | 1990-11-14 |
Family
ID=10614700
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8707249A Expired - Lifetime GB2202673B (en) | 1987-03-26 | 1987-03-26 | The semi-conductor fabrication |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2202673B (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2224600A (en) * | 1988-10-29 | 1990-05-09 | Stc Plc | Circuit assembly |
| EP0472451A1 (en) * | 1990-08-21 | 1992-02-26 | Thomson-Csf | Hybrid integrated circuit interconnection structure and method of fabrication |
| EP0478426A1 (en) * | 1990-09-28 | 1992-04-01 | Thomson-Csf | Method of fabrication for a hybrid module |
| FR2672427A1 (en) * | 1991-02-04 | 1992-08-07 | Schiltz Andre | METHOD AND DEVICE FOR INSERTING CHIPS INTO HOUSINGS OF A SUBSTRATE BY INTERMEDIATE FILM. |
| EP0746020A2 (en) * | 1995-05-30 | 1996-12-04 | General Electric Company | Scaled adaptive lithography |
| EP0777274A1 (en) * | 1995-11-30 | 1997-06-04 | Lockheed Martin Corporation | A high density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate |
| WO2000002247A1 (en) * | 1998-07-06 | 2000-01-13 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method and device for producing an interconnection between a carrier element and at least one component contained therein |
| US6281114B1 (en) * | 2000-02-07 | 2001-08-28 | Infineon Technologies Ag | Planarization after metal chemical mechanical polishing in semiconductor wafer fabrication |
| EP1387394A2 (en) * | 1997-04-15 | 2004-02-04 | STMicroelectronics S.r.l. | Process of final passivation of integrated circuit devices |
| DE102005007423B3 (en) * | 2005-02-18 | 2006-06-14 | Atmel Germany Gmbh | Integration of electronic component (8) into substrate by formation of dielectric insulating layers on substrate front side useful in structural element modelling in semiconductor flip-chip technology with photoresistive layer in cavity |
| WO2008012481A1 (en) * | 2006-07-28 | 2008-01-31 | Microcomposants De Haute Sécurité Mhs | Process for fabricating an encapsulated integrated circuit and associated encapsulated integrated circuit |
| FR2917234A1 (en) * | 2007-06-07 | 2008-12-12 | Commissariat Energie Atomique | MULTI-COMPONENT DEVICE INTEGRATED IN A SEMICONDUCTOR MATRIX |
| EP1153429B1 (en) * | 1998-09-09 | 2009-11-25 | Telefonaktiebolaget LM Ericsson (publ) | An electronic arrangement comprising a component carrier and a method of producing an electronic arrangement |
| EP2148366A1 (en) | 2008-07-21 | 2010-01-27 | Commissariat a L'Energie Atomique | Device having plurality of integrated circuits in a matrix |
| US8288841B2 (en) | 2009-07-09 | 2012-10-16 | Commissariat à l'énergie atomique et aux énergies alternatives | Handle wafer having viewing windows |
| GB2582383A (en) * | 2019-03-22 | 2020-09-23 | Cirrus Logic Int Semiconductor Ltd | Semiconductor structures |
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| GB1073910A (en) * | 1965-06-23 | 1967-06-28 | Ibm | Improvements in and relating to electrical connections to a solid state device |
| US3570115A (en) * | 1968-05-06 | 1971-03-16 | Honeywell Inc | Method for mounting electronic chips |
| US3903590A (en) * | 1973-03-10 | 1975-09-09 | Tokyo Shibaura Electric Co | Multiple chip integrated circuits and method of manufacturing the same |
| GB2130794A (en) * | 1982-11-27 | 1984-06-06 | Prutec Ltd | Electrical circuit assembly |
| US4466181A (en) * | 1981-12-04 | 1984-08-21 | Clarion Co., Ltd. | Method for mounting conjoined devices |
-
1987
- 1987-03-26 GB GB8707249A patent/GB2202673B/en not_active Expired - Lifetime
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1044689A (en) * | 1962-09-21 | 1966-10-05 | Standard Telephones Cables Ltd | Improvements in or relating to mountings for semi-conductor devices |
| GB1073910A (en) * | 1965-06-23 | 1967-06-28 | Ibm | Improvements in and relating to electrical connections to a solid state device |
| US3570115A (en) * | 1968-05-06 | 1971-03-16 | Honeywell Inc | Method for mounting electronic chips |
| US3903590A (en) * | 1973-03-10 | 1975-09-09 | Tokyo Shibaura Electric Co | Multiple chip integrated circuits and method of manufacturing the same |
| US4466181A (en) * | 1981-12-04 | 1984-08-21 | Clarion Co., Ltd. | Method for mounting conjoined devices |
| GB2130794A (en) * | 1982-11-27 | 1984-06-06 | Prutec Ltd | Electrical circuit assembly |
Cited By (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2224600B (en) * | 1988-10-29 | 1992-03-18 | Stc Plc | Circuit assembly |
| GB2224600A (en) * | 1988-10-29 | 1990-05-09 | Stc Plc | Circuit assembly |
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| GB2582384A (en) * | 2019-03-22 | 2020-09-23 | Cirrus Logic Int Semiconductor Ltd | Semiconductor structures |
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Also Published As
| Publication number | Publication date |
|---|---|
| GB8707249D0 (en) | 1987-04-29 |
| GB2202673B (en) | 1990-11-14 |
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