GB2150750A - One transistor-one capacitor DRAM - Google Patents

Abstract

A DRAM has a plurality of memory cells each formed of a series connection consisting of a capacitor C and a MISFET Q. A first electrode (7) of the storage capacitor (C) is formed on a semiconductor substrate (1) and is electrically connected with one semiconductor region 6 of the MISFET (Q). A semiconductor region (4) which has a conductivity type identical to that of the semiconductor substrate (1) and an impurity concentration higher than that of the semiconductor substrate is used as a second electrode of the storage capacitor (C). Charges to serve as information are stored in the storage capacitor by principally utilizing the charges of an accumulation layer and the space charges of a depletion layer in the region 4. The depletion layer is narrower or removed, and an inversion layer is prevented from developing. The degree of influence of unnecessary minority carriers attributed to alpha -particles or the injection thereof from a peripheral circuit is reduced, and adjacent memory cells are electrically isolated by the semiconductor region. The capacitor can be formed in a groove in the substrate and it may have further metal plates overlying the electrode 7. A field oxide 2 may be omitted. <IMAGE>

Description

SPECIFICATION Asemiconductor memory device The present invention relatesto a semiconductor memory device, and more particularly to a technique which is effective when applied to a dynamic random access memory (DRAM).

Each memory cell of a DRAM consists of a storage capacitor and a switching MISFET. The storage capacitor is constructed of a capacitor of the MIS type.

Specifically, it is constructed of a semiconductor substrate, an insulatorfilm which is formed on the semiconductor substrate, and a capacitor electrode which is formed on the insulatorfilm and to which a predetermined voltage is applied. Charges in a quantity corresponding to the information of "1 " or "0" are stored in an inversion layerwhich isformed within the semicondcutor substrate underthe capacitor electrode having the predetermined voltage applied thereto.

For integrating the DRAM ata high packing density, it is effective to make the capacitor small in area while holding a capacitance of certain magnitude.

A DRAM which meets this requirement is disclosed in Japanese Patent Application No.53883/75. The capacitor of th is DRAM is constructed of a trench (also called "U-groove")which is formed so as to extend from one main surface of a semiconductor substrate inwardly ofthe same, an insulatorfilm which is formed along thetrench, and a capacitor electrode which is formed so asto cover the insulatorfilm.

It holds true, however, that charges are stored in a depletion layer and an inversion layerwithin the semiconductor substrate.

We have found by experiment thatthe DRAM composed of memory cells of the type which stores charges in a depletion layer and an inversion layer is not suited for high-density integration.

The memory cell ofthistype cannot exclude the influence of minority carriers appearing due too:- particles or minority carriers injected from a peripheral circuit portion. Insofar as the charges are stored in the depletion Iayerandthe inversion layer, the quantity of charges fluctuates due to the minority ca rri ers. Accordi ngly, the occupying area of a storage capacitor cannot be made smallerthan a certain value.

Since the influence ofthe minority carriers increases the deeper one goes from the surface of a semiconductor substrate, deepening the trench is notvery effective.

Moreover, with the memory cells ofthe specified type, it is impossible to reduce in size an isolation region for electrically isolating the adjacent memory cells. The reason is that, since the depletion layers and inversion layers ofthe capacitors of the adjacent memory cells need to be prevented from coupling, the distance between the memory cells cannot be made smallerthan a certain value. In the case where a field oxide film is used as the isolation region, the problem of bird's beak is also involved. Meanwhile, the depletion layer couples to the depletion layer of the adjacenttrench more easily inthe deep partofthe trench than in the shallow part thereof. For this reason, the distance between the trenches cannot be made smallerthan a certain value.

It is an object ofthe present invention to provide a DRAM capable of integration at a higher packing density.

Another object of the present invention is to prevent the leakage of charges between the storage capacitors ofthe adjacent memory cells of a DRAM, and to reduce the degree of influence of minority carriers in the storage capacitor of the memory cell of a DRAM.

Yet another object of the present invention is to lengthen the data retension time of the storage capacitors of a DRAM, thereby making it possible to enhance the operating speed ofthe DRAM.

According to a first aspect ofthe present invention there is provided a semiconductor memory device having memory cell arrays in which memory cells are arranged in the shape of a matrix, said each memory cell comprising a switching element and a capacitor which is formed on a main surface of a semiconductor substrate of a first conductivity type and which is connected with said switching element, wherein:: (a) said capacitor comprises a first insulatorfilm which is formed on the main surface of said semiconductor substrate, a first electrode a part of which is electrically connected with said switching element and which is formed on said first insulatorfilm, said first electrode being independentforsaid each memory cell, and a first semiconductor region to serve as a second electrode, which is formed in said semiconductor substrate under said first insulator film and which hasthefirst conductivity type and an impurity concentration higherthan that of said semiconductor substrate; and (b) the first semiconductor region of one memory cell is connected with thefirstsemiconductor region of at least one ofthe memory cells which adjoin said one memory cell within the identical memory cell array by a second semiconductor region which is formed in said semiconductor substrate and which hasthefirstconductivitytypeand an impurity concentration higherthan that of said semiconductor substrate.

According to a second aspect of the present invention there is provided a semiconductor memory device having memory cell arrays in which memory cells are arranged in the shape of a matrix, said each memory cell comprising a switching element and a capacitorwhich is formed on a main surface of a semiconductor substrate of a first conductivity type and which is connected with said switching element, wherein:: (a) said capacitor comprises a first insulatorfilm which is formed on the main surface of said semiconductor substrate, a first electrode a part of which is electrically connected with said switching element and which is formed on said first insulatorfilm, said firstelectrodebeingindependentforsaideach memory cell, and a first semiconductor region to serve as a second electrode, which is formed in said semiconductorsubstrate under said first insulatorfilm and which has the first conductivity type and an impurity concentration higherthan that of said semiconductor substrate; and (b) said capacitor changes a quantity of space charges of at least a depletion layer arising within said second semiconductor region, into first and second statuses in accordance with first and second potentials which are applied to said first electrode.

The present invention will now be described in greater detail by way of examples with reference to the accompanying drawings, wherein:~ Figure 1 is an equivalent circuit diagram to illustrate the essential portions of the memory cell array of a DRAM for explaining an embodiment of the present invention; Figure 2A is a plan view ofthe essential portions of a DRAM memory cell which forms a first embodiment of the present invention; Figure 2B is a sectional view taken along line Il-Il in Figure 2A; Figures 3A and 3B are graphs for explaining the principle of the present invention; Figures 4A, 5A, 6A, 7A and 8A are plan views of the essential portionsofthe DRAM memory cell illustrating the manufacturing steps ofthe DRAM shown in Figures 2A and 2B;; Figures 48,58,68, 7B and 88 are sectional views taken along cutting-plane lines indicated in Figures 4A, 5A, 6A, 7A and 8A, respectively; Figure 5C is a plan view showing the manufacturing steps of a memory cell array in the DRAM of Figures 2A and 2B; Figure 9A is a plan view of the essential portions of a DRAM memory cell which forms a second embodi mentofthe present invention; Figure 9B is a sectional view taken along line IX-IX in Figure 9A; Figure 10 is a plan view of the essential portions of a schematic memory cell array in the DRAM shown in Figures 9A and 9B; Figures 11A and 1 2A are plan views ofthe essential portions ofthe DRAM memory cell illustrating the manufacturing steps ofthe DRAM shown in Figures 9A and 9B;; Figs. 11 B and 12B are sectional views taken along cutting-plane lines indicated in Figures 1 1A and 12A, respectively; Figures 1 3,1 4 and 15 are plan views of the essential portions of a memory cell array illustrating the manufacturing steps of a DRAM memory cell which forms a third embodiment of the present invention; Figure 1 6A is a plan view of the essential portions of a DRAM memory cell which forms a fourth embodiment ofthe present invention; Figure 16B is a sectional view taken along line XVI-XVI in Figure 16A; Figures 17A, 18A, 20A, 21A, 22A and 23A are plan views of the essential portions ofthe memory cell illustrating the various manufacturing steps of the DRAM shown in Figures 16A and 16B;; Figures 17B, 18B, 20B, B, 22B and 23B are sectional views taken along cutting-plane lines indi cated in Figures 17A, 18A, 20A, 21A, 22A and 23A respectively; Figure 19 is a plan view showing an intermediate state in the manufacturing process ofthe DRAM shown in Figuras 16A and 16B; Figure 24A is a plan view of the essential portions of a DRAM memory cell which forms a fifth embodiment of the present invention; Figure 24B is a sectional view taken along line XXIV-XXIV in Figure 24A; Figure 25 is a plan view of the essential portions of a schematic memory cell array in the DRAM shown in Figures 24Aand 24B; and Figures 26, 27 and 28 are plan views showing the manufacturing steps of a DRAM memory cell which forms a sixth embodimentofthe present invention.

Referring first to Figure 1, the memory cell array of a DRAM includes: sense amplifiers SA1, SA2 ......., each of which serves to amplifythe minute potential difference between a predetermined memory cell and a predetermined dummy cell to be described later; bit lines BL11 and BL12 which extend in the row direction from one side end of the sense amplifier SA1; bit lines BL21 and BL22 which extend in the row direction from one side end of the sense amplifier SA2. These bit lines B L serve to transmit charges as information. The memory cell array also includes word lines WL1 and WL2 which extend in the column direction and word lines WL3 and WL4which also extend in the column direction.The word lines WL1 and WL2 are connected to predetermined gate electrodes which constitute the switching MlSFETsofthe dummy cells to be described later, and they serve to turn "on" and "off" these MISFETs. The word lines WL3 and WL4 are connected to predetermined gate electrodes which constitute the switching MlSFETs ofthe memorycellsto be de scribed later, and they serve to tu rn "on" and "off" these MlSFETs. The memory cell array further in cludes memory cells M11, M12, M21, M22,......which hold the charges serving as the information.The memory cells M11, M12, M21, MISFETs Q11, Q12, Q21,Q22, ...... one end of each MISFET being connected to the predetermined bit line BL and the gate electrode of each MISFET being connected to the predetermined word line WL; and capacitors C11, C12, C21 r C22,......

one end of each capacitor being connected to the other end of the respective M ISFETs Q1 f, Q12, Q21, Q22, ...... and the other end of each capacitor being connected to a fixed potential Vss such as earth potential (0 V) or a substrate back bias potential (-2.5 to -3.0 V). The memory cell array also includes dummy cells D11, D12, D21, charges permitting the judgement of "1" and "0" that are the information of the memory cells M.The dummy cells D11, D11, D12, D22, D22,...... are respectively constituted by M ISFETs 0D11 QD12, QD2l, 0D22 ......

one end of which each MISFET being connected to the predetermined bit line BL and the gate electrode of each MISFET being connected to the predetermined word lineWL; capacitors CD11, CD12, CD21, CD22,......

one end of each capacitor being connected to the other end of respective MISFETs QD11, QD12, QD21, being connected to the terminal of the fixed potential Vss; and a clearing MISFET CQwhich serves to clearthe charges stored in the capacitors CD11, CD12, CD21,CD22, ...... Aterminal ~D isconnected withthe gate electrode of the clearing MISFET CO.

The structure of the first embodiment of the present invention will be described with reference to Figures 2A and 2B.

The DRAM memory cell includes a p--type semi conductor substrate 1, which serves to constitute the DRAM; and a field oxide film 2 which is formed on the main surface portion ofthe semiconductor substrate 1 so asto be located among predetermined memory cells and among semiconductor elements constituting peripheral circuits (not shown), for example, an address selecting circuit, a reading circuit and a writing circuit, and which serves to electrically isolate them. The memory cells are surrounded with and defined by the field oxidefilms2 so that the pattern of one pair of memory cells may be repeated in the direction in which a bit line 15 to be described later extends (hereinaftercalled "row direction"). The insulatorfilms 2 are indicated by dotted lines.No insulator film 2exists between the memory cells which adjoin each other in the row direction.

The DRAM memory cell also includes an insulator film 3 which is provided on the main surface portion of the semiconductor substrate 1 in at least an area for forming a storage capacitor, and which serves to constitute the dielectric of the storage capacitor.

Charges, for example, holes are stored by the first electrode of the capacitor (hereinaftertermed "first conductive plate") and the second electrode of the capacitor (hereinaftertermed "Second conductive plate") to be described later, with the insulatorfilm 3 interposed therebetween.

A p±type semiconductor region 4 serves as the second conductive plate, which is provided in the surface of the semiconductor substrate 1 in the area for forming the storage capacitor and which is provided integrally with the storage capacitors adjacent in the row direction. It serves to constitute the storage capacitor C and simultaneously to electrically isolate the storage capacitors adjacent in the row direction.The p±type semiconductor region 4 is provided in orderthatthe charges of holes or the charges of a depletion layer to be stored in the capacitor with the insulator film 3 interposed between this region 4andthefirstconductive plate may be obtained in as great a number as possible, or that a threshold voltage higherthan a voltage which is applied to the first conductive plate to be described later may be provided in the vicinity of the surface of the semiconductor substrate 1. The semiconductor region 4 serves also to suppress the stretch of the depletion layerwhich is formed, upon the application ofthe voltage to the first conductive plate, so as to extend from the underlying surface portion of the semiconductor substrate 1 inwardly of this semiconductor substrate.The semiconductor region 4 may have an impurity concentration higher than that of the semiconductor substrate 1.The p±typesemiconduc- tor region 4 should desirably be located apartfrom an n±type semiconductor region to be described later.

This is intended to avoid lowering in the breakdown voltage of a junction.

A contact hole 5 serves for electrically connecting the first conductive plate 7 to be described later and one semiconductor region 6 or 12 of a MISFET Q. The n±type semiconductor region 6 is formed in the surfaceofthesemiconductorsubstrate 1 corresponding to the contact hole 5, and serves to electrically connect the first conductive plate to be described later and onesemiconductor region of the MISFET Q.

The first conductive plate 7 is provided on the insulatorfilm 3 in the storage capacitorforming area independently for each memory cell, in such a manner that one end part thereof is electrically connected through the contact hole 5 and the semiconductor region 6with onesemiconductorregion ofthe MISFET Qto be described later. The first conductive plate7 serves to constitute the storage capacitor C. It is indicated by a two-dot chain line. The storage capacitorC ofthe memory cell is principallycomposed ofthe first conductive plate 7, the semiconductor region 4 being the second conductive plate, and the insulatorfilm 3.

An insulatorfilm 8 is formed so as to cover the first conductive plate 7, and serves for electrically isolating the first conductive plate 7 and a word line 11 to be described later.

An insulatorfilm 9 is provided on the main surface portion of the semiconductor substrate 1 in the MlSFETforming area, and serves principally to construct a gate insulatorfilm. A gate electrode is formed on the predetermined insulatorfilm 3, and serves to construct the MISFET Q.

The word line (WL) 11 is arranged so as to be electrically connected with the gate electrodes 10 of the memory cells adjacent in the column direction and to extend in the column direction integrally with the gate electrodes 10. It serves for turning "on" and "off" (switching operation) MISFETs to be described later (hereinafter, the direction in which the word line 11 extends shall be called the column direction).

As shown n±type semiconductor regions 12 are formed in the surface ofthe semiconductor substrate 1 on both the sides of the gate electrode 10. These regions 12 serve as a source region and a drain region of the MISFET Q. The switching transistor (MISFET) Q is composed ofthe gate electrode 1 the semiconductor regions 12 and the insulatorfilm 9. One ofthe semiconductor regions 12 is electrically connected with the semiconductor region 6, and is electrically connected with the first conductive plate 7 as connected with the first conductive plate 7 as stated above.

An insulator film is formed so as to cover the whole surface, and serves for electrically isolating the gate electrode 10 as well as the word line (WL) 11 and a bit line 15to be described later.

A contact hole 14 is provided by locally removing the insulatorfilms 9 and 13 on the other semiconductor region 12, and serves for electrically connecting the semiconductor region 12 and the bit line to be described below.

The bit line (BL) 15 is arranged in a mannerto be electrically connected with the semiconductor region 12 through the contact hole 14and to extend in the row direction. It serves to transmit a voltage serving as information.

The principleof operation ofthe DRAM according to the present invention having the above construction will now be described with reference to Figures 3A and 3B. In these figures, the axis of the abscissa represents the voltage value Vp [ Vi which is applied across the two capacitor electrodes ofthe MIS type storage capacitor. The axis of the ordinate represents the concentration of charges Qsc [ icm2j per unit area, the charges being held in the surface of the lower p-type semiconductor region bythe voltage applied across the capacitor electrodes. The axis of the ordinate has a logarithmicscale.Since, in Figures 3A and 3B, the p-type silicon semiconductor substrate is exemplified, the charges to be induced in the surface are negative charges for the voltages across the capacitor electrodes, V > VFB and positive charges for Vp < VFB. In this case VFB denotes a flatband voltage. The negative charges are electrons or acceptor impurities, while the positive charges are holes.

Figure 3A illustrates the case where the holes which are space charges in the depletion layer are principally utilized as the charges which are stored as information. This corresponds to the case where the p±type semiconductor region 4shown in Figures 2A and 2B is included.

The principle of the prior art DRAM will be first explained with reference to Figure 3A.

Curves (a), (b) and (c) illustrate the relationships between the voltage Vp and the charge concentration QSC in the vicinity of the surface, in the prior art DRAM.

In the figure, h indicates an accumulation region in which an accumulation layer is formed, ka depletion region in which a depletion layer is formed, and man inversion region in which an inversion layer is formed.

In the figure, the curves (a), (b) and (c) indicate the numbers of electrons and acceptor impurities (the numbers of negative charges) nandthe number of holes pin the case where the threshold voltage (Vth) of the vicinity ofthe semiconductor substrate surface in the storage capacitor is rendered about -0.2 V. The curve (a) indicates the number of holes pin the accumulation region h, which is expressed by p = ,COX/q (VP~VFB)! - ~ ~ ~ ~ ~ (1). The curve (c) indicates the numberofelectrons and acceptor impurities n in the inversion region m, which is expressed by n= C,q (Vp~Vth) ...... (2). Here, COX denotes the thickness of the insulatorfilm which is the dielectric of the capacitor.The curve (b) indicates the number of acceptor impurities appearing in the state (deep depletion state) in which no inversion layer is formed despite the inversion region, the number being approximately expressed by Qse &alpha; A/VP~VFB. When, from the above, the surface charge concentrations Qsc in the essential parts ofthe curves (a), (b) and (c) are evaluated, the surface negative charge concentration atthe voltage Vp = Vth becomes OIF = 1 X 1011 [ /cm2 ] , and the surface negative charge concentration at the voltage Vp = 0 becomes Q10 = 2.2 x 1011 [ /cm21.

In the storage capacitor of the prior-art DRAM memory cell, charges to serve as information have been the electrons in the inversion region m. Specifically, a fixed voltage, for example, a voltage of about 5 [ V ] is applied across the capacitor electrodes so asto bring the operating region into the inversion region m.

Thereunder, the quantity of charges 01L in the case of forming the inversion layer byexternallysupplying charges (the state ofthe curve (c) ) and the quantity of charges OIH in the case ofthe deep depletion state without externally supplying charges (the state ofthe curve (b) ) are established in correspondence with information. Byway ofexample,the quantity of charges OIL corresponds to a signal "0" (namely, "L"), and the quantity of charges QIH a signal " (namely, "H"). The signals are read out by utilizing the difference of the quantities of charges in the two statuses, A QI = QIL - OIH = 5.3 x 1012 [/cm].

In contrast, in the storage capacitorofthe DRAM memory cell ofthe present invention, the charges to serve as information are space charges in, at least, a depletion region. That is, the DRAM ofthe present invention is characterized in that an inversion layer is not utilized.

Curves (d) and (e) illustrate the relationships between the voltage ofthe capacitor electrode (the voltage ofthefirst conductive plate) Vp and the charge concentration QSC in the vicinity of the surface of the semiconductor region 4, in the DRAM ofthe present invention.Thecurve(d)approximatesa curvewhich is obtained by moving the curve (a) in the negative direction of the voltage Vp (leftward in the figure). The curve (e) indicates the quantity of space charges which appear in the depletion layer, not in the inversion state. The flatband voltage is set at VFBD = - 1.2 [V] from VFB = -0.9 [V] in the prior art.In order to increase the quantity of space charges in the depletion state by scarcely changing theflatband voltage, the p±type semiconductor region 4 is formed. Specifically the impurity concentration is raised to 1.5 x 1 o19 [ /cm3 ] from the impurity concentration ofthe p--type substrate 1, which is 1.5 x 1015 [ 1cm3 ] . Thus, the quantity of charges to be fetched is increased. The ranges of voltages to establish the accumulation region h, the depletion region kand the inversion region m change similarly.

As thus far described, the space charges of the depletion region are permitted to be effectively utilized by changing the relationship between Vp and Qsc. More specifically, when the first conductive plate 7 being the capacitor electrode has Vp = 0 [ Vi or5 [V] applied thereto in correspondence with information, the quantity of charges as the information to be stored changes in accordance with the curve (e).That is, the inversion layer is notformed, and the deep depletion state is established. Thus, the quantity of charges QDL at Vp = 0 [V] orthe quantity of charges QDH at Vp = 5 [V] is stored. Byway of example, the quantity of charges QDL corresponds to a signal "0", and the quantity of charges QDH a signal "1".When the difference between the two quantities of charges, A Qo = QDH QDL = 5.6 x 1012 [ 1cm2 ] is utilized, the information of 1 bit can be stored in the memory cell. This quantity of charges is equal or above that of the memory cell of the prior-art DRAM described before. In this manner, the sufficient quantity of charges is obtained without utilizing the inversion layer.

Fig. 3B illustrates the case where holes in the accumulation region are principally utilized as charges which are stored as information. This correspondsto a case offorming a very shallow p±type ion implantation region, notto the case offorming the deep p±type semiconductor region as in Figs. 2A and 2B. That is, it exemplifies the case where boron ions are ion-implanted shallowly so asto function as surface charges apparently. The same parts as in Fig.

3A are indicated by identical symbols, and are thus omitted from the description.

Curves (f) and (g) are approximate to curves which are respectively obtained by shifting the curves (a) and (b) in the positive direction ofthe voltage Vp (right ward in the figure) by fixed values. Specifically, the flatband voltage is raised to VFBA = +5.2 [V] from VFBI = -0.9 [V] in the prior art. To this end, surface charges are increased by implanting boron ions to be very shallow. The ranges of the voltages Vp to establish the accumulation region h, the depletion region kand the inversion region m change similarly by the variation of theflatband voltage.

As thus far described, the holes in the accumulated state are permitted to be effectively utilized by changing the relationship between Vp and Qsc. More specifically, when the first conductive plate 7 being the capacitor electrode has Vp = 0 V or 5.2 [ V ] applied thereto in correspondence with information, the quantity of charges as the information to be stored changes in accordance with the curves (f) and (g). That is,the inversion layer is not utilized. The quantity of charges Awl is stored atVp = 0 [V], and the quantity of charges 0AH atV# = S [ V ] . By way of example, the quantity of charges QAL corresponds to a signal "0", and that QAH a signal "1".The difference between the two quantities of charges, AQA = AQAL- AOAH is greaterthan the quantity of charges EQI in the prior art. In this manner, the sufficient quantity of charges is obtained without utilizing the inversion layer. The quantity of charges QAL is held by the holes in the stored state, and the quantity of charges QAH by the space charges in the depletion region. The charges of QAH are opposite in sign to those of QAL, but this forms no inconvenience, and the difference of the quantities of charges is indicated by AQA. In addition, atVp = 5 [ V ] ,the quantity of charges OAH is held by the holes in the stored state located on the left side of VFBA in Fig.

3B. The curves (f) and (g) can be controlled bythe dose of impurity ions. In this example, the dose is equal to that in the case of Fig. 3A.

Besidesthe principles illustrated in Figs. 3A and 3B, a DRAM which usesthetwo in combination is also possible. It is possible to increase the quantity of surface charges by any method and to simultaneously increase the quantity of space charges in a depletion layer. Further, a case of employing an n-type semiconductorsubstrate is similar. In this case, chargesto serve as information are space charges which consist of electrons in an accumulation layer or donors in a depleted state.

There will now be described a practicable method of manufacturingthefirstembodimentofthe present invention.

First, in orderto construct a DRAM, a p--type semiconductor substrate 1 made of single crystal silicon (Si) is prepared. As shown in Figs. 4A and 4B, the semiconductor substrate 1 is partly covered with a thickfield oxide film (SiO2film) 2 for electrically isolating predetermined memorycellswhich adjoin each other or semiconductor elements (not shown) which constitute a peripheral circuit, for example, an addressing circuit, a reading circuit or a writing circuit.

The field oxide film 2 may be formed by the well-known technique in which the silicon substrate is thermally oxidized locally by employing a silicon nitride film as a mask. A p±type region as a channel stopper may well be arranged underthefield oxide film 2.

Afterthe steps illustrated in Figs. 4A and 4B, an insulatorfilm 3 is formed on the whole surface in order to construct a storage capacitor. Used as the insulator film 3 is a silicon nitride (Si3N4) film which is formed by CVD, the relative dielectric constant of which is as high as 7-8 and which hasathicknessof,e.g. ^roximate- ly 150 [ A ] . In orderto relieve the stress be tvveen the silicon nitride film and the semiconductor substrate 1, a first silicon dioxide (SiO2) film having a thickness of, e.g., approximately 80 [ A ] is arranged underthe silicon nitride film. In orderto eliminate the pinholes of the silicon nitride film, a second silicon dioxide film havingathicknessof,e.g.,approximately30 [ A ] is arranged overthe silicon nitride film.The first and second SiO2films may be formed by thermally oxidizing the surfaces of the semiconductor substrate and the silicon nitride film, respectively. Thereafter, as illustrated in Figs. 5A and 5B, a p±type semiconductor region 4to serve as the second conductive plates of storage capacitors is locally formed in the vicinity of the surface of the semiconductor substrate 1 in an area forforming the storage capacitors of memory cells, in particular, unitarily with the storage capacitors adjacent in the row direction.As explained with reference to Figs. 3A and 3B, the semiconductor region 4 is formed in the storage capacitorforming areaforthe purpose of producing a larger quantity of charges of holes or in a depletion layer, to be stored in the storage capacitor and to become a larger quantity of information, orforthe purpose of attaining a threshold voltage (Vth) higherthan an operating voltage which is applied to afirstconductive plate to be described later. Byway of example, boron ions on the order of 5 x 1013 [atoms/cm2] are introduced as impurities by the ion implantation at an energy level of about 30 [keV]. In orderto utilize the principle stated in conjunction with Fig. 3A, the introduced impurities may be subjected to the drive-in diffusion.The depth of the semiconductor region 4 in that case is rendered 0.3 [ pm ] or so. On the other hand, in the case of utilizing the principle stated in conjunction with Fig. 3B,the drive-in diffusion is not carried out. In this case, it is desirable to still lowerthe ion implantation energy orto introduce the impurities into a very shallow position ofthe substrate through another insulatorfilm. This measure is intended to cause the ion-implanted impurities to apparently function as surface charges.

Fig. so shows a part of memory cell arrays which are formed with the p±type semiconductor regions 4. The field oxide film 2 is provided for electrical isolation between the memory cells adjoining each other in the column direction, namely, in the direction in which a word line is to extend (vertical direction in the figure).

Thefieldoxidefilm 2is not arranged betweenthe memory cells adjoining each other in the row direction, namely, in the direction in which a bit line isto extend (lateral direction in thefigure). In one memory cell array, the field oxide film 2 is arranged in the shape of a belt meandering from one end parttothe other end partthereof. The semiconductor region 4 is arranged as a region which is common to thetwo capacitors adjoining each other in the row direction. A region 20 is a region which is provided so asto surround the memory cell arrays and which serves as a guard ring. The region 20 has n-type impurities introduced thereinto later simultaneously with the formation of MISFETs Q,to be turned into an n'-type region.A section along a cutting-plane line B-B in the figure is shown in Fig. SB. The insulatorfilm 3 is omitted.

Afterthe steps illustrated in Figs. 5A and 5B, in the electrical connection part between the first conductive plate to be formed by a later step and one semiconductor region to constitute the MISFET, the insulatorfilm 3 is locally removed to form a contact hole 5. The contact hole 5 is provided in a mannerto be spaced from the semiconductor region 4. Thereafter, a polycrystalline silicon film to become the first conductive plates is formed on the whole surface by the CVD.

The polycrystalline silicon film may have a thickness of approximately 1500-3000 [ A ] by way of example. In orderto render the polycrystalline silicon film low in resistivity, the processing of diffusing phosphorus is performed, or arsenic (As) ions at a dose of approximately 5 x 1014 [atoms/cm2] are ion-implanted at an energy level ofapproximately30 [ keV ] ,whereupona heat treatment is executed. By this treatment, the impurities are diffused into the surface part of the semiconductorsubstrate 1 corresponding to the contact hole 5, to form the n'-type semiconductor region 6 constituting the MISFETwhich is formed by the later step.The depth of the semiconductor region 6 becomes approximately 0.2 [ lim ] . Thereafter, the polycrystalline silicon film is locally patterned, to form the first conductive plate 7 which is electrically connected with the semiconductor region 6 as shown in Figs. 6A and 6B. Thus, the storage capacitor C ofthe memory cell is formed.

After the steps illustrated in Figs. 6A and 6B, using principally the silicon nitride film ofthe exposed insulatorfilm 3 as a maskagainsta heattreatment,an insulatorfilm (SiO2film) 8 which covers the first conductive plate 7 is formed bythethermal oxidation.

This SiO2film 8 may have its thickness rendered, for example, approximately 2000-3000 [ ] so that the first conductive plate 7 and the word line to be formed by a later step can be electrically isolated. Thereafter, the exposed insulator film 3 is locally removed,whereupon as illustrated in Figs. 7A and 7B, an insulatorfilm (SiO2film) 9 serving principallyto construct a gate insulatorfilmisformedintheremoved part of the insulatorfilm 3 bythethermal oxidation ofthe exposed surface ofthe semiconductor substrate 1.

This insulatorfilm 9 has a thickness of, for example, approximately 200 [ A ] .

Afterthe steps illustrated in Figs. 7A and 7B, a polycrystalline silicon film is formed on the whole surface in orderto form the gate electrodes ofthe MISFETs, the word lines, and the semiconductor elements of peripheral circuits. This polycrystalline silicon film is subjected to the same treatment as in the foregoing, to have its resistivity lowernd Thereafter, the polycrystalline silicon film is locally patterned, to form the gate electrode 10, the word line (WL) 11 and the gate electrode (not shown) of the MISFET of the peripheral circuit. The gate electrode 10 is electrically connected witilthe gate electrode 10 ofthe otherof the memory cells adjacent in the column direction, and it constructs the word line 11 extending in the column direction.As the gate electrode 10 or the word line (WL) 11, it is also allowed to use, for example, a layers a refractory metal such as molybdenum (Mo), tungsten (W) or titanium (Ti); a layer of any silicide which is the compound ofthe refractory metal and silicon; or a double-layer structure which consists of a polycrystalline silicon layer and a refractory metal layer or a refractory metal silicide layer overlying the former.Thereafter, in the MlSFETforming area, using the gate electrode 10 as a mask against impurity introduction, impuritiesofthe n±type are introduced in self-alignment fash ion in orderto form the source region and drain region of the MISFET in the vicinities ofthe surface ofthe semiconductorsubstrate 1 through the insu latorfil m s intervening between them and the gate electrode. The introduced impurities are subjected to the drive-in diffusion,wherebythe n ±type semiconductor regfon#12to serve as the source region and the drain region are formed as shown in Figs. 8A and 88.The semiconductor region 6 is electrically connectedwith one-ofthesemiconduc- tor regions 12. Thus, the switching-transistor (MISFET) Q of the memory cell is formed. In addition, arsenic ion impurities may be used as the n ±type impurities and may be introduced by the implantation permitting them to permeatethrough the insulatorfilm 9. The depth of the n±type region is as small as 0.2 um.

After the steps illustrated in Figs. 8A and 83, an insulatorfilm 13 is formed on the whole surface forthe purpose of electrically isolating the gate electrode 10 as well as the word line (WL) 11 and the bit line be formed by a later step. As this insulatorfilm 13, a phosphosilicate glass (PSG) film may be used which relieves the undulations of the surface and which can trap sodium (Na) ions affecting the electrical performance of the DRAM. Subsequently, in orderto connect the other semiconductor region 12 and the bit line to be formed by the later step, the insulatorfilms 9 and 13 on this semiconductor region 12 are locally removed to form a contact hole 14.The bit line (BL) isformed which is electrically connected with thesemiconductor region 12through the contact hole 14 and which extends in the row direction. This bitline(BL) 15 may be formed of, e.g. aluminium (Al).Theresulting state is illustrated in Figures 2A and 2B. Thereafter, a PSG film and a silicon nitride filirr bythe plasma CVD are formed as a final passivati' :film.

The operation of the firs#tembodiment ofthe DRAM memory cell will now be.descii#bedwith reference to Figures 2A and 2B.

First, the case of writing inbnlnation into the memory cell will be:explained#Avoltage is selectively applied to the gatzelectrode 10 constituting the MISFET Q of the memory cell, to turn "on" this MISFET Q.A voltage to serve as the information is applied to thebit line (Be) 15 which is electrically connected with the semiconductor region 12 through the contacthole 1 4. Thus. the voltage of the bit line (BL) 15 corresponding to the information is applied to the firstconductive plate 7 through the MISFET Q. The semiconductor region 4 serving as the second con ductive plate is electrically connected with the semi conductor substrate 1, and is heldatthefixed potential Vss as predetermined. If there is a potential difference between the potential of the second conductive plate and the voltage as the information appliedtothefirst conductive plate 7, charges to serve as information are stored in the insu latorfilm 3 wh ich is the intervening portion between the conductive plates, that is, they are written into the storage capacitor C of the memory cell in the normal way.

In the case of holding the information in the memory cell, the MISFET Q may beturned "off" in the state in which the information has been written into the storage capacitor C ofthe memory cell.

Besides, in the case of reading out the information from the memory cell, an operation reverse to the writing operation may be performed.

According to the present embodiment, in a DRAM wherein a series circuit consisting of a storage capacitor and a MISFET is employed as a memory cell, a first conductive plate which constitutes the storage capacitor is formed on a semiconductor substrate and is arranged so as to be electrically connected with one semiconductor region ofthe MISFET, and a semiconductor region which has an impurity concentration higherthan that of the semiconductor substrate is arranged as a second conductive plate which consti tutesthe storage capacitorth rough an insulator film, whereby charges serving as information can be stored in the storage capacitor by holes.Thus, electrons stored in an inversion layer need not be used as the charges serving as the information, so that the influence of unnecessary minority carriers attributed toa-particlesortheinjectionthereoffroma peripheral circuit portion can be prevented.

Moreover, since the storage capacitor need nottake into consideration the degree of influence bythe unnecessary minority carriers attributed to the aparticles or the injection from the peripheral circuit portion, the occupying area thereof can be reduced.

This makes it possible to integrate the DRAM at a higher packing density.

Further, the storage capacitor can be electrically isolated fromanotherstorage capacitor adjoining it in a a row direction, bythesemiconductor region being the second conductive plate, so that a field oxide film of large occupying area becomes unnecessary to realize the integration of the DRAM at a higher packing density.

Asecond embodiment ofthe present invention will bedescribedwith reference to Figure 9Ato Figure 128.

lnallthefiguresofthe present embodiment, parts having the same functions as in the first embodiment are assigned the same symbols, and they shall not be repeatedly explained.

In Fiugres 9A and 9B, the DRAM memory cell includes an insulatorfilm 18 which is formed so as to cover at least a first conductive plate 7 and which serves to construct a storage capacitor. The insulator film 1 8forms the capacitor along with the first conductive plate 7 and a third electrode to be described later (hereinaftertermed the "third conductive plate"), and is provided to store charges serving as information. The insulatorfilm 18 is also provided to electrically isolate the first conductive plates 7 of adjacent memory cells. The third conductive plate 16 is located on the insulator film 18 outside an area for forming a MISFET Q, and which serves to construct the storage capacitor.A fixed potential, for example, the same potential as that of a substrate 1 is applied to the third conductive plate 16. The third conductive plate 16 is provided as an electrode common to the whole of one memory cell array in which a plurality of memory cells are arranged in the shape of a matrix.

The third conductive plate 16 iswindowed in a part for arranging the MISFET Q. The storage capacitor ofthe memory cell is principally constructed of a parallel circuit connection consisting of a capacitance C which is composed ofthe first conductive plate 7, a semiconductor region 4 being a second conductive plate and an insulatorfilm 3, and a capacitance C1 which is composed of the first conductive plate 7, the third conductive plate 16 and the insulatorfilm 18. An insulatorfilm 19 is arranged so as to coverthethird conductive plate 16, and which serves to electrically isolate the third conductive plate 16 and a word line (WL) 11. Semiconductor regions 4 and 6 are spaced from each other.

When practicable memory cell arrays are constructed by the use of such memory cells shown in Figures 9A and 9B, they become as illustrated in Figure 10. In order to clarify the drawing, insulator films to be arranged between respective conductive layers, contact holes 5 semiconductor regions 4 are omitted from the illustration. The shapes and positional relations of the contact holes 5, the semiconductor regions 4 and other regions will be apparent from Figure 9A.

Excepting the third conductive plate 16, the second embodiment is exactly the same as in the first embodiment.

A practicable method of manufacturing the second embodiment is shown in Figures 11A, 11 B, 1 2A and 12B.

Afterthe steps ofthe first embodiment illustrated in Figures 6A and 6B, an insulatorfilm 18 is formed on the whole surface in orderto construct a storage capacitor. Likewise to the foregoing insulatorfilm 3, this insulatorfilm 18 may be constructed of a silicon dioxide film a silicon nitride film and another silicon dioxide film. Thereafter, a polycrystalline silicon film to become a third conductive plate is formed on the whole surface by the CVD. The polycrystalline silicon film may have a thickness of, for example, approx imately3000 [ A ] . In orderto renderthis polycrystalline silicon film low in resistivity, phosphorus or arsenic is introduced by the same method as in the foregoing.

Subsequently, the polycrystalline silicon film is locally patterned, to form the third conductive plate 16 common to a plurality of memory cells outside a MlSFETforming area as shown in Figs. 1 1Aand 11B.

Thus, the storage capacitor C1 ofthe memory cell is formed.

Afterthe steps illustrated in Figs. 1 1A and 11 B, using principallythe silicon nitride film ofthe exposed insulatorfilm 18 as a mask against a heattreatment, the polycrystalline silicon layer being the third conductive plate is thermally oxidized, therebyto form an insulatorfilm (SiO2film) 19which coversthethird conductive plate 16. Thereafter,the exposed insulator film 18 andthe underlying insulatorfilm 3are locally removed. As in the first embodiment, a gate insulator film 9 is formed in the removed area as shown in Figs.

1 2A and 1 2B. Further, a gate electrode 10, a word line (WL) 11 and semiconductor regions 12 are formed.

After the steps illustrated in Figs. 1 2A and 12B, an insulatorfilm 13, a contact hole 14 and a bit line (BL) 15 are formed as in the first embodiment. Then, the resultant structure becomes as shown in Figs. 9A and 98. Thereafter, a PSG film and a silicon nitride film by the plasma CVD are formed as a final passivation film.

The operation of the second embodiment will be explained with referenceto Figures9Aand 9B.

First, the case of writing information into the memory cell will be explained. A voltage is selectively applied to the gate electrode 10 constituting the MISFET Q ofthe memory cell, to turn "on" this MISFETQ. Avoltage corresponding to the information is applied to the bit line (BL) 15 which is electrically connected with the semiconductor region 12through the contact hole 14. Thus, the voltage ofthe bit line (BL) 15 to serve asthe information is applied to the first conductive plate 7 through the MISFET Q. The semiconductor region 4serving as the second conductive plate is electrically connected with the semiconductor substrate 1, and is held at the fixed potential Vss as predetermined. Also the third conductive plate 16 is held atthefixed potential Vss byway of example.

If there is a potential difference between the potentials of the second conductive plate and the third conductive plate 16 equal to each other and the voltage as the information applied to the first conductive plate 7, charges to serve as information are stored in the insulatorfilm 3 and the insulatorfilm 18 which are the intervening portions between the conductive plates, that is, they are written into the storage capacitor C and C1 ofthe memory cell in the normal way.

In the case of holding the information in the memory cell, the MISFET Q may be turned "off" in the state in which the information has been written into the storagecapacitorCand C1 ofthe memory cell.

Besides, in the case of reading out the information ofthe memory cell, an operation reverse to the writing operation may be performed.

According to the present embodiment, effects similartothoseofthefirstembodimentareachieved.

Furthermore, by arranging a third conductive plate on afirstconductive plate through an insulatorfilm, the quantity of charges to be stored bythefirst conductive plate and the second conductive plate and the quantity of charges bythefirstconductive plate and the third conductive plate can be stored in a storage capacitor. Thus, when the second embodiment is compared with the first embodiment, the quantity of charge storage of the storage capacitor per unit area can be increased to approximately double, and the integ ration of the DRAM at a higher packing density can be realised.

Itshould be noted that, when the potential of a substrate or a p±type semiconductor region 4 is a substrate bias potential VBB = -3.0 V and the potential of a polycrystalline silicon layer 16 is at earth potential Vss = O V, the quantityofcharge storage becomes about 1 .5timesthat inthe absence ofthe polycrystalline silicon layer 16.

In addition, by arranging the third conductive plate 16 of fixed potential on the first conductive plate, a word line WLto which a control voltage of fluctuating magnitude is applied can be prevented from affecting the first conductive plate 7, so that the quantity of charges to be stored in the storage capacitor can be stabilized. Thus, the writing and reading operations of the DRAM can be stabilized, and the reliability of the DRAM can be enhanced.

Athird embodiment is an example wherein, in the second embodiment, the thick field oxide film 2 which isolates the memory cells is not formed at all. The plane and sectional shapes ofthethird embodiment become identical to those of Figs. 9A and 9B and Fig.

10 from which thefield oxide film 2 has been omitted.

Forthis reason, the plane and sectional shapes of the DRAM of the third embodiment shall not be explained, and a practicable method of manufacturing the embodiment will be described, along with the brief description of the structure thereof, with reference to Figures 13,14and 15. Inthesefigures, parts having the same functions as in thefirstand second embodiments are assigned the same symbols, so thatthey are not repeatedly described.

First, excepting a memory cell array portion, a semiconductor substrate 1 is partly covered with a field oxide film in order to electrically isolate the semiconductor elements (not shown) of a peripheral circuit. As in the first and second embodiments, an insulator film 3 is formed on the whole surface.

Thereafter, a mask 17 for impurity introduction made of, e.g. a silicon nitride film is formed selectively on the insulatorfilm 3 in an area in which the MISFET of a switching transistor is to be formed by a later step. An area outside the memory cell array, namely, an area to form the peripheral circuit therein is covered with the mask 17. Subsequently, using the mask 17, p-type impurities are introduced intothe partofthesemiconductor substrate 1 other than the mask 17, to form a p±type semiconductor region 4which becomes the second conductive plate of a storage capacitor and which serves to electrically isolate memory cells adjacent in row and column directions, as illustrated in Fig. 13.That is, the p±type semiconductor region 4 is formed on the whole surface ofthe memory cell array exceptforthe area in which the MISFETs are to be provided.

Afterthe steps illustrated in Fig. 13, the mask 17 is removed, whereupon in the electrical connection part between afirstconductive plateto be formed bya later step and one semiconductor region to constitute the MISFET, the insulator film Sis locally removed to form a contact hole 5.The The,contactholeS and the semicon- ductor region 4 a re spaced. Thereafter, a polycrystal; line silicon film to becomethe first conductive plate-is formed on the wholesurface, and it is implanted with As ions to lower itsresistivity and simultaneouslyto locally form an n ±tWe semiconductor region 6.

Subsequently,thepolycrystalline silicon film ix locally patterned to form thefirst conductive plate7 as shown in Fig. 14.

Afterthe steps illustrated in Fig. 14, as in the second embodiment, an insulatorfilm 18 and a third conductive plate 16 are formed thereby to construct a storage capacitorC1.Afterforming insulatorfilms 19 and 9, a gate electrode 10 and a word line (WL) 11 are formed.

By forming semiconductor regions 12, the MISFET Q is constructed. Afterforming an insulatorfilm 13 and a contact hole 14, a bit line (BL) 15 is formed as shown in Fig. 15. In Fig. 15, insulatorfilmsto be provided between respective conductive layers are omitted in orderto simplify the drawing.

As in the first embodiment, the MISFETs Q may well be formed to finish up the DRAM, without forming the storage capacitors C1.

The DRAM of the third embodiment is finished up by these series of manufacturing steps. Thereafter, a final passivation film is formed as in the first or second embodiment.

According to the present embodiment, effects similarto those ofthe second embodiment are achieved.

Furthermore, the memory cell of the DRAM can be electrically isolated from other memory cells adjoining it in row and column directions, by a semiconductor region being a second conductive plate which constitutes a storage capacitor. Accordingly, a field oxide film in a memory cell array becomes unnecessary, and the integration of the DRAM at a higher packing density can be realized.

Afourth embodiment will be described with reference to Figs. 16Ato 23B. Thefourth embodiment is an example wherein a trench (groove) is added to the first embodiment in orderto increase the quantity of charges which can be stored in a capacitor.Through- out the drawings ofthefourth embodiment, parts having the same functions as in the first embodiment are assigned the same symbols, and they are not repeatedly explained.

In Figs. 16Aand 168, the DRAM memory cell includes a field oxide film 2. Memory cells are shaped by the field oxide films 2 so that the pattern of one pair ofthe memory cells may be repeated in a row direction as shown in Fig. 19. Within a memory cell array, the field oxide film 2 is located principally between the memory cells adjacent in a column direction. This is the same as in thefirstorsecond embodiment.

Trench21 (groove) is provided in a semiconductor substrate 7 in an area forforming a storage capacitor therein, and which serves to construct the storage capacitor. Thistrench 21 increases the quantity of charges as information per unit area in the storage capacitor.

A A p±tvpesemiconductor region 4serving as a second conductive plate is arranged in the main surfaceofthesemiconductorsubstrate 1 in the storage capacitorforming area and the surface of the substrate 1 within the trench 21, and is provided unitarilywith the storage capacitors adjacent in the row direction. The situation of such p±type semicon ductorregions4isshown in Fig. 19.

Now, a method of manufacturing the fourth embodiment will be described.

First, a field oxide film (Si02 film) 2 and p±type semiconductor regions 4 are formed by the same method as that of the first embodiment illustrated in Figs. 4A, 4B, 5A and 5B.

Afterthe step illustrated in Figs. SAand 5B, an insulatorfilm 22A, an insulatorfilm 22B and an insulatorfilm 22C are formed on the whole surface of a semiconductor substrate 1 in ordertoform atrench and a second conductive plate. The insulatorfilm 22C is a mask against etching forforming the trench, and a silicon dioxide (SiO2)film may be employed by way of example. The insulatorfilm 22B is a mask against impurity introduction forforming the second conduc- tive plate, and a silicon nitride (Si3N4) film may be employed by way of example.The insulatorfilm 22A serves to relievethe stress between the semiconductor substrate 1 and the silicon nitride film 22B, and a silicon dioxide film may be employed byway of example. The insulatorfilm 22A may be formed by the thermal oxidation ofthesurfaceofthesubstrate 1.The insulatorfilms 22B and 22C may be formed by the CVD.The insulatorfilm 22C in a storage capacitor forming area is locally patterned, to form a first mask for forming the trench. Anisotropic dry etching is performed using the first mask, wherebythe insulator films 22B and 22c are Iccally removed to form a second mask out of the insulatorfilm 22B, and further, a predetermined part of the semiconductor substrate 1 is locally removed to form the trench 21 as shown in Figs. 17A and 17B. Thewidthwise dimension W ofthe trench 21 may be approximately 1-1.5 [ pmj,andthe depth thereof from the surface of the semiconductor substrate 1 may be approximately 2-4 [ pm ] .

After the steps illustrated in Figs. 17Aand 178, the insulator film 22C having served as the first mask is removed, and the insulatorfilm 228 to serve as the second mask is exposed. Using this second mask, impurities are introduced into the vicinity of the surface of the semiconductor substrate 1 exposed inside the trench 21, whereby a p±type semiconductor region 4to become the second conductive plate is formed as shown in Figs. 18A and 18B. Byway of exa mple, the semiconductor region 4 is formed in such a way that boron (B) ions at a concentration of approximately 1 x 1018 [ atoms/cm3 ] or above are introduced by thermal diffusion at approximately 900-1000 [ 0C ] . In this case, the depth of the semiconductor region 4taken from the surface ofthe semiconductor substrate 1 inwardlythereof is made approximately 0.3 [ Clm ] .

The state of memory cell arraysaftertheformation ofthesemiconductorregions4isshown in Fig. 19. The insulatorfilms 22A and 22B are omitted in Fig. 19. A section along a cutting-plane line B-B in Fig. 19 is shown in Fig. 18B.

After removing the insulator films 22B and 22A,the same insulatorfilm 3 as in the first embodimentfor forming the storage capacitor is formed as shown in Figs. 20A and 20B.

After the step illustrated in Figs. 20A and 20boa contact hole 5, an n±type semiconductor region 6 and a first conductive plate 7 are formed as shown in Figs.

21A and 21 by the same method as that illustrated in Figs. 6A and 68. The trench 21 may well be buried with polycrystalline silicon forthe first conductive plate 7 so as to flatten the su rface thereof.

Afterthe steps illustrated in Figs. 21A and 21 B, using principally the silicon nitride film ofthe exposed insulatorfilm 3 as a mask against a heattreatment, an insulatorfilm (SiO2film) 8which covers the first conductive plate7 is formed bythethermal oxidation.

The insulator film 8 may have its thickness made, e.g., approximately 2000-3000 [ l so that the first conductive plate 7 and a word line to be formed by a later step can be electrically isolated. Thus, in the case where the portion ofthetrench 21 is not buried, the interiorofthe groove needs to be buried by the use of a burying material,for example, a polycrystalline silicon film or an insulatorfilm. The polycrystalline silicon needs to be turned into an insulator by oxidation. Thereafter, the exposed insulatorfilm 3 is locally removed, wherebythesame insulatorfilm 9 as in the first embodiment is formed as shown in Figs. 22A and 22B.

Afterthe steps illustrated in Figs. 22Aand 22B, a MISFETQ and a word line WL are formed as shown in Figs. 23A and 23B. These are the same as those of the firstembodimentshownin Figs. 8A a nd 8B.

Thereafter, an insulatorfilm 13, a bit line BL, etc. are formed as in the firstembodiment. Then,the resultant structure becomes as shown in Figs. and 16B.

Thereafter, a PSG film and a silicon nitride film by the CVD are formed as a final passivation film.

Operations in the cases of writing information into the memory cell ofthefourth embodiment, holding the information and reading outthe information are the same as in the first embodiment.

According to the fourth embodiment, the same effects as in the first embodiment are achieved.

In addition,the variation of the quantity of charge storage ascribable to minority carriers and the coupling of the depletion layer of one trench with that of anothertrench in the deep parts ofthe trenches 21 can be prevented. Accordi ng ly, the trenches 21 can be formed deep. The distance between adjacenttren ches, namely, the distance D1 indicated in Fig. 17A car also be shortened.

Furthermore, since all regions forforming capacitors are p±type semiconductor regions, the distance D2 between atrench and afield oxide film as indicated in Fig. can be shortened.

A A fifth embodiment will be described with reference to Figs. 24A, 24B and 25. Since the manufacturing method thereof is substantially similarto that ofthe fourth embodiment, it shall not be explained. Thefifth embodiment is an example wherein the first conduc- tive plate ofthe fourth embodiment is further overlaid with a third conductive plate to which a fixed potential is applied, so as to increase the stabilize a capacitance.

In the drawings of the fifth embodiment, parts having the samefunctions as in thefourth embodiment are assigned the same symbols, and so are not repeatedly explained.

In Figs. 24A and 24B,the DRAM memory cell includes an insulatorfilm 18, similar in construction to the foregoing insulatorfilm 3, which is located so asto cover at least a first conductive plate 7 and which serves to construct a storage capacitor C1. This insulatorfilm 18 stores charges owing to the first conductive plate 7 and a third electrode to be described later (hereinafter, termed "third conductive plate"). It electrically isolates the first conductive plates 7 of adjacent memory cells.The third conductive plate 16 for constructing the storage capacitor, is located on the insulatorfilm 18 outside an area for forming a MISFET Qtherein and which is connected and provided unitarilywith the third conductive plate ofthe other memory cell in an identical memory cell array. Afixed potential, for example, the same potential as that of a substrate is applied to this third conductive plate 16. The storage capacitor of the memory cell is principally constructed of a parallel connection consisting of a capacitance Cwhich is composed ofthe first conductive plate 7, a semiconductor region 4 being a second conductive plate and the insulatorfilm 3, and a capacitance C1 which is composed ofthe first conductive plate 7, the third conductive plate 16 and the insulatorfilm 18.An insulatorfilm 19 is arranged so asto coverthethird conductive plate 16, and servesto electrically isolate the third conductive plate 16 and a word line (WL) 11.

When practicable memory cell arrays are constructed by the use of the memory cells as shown in Figures 24A and 24B, they become as illustrated in Figure 25. In order to simplify the drawing, the insulatorfilmsto be located between respective conductive layers are not illustrated.

Afigure obtained by omitting the third conductive plates 16 in Figure 25 is identical to the planviewofthe fourth embodiment.

The operation of the fifth embodiment is the same as that of the second embodiment.

According to the fifth embodiment, effects similar to those of the second and fourth embodiments are achieved.

Asixth embodiment will be described with reference to Figures 26, 27 and 28. The sixth embodiment is an example wherein, in the fifth embodiment, the field oxide film 2 which electrically isolates the memory cells adjacent in the column direction is omitted, and no field oxide film is provided within the memory cell array.

In the drawings of the sixth embodiment, parts having the same functions as in thethird and fourth embodiments are assigned the same symbols, and so they are not repeatedly explained.

First, excepting a memory cell array portion, a semiconductor substrate 1 is partly covered with a fieldoxidefilm by the local thermal oxidation of the substrate 1 in orderto electrically isolate the semicon ductorelements (notshown) of a peripheral circuit. A trench 21 and the insulatorfilm 3 are formed.

Thereafter, a p±type semiconductor region 4 is formed in the whole area ofthe memorycell array except for an area covered with a mask 17, by the same method as shown in Figure 13.

Afterthe steps illustrated in Figure 26, a contact hole 5, an n±type semiconductor region 6 and a first conductive plate 7 are formed bythe same method as shown in Figure 14. A section of Figure 27 is identical to Figure 21 B in which the field oxide film 2 is replaced with the p±type semiconductor region 4.

After the steps illustrated in Fig. 27, as in the third embodiment, an insulatorfilm 18 and a third conductive plate 16 are formed, thereby to construct a storage capacitor C1. Afterforming insulatorfilms 19 and 9, a gate electrode 10 and a word line (WL) 11 are formed, and semiconductor regions 12 are formed, thereby to form a MISFET O. After forming an insulatorfilm 13 and a contact hole 14, a bit line (BL) 15 is formed as shown in Fig. 28. In Fig. 28, in orderto simplify the drawing, insulatorfilmsto be provided between respective conductive layers are not shown. In addition, a section of Fig. 28 is equal to Fig. 24B in which the field oxide film 2 is replaced with the p±type semiconductor region. Thereafter, the processing of a protective film etc. is performed as in the first embodiment.

In the sixth embodiment, the p±type semiconductor region 4 and the n ±type semiconductor region 6 need to be provided in spaced relation as in the other embodiments The operation ofthe sixth embodiment is the same as that of the second embodiment.

According to the sixth embodiment, effects similar to those of the third and fifth embodiments-are achieved.

In the sixth embodiment, it is needless to say that the formation ofthethird conductive plate 16may well be omitted. This s identical to the relation between the third embodiment and the first embodiment. The plan andsection ofthe memory cells of the DRAM in this case and the sections thereof in the course ofthe manufacturing steps will be apparent from the description ofthethird and fourth embodiments.

The present embodiment brings forth the following effects: A storagecapacitor is constructed of an insulator film which is located on the surface of a semiconductor substrate, a first conductive plate one end part of which is located on the insulatorfilm and the other end part of which is arranged so as to be electrically connected with one semiconductor region of a MISFET, and a semiconductor region to serve as a second conductive plate, which is arranged in a predetermined surface part of the semiconductor substrate. This eliminates the coupling between the depletion layers ofthe adjacent storage capacitors, and the leakageofchargesbetweenthem.

Sincethe leakage ofthe chargesis eliminated, the retention time of charges inthestorage capacitor is enhanced, and the frequency of refreshing operations is lowered. Accordingly, the operating speed of the DRAM is enhanced.

As charges to be stored in a storage capacitor, charges in an accumulation layerora narrowdeple tion layer are used. Accordingly, it becomes unneces- sark to use electrons which are stored in a wide depletion layeroran inversion layer, so that the DRAM is not affected by minority carriers.

Sincethe degree of influence of minority carriers on a storage capacitor need not be considered, the occupying area of the storage capacitor can be reduced. Thus, the integration ofthe DRAM at a higher packing density is realized.

Since charges can be stored between a first conductive plate and a second conductive plate and betweenthefirst conductive plate and a third conductive plate, the quantity of charge storage of a storage capacitor per unit area increases.

A memory cell is electrically isolated from another memory cell adjoining it in a row direction or/and a column direction, by a semiconductor region being a second conductive plate which constitutes a storage capacitor. An isolation region made of an insulator film becomes unnecessary, and the integration ofthe DRAM at a higher packing density is permitted.

The occupying area of a memory cell can be markedly reduced, and the integration ofthe DRAM at a still higher packing density is permitted.

By providing a third conductive plate offixed potential on a first conductive plate, the influence of a word line on the first conductive plate is eliminated, and the quantity of charges to be stored in a storage capacitor is stabilized. The writing and reading operations of the DRAM are also stabilized.

Since a semiconductor region of a first conductivity type constituting the capacitance of a memory cell and a semiconductor region of a second conductivity type connected with the MISFET ofthe memory cell are arranged spaced from each other, the reverse breakdown voltage of a junction is not deteriorated.

In a modified embodiment from those described above, a p-type well region is formed in an n-type semiconductor substrate and the memory cells of a DRAM are formed within the well region. In addition, it is possible to employ an n-type semiconductor substrate and to use an n-type semiconductor region as a second conductive plate so as to store charges for information. Furthermore, itis possibletoform an n-type well region in a p-type semiconductor substrate and to form the memory cells of a DRAM within the well region.

In thefourth to sixth embodiments, an ion implantation process may well be employed as a method of forming a semiconductor region which is a second conductive plate. In this case, the ion implantation is performed in the state shown in Figure 18B. The implanted impurity element, for example, boron is introduced into the bottom of a trench 21. The boron is diffused by subsequent annealing, to form a semiconductor region in the bottom ofthe trench 21 and to rise along the side wall of the trench toward the surface of a substrate. Therefore, the semiconductor region is formed also in a part ofthe side wall of trench. The semiconductorregionextending along the sidewall does not reach the vicinity of the substrate surface (a region where a semiconductor region 6 of the opposite conductivity type is formed). With this measure, the capacitance of a memory cell decreases to some extent, but a mask registration margin for spacedly arranging the semiconductor regions 4 and 6 of the conductivity types opposite to each other can be dispensed with.

Claims (19)

1. A semiconductor memory device having memory cell arrays in which memory cells are arranged in the shape of a matrix, said each memory cell comprising a switching element and a capacitor which is formed on a main surface of a semiconductor substrate of a first conductivity type and which is connected with said switching element, wherein::~ (a) said capacitor comprises a first insulatorfilm which is formed on the main surface of said semiconductorsubstrate, a first electrode a part of which is electrically connected with said switching element and which is formed on said first insulatorfilm, said first electrode being independentforsaid each memory cell, and a first semiconductor region to serve as a second electrode, which is formed in said semicon ductor substrate under said first insulatorfilm and which has the first conductivitytype and an impurity concentration higherthan that of said semiconductor substrate; and (b) the first semiconductor region of one memory cell is connected with the first semiconductor region of at least one ofthe memory cells which adjoin said one memory cell within the identical memory cell array by a second semiconductor region which is formed in said semiconductor substrate and which hasthefirstconductivitytypeand an impurity concentration higherthan that of said semiconductor substrate.

2. A semiconductor memory device according to Claim 1, wherein said capacitor is formed by the use of a trench, said trench isformed by removing said semiconductorsubstratefrom sem icon uctor su state fro m said main su surface thereof inwardly, and said first semiconductor region is formed in said main surface of said semiconductor substrate and a surface of said trench.

3. A semiconductor memory device according to Claim 1, wherein the first semiconductor region of one memory cell is connected with the first semiconductor region of another memory cell which adjoins said one memory cell within the identical memory cell array and which is connected to a bit line identical to that of said one memory cell and also to a word line adjacent to that of said one memory cell.

4. A semiconductor memory device according to Claim 1, wherein said capacitor includes a first capacitor and a second capacitor which is formed on said first capacitor, said first capacitor comprising the first insulatorfilm which is formed on the main surface of said semiconductor substrate, the first electrode a part of which is electrically connected with said switching element and which is formed on said first insulatorfilm, said first electrode being independent for said each memory cell, and thefirst semiconductor region to serve as the second electrode, which is formed in said semiconductor substrate under said first insulatorfilm and which has the first conductivity type and the impurity concentration higherthan that of said semiconductor substrate, said second capacitor comprising the first electrode, a second insulator film which is formed on at least said first electrode, and a third electrode which is formed on at least said second insulator film.

5. A semiconductor memory device according to Claim 4,wherein said third electrode is an electrode common to all the memory cells of the identical memory cell array, and it is formed unitarilywithin one memory cell array.

6. A semiconductor memory device according to Claim 5, wherein said second insulatorfilm is formed underthe whole third electrode.

7. Asemiconductormemory device according to Claim 5, wherein said third electrode is connected to earth potential of said semiconductor memory device.

8. A semiconductor memory device according to Claim 4, wherein said capacitor is formed by the use of a trench, said trench is formed by removing said semiconductorsubstratefrom said main surface thereof inwardly, and said first semiconductor region is formed in said main surface of said semiconductor substrate and a surface of said trench.

9. A semiconductor memory device according to Claim 4, wherein the first semiconductor region of one memory cell is connected with thefirstsemiconductor region of anobier memory cell which adjoins said one memory cell within the identical memory cell array and which is connected to a bit line identical to that of said one memory cell and also to a word line adjacent to that of said one memory cell.

10. A semiconductor memory device according to Claim 1, wherein all of said first semiconductor regions within the same memory cell array are connected to each other by said second semiconductor region.

11. A semiconductor memory device according to Claim 10, wherein said capacitor is formed by the use of a trench, said trench is formed by removing said semiconductor substrate from said main surface thereof inwardly, and said first semiconductor region is formed in said main surface of said semiconductor substrate and a surface of said trench.

12. A semiconductor memory device according to Claim 10, wherein said capacitor includes a first capacitor and a second capacitor which is formed on said first capacitor, said first capacitor comprising the first insulatorfilm which is formed on the main surface of said semiconductor substrate, the first electrode a part of which is electrically connected with said switching element and which is formed on said first insulatorfilm, said first electrode being independent for said each memory cell, and the first semiconductor region to serve as the second electrode, which is formed in said semiconductor substrate under said first insulatorfilm and which has the first conductivity type and the impurity concentration higherthan that of said semiconductor substrate, said second capacitor comprising thefirst electrode, a second insulator film which is formed on at least said first electrode, and a third electrode which is formed on at least said second insulator film.

13. A semiconductor memory device according to Claim 12,wherein said third electrode is an electrode common to all the memory cells ofthe identical memory cell array, and it is formed unitarily within one memory cell array.

14. A semiconductor memory device according to Claim 12, wherein said second insulatorfilm is formed underthewhole third electrode.

15. A semiconductor memory device according to Claim 13, wherein said third electrode is connected to earth potential of said semiconductor memory device.

16. A semiconductor memory device according to Claim 12, wherein said capacitor is formed by the use of a trench, said trench is formed by removing said semiconductorsubstratefrom said main surface thereof inwardly, and said first semiconductor region is formed in said main surface of said semiconductor substrate and a surface of said trench.

17. A semiconductor memory device having memory cell arrays in which memory cells are arranged in the shape of a matrix, said each memory cell comprising a switching element and a capacitor which is formed on a main surface of a semiconductor substrate of a first conductivity type and which is connected with said switching element, wherein::~ (a) said capacitor comprises a first insulator film which is formed on the main surface of said semiconductor substrate, a first electrode a part of which is electrically connected with said switching element and which is formed on said first insulatorfilm, said first electrode being independentforsaid each mem ory cell, and a first semiconductor region to serve as a second electrode, which is formed in said semicon ductor substrate under said first insulator film and which hasthefirst conductivity type and an impurity concentration higherthan that of said semiconductor substrate; and (b) said capacitor changes a quantity of space charges of at least a depletion layer arising within said second semiconductor region, into first and second statuses in accordance with first and second potentials which are applied to said first electrode.

18. A semiconductor memory device according to claim 17, wherein said capacitorchangesthe quantity ofthe space charges ofthe depletion layer arising in said second semiconductor region and a quantity of charges of an accumulation layer within said second semiconductor region, into first and second statuses in accordance with the first and second potentials which are applied to said first electrode.

19. A semiconductor memory device constructed and arranged to operate substantially as herein described with reference to and as illustrated in the accompanying drawings.