FR2554954A1 - SEMICONDUCTOR MEMORY DEVICE - Google Patents

Abstract

THIS DEVICE INCLUDES MEMORY CELLS EACH INCLUDING A SWITCHING ELEMENTQ AND A CONDENSERC FORMED ON A SEMICONDUCTOR SUBSTRATE1, THE CONDENSERC CONSISTING OF AN INSULATING LAYER3, AN ELECTRODE7 AND A SEMICONDUCTOR AREA FORMING4 ELECTRODE IN THE SUBSTRATE BELOW LAYER3 HAVING THE SAME TYPE OF CONDUCTIVITY AS THE SUBSTRATE AND A HIGHER IMPURITY CONCENTRATION THAN THAT OF THE SUBSTRATE, AND THE REGIONS OF THE CELLS ARE JOINED BY ANOTHER SEMICONDUCTOR REGION OF THE SUBSTRATE CONDUCTING THE TYPE OF CONDUCTOR , AND AN IMPURITY CONCENTRATION GREATER THAN THAT OF THE SAID SUBSTRATE, THE ELEMENTSQ, C BEING CONNECTED TO TRANSMISSION LINES OF BITS15, BL AND TO TRANSMISSION LINES OF MOTS11, WL. APPLICATION IN PARTICULAR TO DYNAMIC MEMORIES WITH DIRECT ACCESS.

Description

The present invention relates to a device

  tif of semiconductor memory, and more particularly a

  technique which is effective when applied to a

  Dynamic Direct Access Memory (DRAM).

  Each cell of a DRAM is constituted by a storage or storage capacitor and

  a switching MISFET transistor. The storage capacitor

  ge is constituted by a capacitor of MIS type. Concretely, it consists of a semiconductor substrate, an insulating film which is formed on the semiconductor substrate and a capacitor electrode which is formed on the insulating film and to which a predetermined voltage is applied. The charges present in an amount corresponding to the information "1" or "0" are stored in an inversion layer, which is formed within the

  semiconductor substrate below the condensate electrode

  to which the predetermined voltage is applied.

  To integrate the DRAM memory into a system

  high integration density, it is effective to give a weak surface to the capacitor, while maintaining its

ability to a certain value.

  A DRAM memory, which satisfies this requirement, is described in the patent application filed in Japan No. 50-53 883. The capacitor of this DRAM memory consists of a trench or a groove (also called "U-shaped groove"). which is formed to extend from a main surface of a semiconductor substrate, inwardly thereof, by an insulating film which is formed along the groove and by a capacitor electrode

  which is formed to cover the insulating film.

  However it is true that charges are stored in a depletion layer and in a layer

  inversion located within the semiconductor substrate.

  According to the studies carried out by the authors of the present invention, the DRAM consisting of memory cells of the type storing charges in a depletion layer and in an inversion layer, does not

  not suitable for high density integration.

  The memory cell of this type does not make it possible to exclude the influence of minority carriers, appearing as a result of the action of particles or carriers.

  minority groups injected from a peripheral circuit element

  phérique, etc. Insofar as the charges are stored in the depletion layer and in the inversion layer,

  o10 the amount of expenses varies because of minority holders

  tary. This is why the area occupied by the storage capacitor can not be made smaller than a certain value. Since the influence of the minority carriers increases more at a deeper location relative to the surface of a semiconductor substrate, increasing the depth of a trench or furrow is not very effective. In addition, with the memory cells of the

  specified type, it is impossible to give small dimen-

  to an insulating region for electrically isolating neighboring memory cells. The reason is that, being

  given that it is necessary to prevent a coupling between the layers of

  poverty and capacitor reversal layers

  neighboring memory cells, the distance between the cells

  lules of memory can not be made lower than a certain value. In the case of the use of a film

  of field oxide as an insulating region, it also arises

  the problem of forming a bird's beak. By -

  elsewhere the depletion layer mates more easily

  to the depletion layer of the neighboring groove in the deep part of this groove as in the low-lying part of this groove. It is for this reason that the distance between the furrows can not be made less than one

certain value.

  An object of the present invention is to provide a DRAM which can be integrated in accordance with

  a higher density of integration. -

  Another object of the present invention is to prevent the leakage of charges between storage capacitors memory cells neighboring a DRAM memory.

  Another object of the present invention

  is to reduce the degree of influence of minority carriers in the storage capacitor of the cell of a DRAM memory. Another object of the present invention is to extend the data retention time allowed by the storage capacitors of a DRAM memory, so as to increase the operating speed of this memory. The objectives mentioned above as well as other objectives and new characteristics of

  the present invention will clearly be apparent from the

  following description and attached drawings.

  We will explain below the main lines

  of a typical aspect of performances obtained thanks to the pre-

this invention.

  A first electrode, which is formed on a semiconductor substrate and which constitutes a capacitor

  storage is electrically connected to a semi-

  conductor of a MISFET transistor, and a semiconductor region

  trice, which has the same type of conductivity as the semiconductor substrate and a higher impurity concentration, is used to

  second electrode to form the storage capacitor.

  This storage capacitor stores charges serving

  information, mainly in an accumulation layer.

  The depletion layer is narrowed or suppressed and a

  inversion layer can not develop. The degree of

  fluence of unnecessary minority carriers, attributed to

  particles "or to an injection from a peripheral

  circuit, is reduced, and memory cells

  are electrically isolated by the semicon-

ductrice.

  More precisely, according to a first

  According to the invention, there is provided a semiconductor memory device characterized in that it comprises memory cell arrays, in which the memory cells are arranged in the form of a matrix and each comprise a memory element. switching and a capacitor that is

  formed on a main surface of a semiconductor substrate

  having a first conductivity type and which is connected to said switching element, said capacitor comprises a first insulating film, which is formed on

  the main surface of said semiconductor substrate, a first

  electrode, part of which is electrically connected to said switching element and which is formed on said first insulating film and is independent for each

  memory cells, and a first semiconductor region

  a second electrode which is formed in said semiconductor substrate below said first insulating film and which has the first conductivity type and an impurity concentration higher than that of said semiconductor substrate, and that the first semiconductor region a memory cell is connected to the first semiconductor region of at least one of the memory cells, which adjoins said memory cell within the same memory cell array through a second memory cell; semiconductor region which is formed in said semiconductor substrate and which has the

  first type of conductivity and a concentration of impure-

  higher than that of said semiconductor substrate.

  According to another aspect of the present invention,

  a semiconductor memory device is provided, characterized in that it comprises memory cell arrays, in which the memory cells are arranged in the form of a matrix and each comprise an element.

  switchgear and a capacitor which is formed on a sur-

  main face of a semiconductor substrate having a

  first type of conductivity and which is connected to this

  switching device, that said capacitor comprises a first

  an insulating film, which is formed on the primary surface

  of said semiconductor substrate, a first electrode, a part of which is electrically connected to said element

  of switching and formed on said first film

  the insulator and is independent for each of the memory cells, and a first semiconductor region for constituting a second electrode which is formed in said

  semiconductor substrate below said first film

  and has the first type of conductivity and an impurity concentration higher than that

  semiconductor substrate, said capacitor bringing a quantity

  space charge of at least one depletion layer.

  appearing within that second region

  semiconductor, in first and second states according to

  first and second potentials that are applied to

said first electrode.

  Other features and benefits of

  the present invention will emerge from the description given

  Hereinafter taken with reference to the accompanying drawings, in which: - Figure lat a diagram of an equivalent circuit illustrating the essential parts of the array of cells of a DRAM memory, for explaining an embodiment of the present invention ;

  FIG. 2A is a plan view of the

  essential parts of a DRAM memory cell from a first

  embodiment of the present invention; Figure 2B is a sectional view taken along line II-II in Figure 2A; FIGS. 3A and 3B are graphs making it possible to explain the principle of the present invention; FIGS. 4A, 5A, 6A, 7A and 8A are plan views of the essential parts of the DRAM memory cell, during the manufacturing phases of this DRAM memory illustrated in FIGS. 2A and 2B; FIGS. 4B, 5B, 6B, 7B and 8B are

  sectional views taken according to plans identified respectively

  4A, 5A, 6A, 7A and 8A;

  FIG. 5C is an illus-

  the operating phase of manufacturing a network of

  memory modules in the DRAM memory of FIGS. 2A and 2B;

  FIG. 9A is a plan view of the

  essential elements of a DRAM memory cell according to a second embodiment of the present invention; Figure 9D is a sectional view taken along the line IX-IX in Figure 9A;

  FIG. 10 is a plan view of the

  essential elements of a schematic cell network of the DRAM memory shown in Figs. 9A and 9B; FIGS. 11A and 12A are plan views of the essential parts of the DRAM memory cell during the manufacturing phases of this memory illustrated in FIGS. 9A and 9B; FIGS. 11B and 12B are views in

  taken in accordance with respective sectional planes

  12A and 12A; FIGS. 13, 14, 15 are plan views of the essential parts of a network of cells of

  memory during the operating phases of manufacturing a

  DRAM according to a third embodiment of the present invention; FIG. 16A is a plan view of

  essential parts of a cell of a DRAM memory in accordance

  to a fourth embodiment of the present invention.

  tion; FIG. 16B is a sectional view taken along the line XVI-XVI in FIG. 16A; FIGS. 17A, 18A, 20A, 21A, 22A and 23A are plan views of the essential parts of the

  memory cell during the different operational phases

  DRAM memory shown in Figures 16A and 16B; FIGS. 17B, 18B, 20B, 21B, 22B and 23B are sectional views taken from the sectional planes respectively indicated in FIGS. 17A, 18A, 20A, 21A, 22A and 23A; Fig. 19 is a plan view showing an intermediate state during the process of manufacturing the DRAM shown in Figs. 16A and 16B; FIG. 24A is a plan view of

  essential parts of a cell of a DRAM memory in accordance

  to a fifth embodiment of the present invention.

  tion; - Figure 24B is a sectional view taken along line XXIV XXIV in Figure 24A;

  FIG. 25 is a plan view of the

  essential elements of a schematic network of a cell of the DRAM memory shown in Figs. 24A and 24B; and FIGS. 26, 27 and 28 are plan views showing the manufacturing phases of a DRAM memory according to a sixth embodiment of FIG.

the present invention.

  The following is a description of the forms of reali-

preferred embodiment of the invention.

  FIG. 1 is a balanced circuit diagram

  are illustrative of the essential parts of the network of

  lules of a DRAM memory, for explaining an embodiment of the present invention. With reference to FIG. 1, it can be seen that the symbols SA1, SA2, .... denote sense amplifiers or read amplifiers, each of which serves to amplify the small potential difference existing between a predetermined memory cell and a

  predetermined hypothetical cell, which will be described later

  is lying. The symbols BL11 and BL12 designate transmission lines

  bit mission, which extend in the direction of the lines from a lateral end of the read amplifier SA1. The symbols BL1 and BL22 denote bit transmission lines which extend in the direction of the lines from a lateral end of the sense amplifier SA2. These bit transmission lines BL serve to transmit charges as information. The symbols WL1 and WL2 denote word transmission lines that extend in the direction of the columns. These lines are connected to predetermined control electrodes which

  constitute the MISFET transistors for switching

  the fictitious ones which will be described later, and serve to place these MISFET transistors in the "conducting" state and in the "blocked" state. The symbols WL and WL4 denote word transmission lines, which extend in the direction of the columns. These lines are connected to predetermined control electrodes which constitute the MISFET transistors for switching memory cells which will be described later, and serve to place these transistors.

  MISFET in the "driver" state and in the "blocked" state. Symbols

  the M11 M12, M21, M22 .... designate the memory cells

  re, which retain the charges serving as information. The memory cell M1, M12, M21, M22, ... is constituted by the MISFET transistor Q1 'Q12' Q21 'Q22' ...

  end is connected to the predetermined line of transmission

  BL bits mission and whose gate electrode or electri-

  command line is connected to the transmission line

  word mission WL, and by a capacitor portion C11, C12, C21, C22, ..., one end of which is connected to the other end of the MISFET transistor Q11 'Q12' Q21 'Q22' and whose other end is placed at a fixed potential VSS

  such as the mass potential (O V) or a polarity potential

  rear substrate (- 2.5 to - 3 V). Symbols

  the D11, D12, D21, D22, ... designate the fictitious cells,

  who maintain the burden of deciding whether to

  git of a "1" or a "0" which constitutes the information of the memory cells M. The dummy cell D11, D12, D21, D22 is constituted by the MISFET transistor QD11 'QD12' QD21 '

  QD22 '..' with one end connected to the predefined line

  terminated bit transmission BL and whose gate electrode is connected to the predetermined word transmission line WL, by a capacitor portion CD11 CD12, CD21, C22, ..., one end of which is connected to the other end of the MISFET transistor QD11 'QD12' QD21 'Q22' ... and whose other end is connected to the terminal of the fixed potential VSS, and by a cancellation transistor MISFET CQ which

  used to erase or annihilate the charges stored in the

  Capacitor forming element CD11, CD12, CD21 'CD22' .... The symbol 0D designates a terminal which is connected to the electrode

  gate of the erase transistor MISFET CQ.

  Hereinafter we will describe the structure that can

  be realized from a first embodiment of the pre-

this invention.

  Figure 2A is a plan view of the

  The essential elements of a DRAM memory cell make it possible to explain the structure of the present invention, while FIG. 2B is a sectional view taken along line II-II in FIG. 2A. On all drawings of this

  embodiment, the elements possessing the same functions

  are designated by identical symbols or references,

  and we will not repeat the explanation.

  In FIGS. 2A and 2B, reference numeral 1 denotes a p-type semiconductor substrate, which serves to

realize a DRAM memory.

  Reference 2 denotes a film of oxy-

  of a field that is formed on the part of the primary surface

  of the semiconductor substrate 1 so as to lie between the predetermined memory cells and between

  semiconductor elements constituting peripheral circuits

  (not shown), for example a selection circuit

  addresses, a read circuit and a recording circuit.

  electrically isolating these elements from each other. The memory cells are surrounded and defined by the field oxide films 2 so that the configuration or structure of a pair of memory cells can be repeated in the direction in which a bit transmission line 15 is to be described later extends (direction hereinafter referred to

  under the term "direction of lines"). Insulating films

  lantes 2 are identified by dashed lines. There is no insulating film 2 between the cells of

  which are close to each other according to the

lines.

  Reference 3 denotes an insulating film

  te which is provided on the part of the main surface of the semiconductor substrate 1 in at least one area provided for the formation of a storage capacitor, and which serves to realize the dielectric of the storage capacitor. Charges, e.g., holes, are stored by the first capacitor electrode (hereinafter referred to as "first conductive plate") and the second capacitor electrode (hereinafter referred to as "second plate"). driver "), which will be described later, with

  interposition of the insulating film 3 between these electrodes.

  Reference 4 designates a semi-

  type b + conductor used as a second

  duct and which is provided on the surface of the semicon-

  1 in the area intended for the formation of condensa-

  storage unit, which is made in one piece with adjacent storage capacitors in the direction of the lines. This region serves to constitute the storage capacitor C and at the same time to electrically isolate the adjacent storage capacitors in the + line direction. The p-type semiconductor region 4 is arranged so that the charges of the holes or the charges of a

  depletion layer to be stored in the conden-

  in which the insulating film 3 is interposed

  between this region 4 and the first conductive plate, can

  to be obtained in as large a quantity as possible, or that a threshold voltage higher than a voltage applied to the first conductive plate remaining at

  describe may be provided near the surface of the subsurface

  semiconductor region 1. The semiconductor region 4 also serves

  removing the extension of the depletion layer formed by applying the voltage to the first conductive plate so as to extend from the portion of the bottom surface of the semiconductor substrate 1 to the inside of this semiconductor substrate. The region

  semiconductor 4 may have a concentration of impure-

  It would be desirable for the p-type semiconductor region to be + located at a distance from an n-type semiconductor region to be described later. This is intended to avoid a

  reducing the breakdown voltage of a junction.

  The reference 5 designates a contact hole, which serves for the electrical connection of the first conductive plate 7, which will be described later, to a semiconductor region 6 or 12 of a MISFET transistor Q. The n + type semiconductor region 6 is. formed in the surface of the semiconductor substrate 1 corresponding to the contact hole 5,

  and serves to electrically connect the first conductive plate

  trice, which will be described later, and a semi-

conductor of the transistor MISFET Q.

  The first conductive plate 7 is

  on the insulating film 3 in the formation area of the storage capacitor, independently for each memory cell, so that a portion of the end of this plate is electrically connected by

  via the contact hole 5 and the semicon-

  6 to a semiconductor region of the MISFET transistor Q to be described later. The first conductive plate 7 serves to build the storage capacitor C. It is indicated by a mixed line formed of lines separated by two points. The storage capacitor C of the

  memory cell is mainly constituted by the first

  first conductive plate 7, by the semiconductor region 4

  which constitutes the second conductive plate, and by the film

insulation 3.

  Reference 8 designates an iso-

  which is formed so as to cover the first

  7 and which serves to electrically isolate the first conductive plate 7 and a transmission line

  of words 11 which will be described later.

  Reference 9 designates an iso-film

  lante which is arranged on the part of the main surface

  of the semiconductor substrate 1 in the zone for forming

  MISFET transistors, and which is mainly used to

  make a film of grid insulation.

  Reference numeral 10 represents a control electrode or gate electrode, which is formed on the predetermined insulating film 3 and which serves to realize the MISFET transistor Q. The word transmission line (WL) 11 is arranged to be electrically connected. to the gate electrodes 10 of the neighboring memory cells in the direction of the columns and to extend in the direction of the columns being made in one piece

  with the gate electrodes 10. This transmission line

  The wording is used to set the MISFET transistors to the "blocked" state (switching operation) to be described later (hereinafter the direction in which the word transmission line 11 extends ,

  will be referred to as column direction).

  References 12 denote the n-type semiconductor regions, which are formed in the surface of the semiconductor substrate 1 on both sides of the gate electrode 10 and serve as source regions and drain regions for constituting the MISFET transistor. Q. The

  switching transistor (MISFET) Q is constituted by the elec-

  gate 10, by the semiconductor regions 12 and by the insulating film 9. One of the semiconductor regions 12 is electrically connected to the semiconductor region 6 and is electrically connected to the first conductive plate

7, as indicated previously.

  Reference 13 designates an iso-film

  which is designed to cover the entire surface and serves to electrically isolate the gate electrode 10 as well as the word transmission line (WL) 11 and a bit transmission line 15 to be electrically isolated. described later. The reference 14 designates a contact hole, which is provided by local elimination of the insulating films 9 and 13 on the other semiconductor region 12 and which serves for the electrical connection of the semiconductor region 12 to the

  bit transmission line to be described hereinafter.

  The bit transmission line (BL) 15 is arranged to be electrically connected to the

  semiconductor region 12 via the lead hole

  tact 14 and extend in the direction of the lines. She

  serves to transmit a voltage serving as information.

  Hereinafter will be described the principle of the memory DRA4 according to the present invention and having the

constitution indicated above.

  Figures 3A and 3B are graphs

  to explain the principle of the present invention.

  In these figures, the abscissa axis represents the value of the voltage Vp (V), which is applied across the two electrodes of the MIS storage capacitor. The ordinate axis represents the concentration of charges QscI / cm 23 per unit area, the charges being maintained on the surface

  of the lower semiconductor region of the p-type by

  sion applied across the electrodes of the capacitor. Sure

  the y-axis, we took a logarithmic scale.

  Since, in FIGS. 3A and 3B, the p-type silicon semiconductor substrate has been taken as an example, the charges to be induced in the surface are negative charges for the voltage present between the terminals of the capacitor for Vp> VFB and positive charges for Vp <VFB. Here, VFB denotes a flat web tension. Negative charges are electrons or impurities of the acceptor type, while positive charges are

holes.

  FIG. 3A illustrates the case where the holes,

  which are loads of space in the depletion layer

  are mainly used as charges that are stored for information purposes. This corresponds to the case + o the p-type semiconductor region represented on

Figures 2A and 2B are included. We will first explain the principle

  of the prior art DRAM with reference to FIG.

re 3A.

  The curves (a), (b) and (c) illustrate the relationship between the voltage V and the charge concentration P QSC in the vicinity of the surface, in the DRAM memory of the prior art. In Fig. H is an accumulation region, in which an accumulation layer is formed, k is

  a region of impoverishment, in which a region of

  poverty is formed and m denotes an inversion region

  wherein an inversion layer is formed. On the

  curves (a), (b) and (c) refer to the numbers of

  the electrons and acceptor impurities (the numbers of the negative charges) n and the number of the holes p in the case where the threshold voltage (Vth) of the vicinity of the surface of the semiconductor substrate in the storage capacitor is brought to about - 0.2 V. The curve (a) indicates the number of

  holes P located in the accumulation region a, which is ex-

  awarded by p. ICox / q (Vp - VFB) I. (1). Curve (c) indicates the number of electrons and acceptor-forming impurities n in the inversion region m, this number being expressed by n Cox / q (Vp-Vth). (2). Here COX denotes the thickness of the insulating film which is the dielectric

  capacitor. Curve (b) indicates the number of impure-

  acceptors appearing in the state (state of ap-

  deep depletion), in which no inversion layer is formed despite the inversion region, this number being approximately expressed by QsC -Vp -VF. When,

  in accordance with the above, concentra-

* QSC surface charges in the essential parts of the

  the curves (a), (b) and (c) are evaluated, the concentration

  surface negative charges for voltage V = Vth il (Pith

  becomes QIF = 1 x 101 L / cm2, and the concentration of

  negative surface ges for voltage V = 0-becomes

Q10 = 2.2 x 1011 [/ cm2].

  In the storage capacitor of the

  DRAM memory cell of the prior art, the charges of

  intended to serve as information were the electrons located

  in the inversion region m. Specifically a tension.

  fixed, for example a voltage of about 5 Vy, is applied.

  between the electrodes of the capacitor so as to bring the

  operating region in the inversion region m. This-

  after the amount of QIL charges in the case of training

  of the inversion layer by externally introduced charges.

  the state of the curve (c) and the quantity of

  QIH in the case of the deep depletion state without the external input of charges (the state of the curve (b)) are established in accordance with the information. For exemple,

  the quantity of charges QIL corresponds to a signal "0" (at

  see "L") and the quantity of charges QIH corresponds to a signal "1" (ie "H"). These signals are read using the difference of the quantities of charges in the two states,

  bQI = QIL - QIH = 5.3 x 102 [I / cm 2].

  In contrast, in the storage capacitor of the DRAM memory cell of the present invention,

  the charges intended to serve as information are

  spaces in at least one impoverished area.

  ment. That is, the DRAM according to the present invention

  This invention is characterized by the fact that no

inversion layer.

  Curves (d) and (e) illustrate the relationships between

  between the voltage of the capacitor electrode (the

  voltage of the first conductive plate) V and the concentration

  QSC loads near the surface of the region

  semiconductor 4, in the DRAM according to the present invention.

  the invention. The curve (d) is close to a curve that is obtained by moving the curve (a) in the negative direction of the voltage Vp (to the left in the figure). Curve (e) refers to the amount of space charge that appears in the depletion layer, but not in the inversion state. The flat web tension is set at VFBD = 1, 2 (V), which is to be compared to VFBI = -0.9 (V) of the prior art. In order to increase the amount of space charges in the depletion state through a slight modification

  of the flat web tension, the semicircular region is formed.

  In practice, the concentration of impurities is increased to 1.5 × 10 19 cm -1 relative to the impurity concentration of the p 1 -type substrate, which is 1.5 × 10 15 [/ cm3]. Therefore the quantity of charges

  to be extracted is increased. The range of tensions

  to establish the accumulation region h, the region of ap-

  poverty k and the inversion region m vary in a similar way. As has been described so far, the space charges of the depletion region can be effectively used by modifying the

  Vp and QSC relationship More specifically, when the first

  conductive plate 7, which is the electrode of the condensa-

  the voltage, which is applied to it, Vp = 0 VJ or [V] according to the information, the quantity of charges forming the information to be stored varies according to the curve (e). That is, the inversion layer is not

  not formed and that the state of deep depletion is established.

  Therefore the quantity of charges QDL for Vp = 0 IV] or the quantity of charges QDH for Vp = 5 CV] is stored. By way of example, the quantity of charges QDL corresponds to a signal "0" and the quantity of charges QDH corresponds to a signal "1". When the difference between the two charge quantities, QD = QDH-Q DL 5.6 x 1012 [/ cm2J is used, the 1-bit information can be stored in the memory cell. This quantity of charges is equal to or greater than that of the memory cell of the RAM memory of the prior art described above. In this way, the sufficient amount of fillers is obtained without using the inversion layer. Figure 3B illustrates the case where holes

  located in the accumulation region are used mainly

  as charges that are stored as

  training. This corresponds to the case of the formation of a re-

  P-type ion implantation ion, very shallow, and not in the case of formation of the semiconducting region.

  p-type deep as in Figures 2A and 2B. That is,

  This is an example of a case where boron ions are implanted at a shallow depth so as to act apparently as surface charges. The same elements

  3A are designated by references or symbols.

  identical boles and no description will be given.

  The curves (f) and (g) are close to the curves which are respectively obtained by shifting the curves (a) and (b) in the positive direction of the voltage Vp (to the right in the figure), and that of fixed values . Concretely, flat web tension is increased at VFBA

  = + 5.2 V compared to VFBI = -0.9 V in the prior art

  laughing. For this purpose, the surface charges are increased by planting boron ions at a very shallow depth. The

  ranges of voltages Vp intended to establish the accumula-

  tion h, the impoverishment region k and the inversion region

  sion m vary in a similar way in accordance with the variation

flat tape tension.

  As has been described so far, the holes in the accumulated state can be used effectively by changing the relationship between Vp and QSC

  More specifically, when the first conductive plate

  which constitutes the electrode of the capacitor at a voltage of

  Vp = 0 V or 5.2 [VJ, applied to it, in accordance with

  information, the amount of information used to inform

  to be stored varies according to curves (f) and (g). That is, the inversion layer is not used. The quantity of charges QAL is stored for Vp = 0 [V] and the quantity of charges QAH is stored for Vp = 5 V For example the quantity of charges QAL corresponds to a

  signal "0" and the quantity of charges QAH corresponds to a

  General "1". The difference between the two quantities of charges, QA - QAL QAH is greater than the quantity of charges

  ÈQI in the prior art. In this way we obtain the quantity

  sufficient loads without using the inversion layer.

  if we. The quantity of QAL charges is maintained by the holes in the stored state, and the quantity of QAH charges is maintained

  by the space charges in the depletion region.

  The QAH loads have a sign opposite to the charges

  of QAL, but this does not cause any inconvenience, and the difference

  the quantities of charges is designated 6QA. In-

  for V = 5 EV], the quantity of QAH charges is now

  Naked by the holes in the stock state, located on the left side by the holes in the stored state, located on the left side, of VFBA in Figure 3B. Curves (f) and (g) can be controlled by the dose of the impurity ions. In this example, the dose is equal to that used in the case of

Figure 3A.

  In addition to the principles illustrated in Figures 3A and 3B, it is possible to have a DRAM using both principles in combination. It is possible

  to increase the quantity of surface charges according to a

  any thode and simultaneously increase the amount of space charge in a depletion layer. In addition, the case of the use of a semiconductor substrate of the type

  n is similar. In this case the charges to be used as in-

  formation are space charges that consist of electrons in an accumulation layer or donors

in an impoverished state.

  We will now describe a possible method

  manufacturing process of the first form of the present invention.

  tion. Firstly, in order to produce a DRAM memory, a p-type semiconductor substrate is prepared.

  consisting of monocrystalline silicon (Si). As a representative

  4A and 4B, the semiconductor substrate 1 is partially covered by a thick field oxide film 2 (SiO 2 film) for electrically isolating predetermined memory cells, which are adjacent to one another, or semiconductor elements (not shown) which constitute a peripheral circuit, for example an addressing circuit, a read circuit or a recording circuit. The field oxide film 2 can be formed using the well-known technique

  according to which the thermal and local

  silicon stratum using a silicon nitride film as a mask. A p-type region can be disposed beneath the field oxide film 2

of channel stop device.

  After the operating phases illustrated in FIGS. 4A and 4B, an insulating film 3 is formed on the entire surface in order to produce a capacitor

  storage. As the insulating film 3, a film is used.

  silicon nitride (Si3N4), which is formed using CVD vapor deposition and has a constant

  relative dielectric is as high as 7 - 8 and which

  has a thickness equal for example to about 15 nanometers.

  In order to eliminate the stresses between the silicon nitride film and the semiconductor substrate 1, a first film of silicon dioxide (SiO 2) having

  a thickness equal for example to about 8 nanometers beyond

  below the silicon nitride film. In order to eliminate

  the pinholes of the silicon nitride

  a second silicon dioxide film is deposited

  having a thickness equal for example to about 3 nanometers

  meters on the silicon nitride film. We can

  the first and second SiO2 films by thermally oxidizing the surfaces of the semiconductor substrate and the silicon nitride film. Then, as illustrated in FIGS. 5A and 5B, a region is locally formed

  p-type semiconductor, intended to constitute the

  conductive plate conductive storage capacitor, in the vicinity of the surface of the semiconductor substrate 1 in

  an area intended for the formation of storage capacitors

  memory cells, and in particular of a machine

  unit with neighboring storage capacitors in the direction of the lines. As has been explained

  with reference to FIGS. 3A and 3B, the semiconductor region is formed

  driver 4 in the area designated for the training of

  storage denser, in order to produce a quantity enough

  significant amount of hole charges, or a layer of impoverishment

  to be stored in the storage capacitor

  and intended to form a fairly large amount of information

  or to obtain a threshold voltage (Vth) greater than an operating voltage which is applied

  to a first conductive plate, which will be described later

  surely. By way of example, it is introduced as impurities

  boron ions in an amount of the order of 5 x 10

  mes / cm2 using ion implantation and this at a ni-

  energy calf of about 30 keV. With a view to

  In accordance with the principle indicated with reference to FIG. 3A, it is possible to subject the introduced impurities to penetrating diffusion or redistribution. In this case the depth of the semiconductor region 4 is made equal to about 0.3 micron. On the other hand, in the case of the implementation of the principle indicated with reference to FIG. 3B,

  the penetrating diffusion or redistribution is not realized

  tion. In this case it is desirable to further reduce the

  ion implantation energy or introducing the impurities in a very shallow position of the substrate through another insulating film. This provision is intended to

  operate in such a way that the impurities introduced by

  ionic reactions act apparently in the form of

2 of surface.

  Figure 5C shows a portion of

  memory cell buckets that are formed with the p-type semiconductor regions 4. The field oxide film 2 is provided to provide electrical isolation between neighboring memory cells in the direction of the columns, i.e. following the direction in which a word line must extend (vertical direction in the figure). The field oxide film 2 is not arranged between the memory cells adjacent to each other in the direction of the lines, namely in the direction in which the lines

  bits must extend (horizontal direction).

  tale on the figure). In a memory cell array, the field oxide film 2 is provided in the form of a serpentine or meandering belt from one end to the other. The semiconductor region 4 is provided as a common region to the two capacitors adjacent to each other in the direction of the lines. Region 20 is a region arranged to surround the memory cell arrays and serve as guard rings. N-type impurities are introduced later in the

  region 20 at the same time as the formation of the tran-

  sistor MISFET Q, to be brought back to form a

  + type n. A section taken along the line of the V-V section plane in the figure is shown in Figure 5B. We

omitted the insulating film 3.

  After the operating phases illustrated in FIGS. 5A and 5B, the film is removed locally.

  insulation 3 to form a contact hole 5, in the

  electrical connection between the first conducting layer

  trice to be formed during a subsequent operational phase.

  and a semiconductor region to constitute the tran-

  MISFET sistor. The contact hole 5 is arranged to be remote from the semiconductor region 4. Then one forms

  over the entire surface a poly-silicon film

  crystalline material for forming the first conductive

  these, using a CVD chemical vapor deposition process. The polycrystalline silicon film may have a thickness of between about 150 - 300 nanometers by way of example. In order to give a low resistivity to the polycrystalline silicon film, it is implemented as

  treatment diffusion of phosphorus ions or arsenic ions

  senic (As) at a dose of about 5 x 1014 (atoms / cm 2) by ion implantation with an energy level of about 30 keV, after which treatment is performed.

  thermal. As a result of this treatment, the different impurities

  fuse by penetrating into the portion I the surface of the semiconductor substrate 1, which corresponds to the contact hole 5, in order to form the n-type semiconductor region 6 constituting

  the MISFET transistor which is formed by means of the operational phase

  indicated later. The depth of the semiconductor region 6 is about 0.2 micron. Then we realize a local structuring of the silicon film

  polycrystalline so as to form the first conductive plate

  7 is electrically connected to the semiconductor region 6 as shown in FIGS. 6A and 6B. It is

  as well as the memory capacitor C of memory cells

re is formed.

  After the operating phases illustrated on

  FIGS. 6A and 6B, mainly using film

  Silicon nitride of the insulating film 3 as a mask against a heat treatment is formed by thermal oxidation an insulating film 8 (SiO2 film) which covers the first conductive plate 7. This film can be given SiO2 8 a thickness equal for example to about 200 - 300 nanometers so that the first conductive plate 7 and the transmission line of

  words to be formed in a subsequent operational phase

  can be electrically isolated. Then we eliminate

  locally the insulating film to bare 3, after which, as shown in Figures 7A and 7B, is formed,

  in the removed part of the insulating film 3, a pel-

  insulating filler 9 (SiO2 film), used mainly to produce a film of gate insulators, by oxidation

  thermal of the exposed surface of the semiconductor substrate 1.

  This insulating film 9 has an equal thickness

example at about 20 nanometers.

  After the operating phases illustrated on

  FIGS. 7A and 7B form a film of silicon

  lycrystalline over the entire surface so as to form the gate electrodes of the MISFET transistors, the word transmission lines and the semiconductor elements of the peripheral circuit. This silicon film is subjected

  polycrystalline to the same treatment as above, in a manner

  to reduce its resistivity. Next, the polycrystalline silicon film is locally structured so as to form the gate electrode 10, the word-transmission line.

  (WL) 11 and the gate electrode (not shown) of the

  MISFET sistor of the peripheral circuit. We connect electrical-

  the gate electrode 10 to the gate electrode 10 of the other of the memory cells, adjacent in the direction of the columns, and forming the word transmission line 11 extending in the direction of the columns. As a gate electrode 10 or as a transmission line of

  words (WL) 11, it is also possible, for example, to use a

  a refractory material such as molybdenum (Mo), tungsten (W) or titanium (Ti), a layer of any silicide, which is the refractory metal compound and silicon, or a structure two-layer structure consisting of a polycrystalline silicon layer and a refractory metal layer or a silicide layer of a refractory metal covering the first layer. Then, in the area used to form the MISFET transistors,

  using the gate electrode 10 as a mask

  the introduction of impurities, we introduce impurities +

  of type n in a self-aligned manner to form the

  source region and the drain region of the MISFET transistor adjacent the surface of the semiconductor substrate 1 through the insulating film 9 located between these regions and

  the gate electrode. The impurities introduced are

  to the diffusion of penetration or redistribution, which + has the effect that the n-type semiconductor regions 12 intended to serve as source regions and as regions of

  drain are formed as shown in Figures 8A and 8B.

  The semiconductor region 6 is electrically connected to one of the semiconductor regions 12. Thus the transistor

  (MISFET) Q of the memory cell is formed.

  In addition, impurities formed of ions + arsenic can be used as n-type impurities and can be introduced by means of ion implantation so that they pass through the insulating film 9 Depth +

  n-type region is as low as 0.2 micron.

  After the operating phases illustrated in FIGS. 8A and 8B, an insulating film 13 is formed on the entire surface in order to achieve the electrical isolation of the gate electrode 10 as well as the transmission line of FIG. words (WL) 11 and the transmission line

  bits to be formed during a subsequent operational phase.

  pool. To form this insulating film 13, it is possible to use a phosphosilicate glass film (designated under the acronym PSG), which relieves the undulations of

  the surface and which can trap sodium ions (Na)

  both the electrical operation of the DPRAM memory. subse-

  secondly, in order to connect the other semiconductor region 12 and the bit transmission line to be formed in a subsequent operating phase, it is locally eliminated

  the insulating films 9 and 13 on this semiconducting region

  12 to form a contact hole 14. The bit transmission line (BL) 15, which is connected, is formed.

  electrically to the semiconductor region 12 via

  contact hole 14 and which extends along the di-

  lines. This line of transmission can be

  bit rate (BL) 15 for example using aluminum

  (HAVE). The resulting state is illustrated in Figures 2A and 2B.

  Then a PSG film and a silicon nitride film are formed by means of plasma deposition in phase

  vapor, in the form of a final passivation film.

  The DRAM of the present embodiment is completed with the implementation of this

  series of operating stages of manufacture.

  Hereinafter will be described the concrete operation of the first embodiment of the present invention. We will explain how the

  present embodiment in relation to the functioning of

26 2554954

  of a predetermined memory cell, referring to

Figures 2A and 2B.

  First of all, we will explain the case of

  recording of information in the memory cell. A voltage is applied selectively to the gate electrode 10 constituting the MISFET transistor Q of the cell.

  memory so as to place in the "conductive" state this

  MISFET Q. A voltage is applied to serve as

  transmission line (BL) 15, which is connected to

  electrically to the semiconductor region 12 via the

  In this way, the voltage of the bit transmission line (BL) corresponding to the information

  is applied to the first conductive plate through

  MISFET transistor Q. The semiconductor region 4

  serving as a second conductive plate is electrically connected

  only to the semiconductor substrate 1 and is kept

  VSS fixed differential as it has been predetermined. If there is a potential difference between the potential of the second conductive plate and the voltage constituting the information applied to the first conductive plate 7, charges forming the information are stored in the film

  3 which is the part between the conductive plates

  that is to say that these charges are recorded or stored in the storage capacitor C of the cell of

  memory, as indicated-usually.

  In the case of maintaining the information in the memory cell, the MISFET transistor Q can be placed in the "blocked" state, that is to say in the state in which

  the information was recorded in the storage capacitor

kage C of the memory cell.

  Outside of this, when reading the information from the memory cell, one can put in

  the reverse operation of the recording operation.

  According to the present invention, in a DRAM memory in which a series circuit constituted

  by a storage capacitor and a MISFET transistor used

  as a memory cell, a first

  conductive, which constitutes the storage capacitor, on a semiconductor substrate and is arranged so that it is electrically connected to a semiconductor region of the MISFET transistor, and there is a semiconductor region, which has a higher impurity concentration than

  of the semiconductor substrate, as a second

  ductor which constitutes the storage capacitor by the interposition of an insulating film, which has the effect of

  that the charges constituting the information can be stored

  in the storage capacitor by means of holes. By

  therefore, there is no need to use stored electrons

  ked in an inversion layer, as serving loads

  information, so that the influence of minority

  uselessly attributed to C2 particles or the injection of these particles from a peripheral part of the circuit

can be annihilated.

  Furthermore, since the storage capacitor does not need to be

  consider the degree of influence df on carriers

  unnecessary minority attributed to particles (or to

  such particles from the peripheral part of the

  of the circuit, it is possible to reduce the area of occupancy

  this circuit. This allows to integrate the DRAM memory

* with a higher integration density.

  In addition, the storage capacitor can be electrically isolated from another storage capacitor which is adjacent to the preceding one in the direction of the lines, by means of the semiconducting region constituting

  the second conductive plate, so that a film

  field oxide with a large surface area of

  tion becomes useless for the integration of the memo-

  DRAM with a high density of integration.

  We will describe a second form of realization

  of the present invention with reference to Figs. 9A-12B.

  Figure 9A is a plan view of the

  The essential elements of a DRAM memory cell make it possible to explain the structure of the present invention, whereas FIG. 9B is a sectional view taken along a line of IX - IX section plane in FIG. 9A. In all the figures of the present embodiment, the elements having the same functions as in the first embodiment are designated by the same symbols or references.

  and we will not give a new explanation.

  In Figs. 9A and 9B, reference numeral 18 denotes an insulating film which is shaped to cover at least a first conductive plate 7 and which serves to provide a storage capacitor. The capacitor is constituted by the insulating film 18 in combination

  with the first conductive plate 7 and a third elec-

  trode to be described later (hereinafter referred to as "third conductive plate"), and this

  insulating film 18 is capable of storing constituents

  killing information. The insulating film 18 is also

  able to electrically isolate the first conductive plates

  7 neighboring memory cells. The reference 16 designates the third conductive plate which is disposed on the insulating film 18 outside an area for forming a MISFET transistor Q and which serves to constitute the storage capacitor. A fixed potential, for example the same potential as that of a substrate 1, is applied to the

  third conductive plate 16. The third conductive plate

  Trice 16 is provided as the common electrode of an entire array of memory cells, wherein a plurality of memory cells are arranged in the form of a matrix. The third conductive plate 16 is pierced in a part intended for the installation of the MISFET transistor Q. The storage capacitor of the memory cell consists mainly of a parallel circuit formed of a

  capacitor C, which is constituted by the first plate con-

  7, by a semiconductor region 4 constituting a second conductive plate and by an insulating film 3, and a capacitor C1 which is constituted by the first conductive plate 7, the third conductive plate 16 and the insulating film 18. reference 19 denotes an insulating film which is arranged so as to cover

  the third conductive plate 16 and which serves to isolate electrical

  triply the third conductive plate 16 and a word transmission line (WL) 11. The semiconductor regions 4 and 6 are arranged so as to be distant from each other. When practicing practical networks of memory cells are made by using memory cells of the type shown in FIGS. 9A and 9B,

  gets the networks shown in Figure 10.

  Fig. 10 is a plan view of the essential parts of the schematic arrays of the memory cells for explaining the second embodiment of the present invention. In FIG. 10, in order to obtain a more convenient understanding of the drawing, it is not shown

  the insulating films to be arranged between the

  The shapes and positional relationships of the contact holes 5, the semiconductor regions 4 and other regions will be apparent from FIG. 9A, except for the respective conductive regions, the contact holes and the semiconductor regions. third conductive plate 16, the second embodiment is

  quite identical to the first embodiment.

  We will now describe a possible method

  manufacturing process of the second embodiment.

  Figs. 11A and 12A are plan views of the essential parts of a DRAM memory cell

  during the respective operating phases of manufacture

  both to explain the manufacturing method according to the present invention, while Figs. 11B and 12B are views

  in section taken along the cutting plane lines of the figures

res 11A and 12A.

  After the implementation of the operational phases

  of the first embodiment shown in FIGS. 6A and 6B, an insulating film 18 is formed on

  the entire surface so as to make a condensation

  storage. Just as in the case of film

  3, this insulating film can be produced.

  lant 18 with a silicon dioxide film, a pel-

  silicon nitride and another film of bioxy-

  of silicon. Then, on the entire surface, using the chemical vapor deposition process, a polycrystalline silicon film is formed to form a third conductive plate. The polycrystalline silicon film may have an equal thickness, for example

  at about 300 nanometers. In order to give a low resis-

  this polycrystalline silicon film, one introduces

  phosphorus or arsenic by the same method as indicated above. Subsequently, the polycrystalline silicon film is locally structured so as to form the third conductive plate 16 common to a plurality of memory cells outside a MISFET forming region, as shown in FIGS.

  Figures 11A and 11B. The storage capacitor C1 of cellulose

  the memory is thus formed. After carrying out the operating steps illustrated in FIGS. 11A and 11B, using mainly the silicon nitride film of the insulating film 18 as a mask against heat treatment, the coating layer is thermally oxidized.

  polycrystalline silicon constituting the third

  duct, so as to form an insulating film 19

  (SiO2 film) which covers the third conductive

  16. The insulating film 18 and the underlying insulating film 3 are then locally removed. As in the first embodiment, a film is formed.

  grid insulation 9 in the area where the elec-

  as shown in FIGS. 12A and 12B. Next, a gate electrode 10 is formed, a transmission line

  of words (WL) 11 and semiconductor regions 12.

  After the implementation of the operational phases

  illustrated in FIGS. 12A and 12B, a pel-

  insulating terminal 13, a contact hole 14 and a bit transmission line (BL) 15 as in the first form of

  production. Then the resulting structure is the one represented

  shown in Figures 9A and 9B. Then a film is

  of PSG and a silicon nitride film using

  the plasma vapor deposition process, to

  constitute a final film of passivation.

  The realization of the DRAM memory of the present invention is completed with the implementation of

  this series of operating stages of manufacture.

  Here we will describe the operation

  concrete of this second embodiment.

  We will explain how the

  present embodiment in relation to the functioning of

  of a predetermined memory cell with reference to

Figures 9A and 9B.

  First we will explain the case of

  the recording of information in the memory cell.

  A gate electrode voltage 10 constituting the MISFET transistor Q of the cell is selectively applied.

  memory in order to place in the "conductive" state this

  MISFET Q. A voltage corresponding to the information is applied to the bit transmission line (BL) 15, which is electrically connected to the semiconductor region 12 via the contact hole 14. Thus the voltage

  of the bit transmission line (BL) serving as information

  is applied to the first conductive plate 7 by

  via the MISFET transistor Q. The semicon-

  ductrice 4 serving as a second conductive plate is connected

  electrically to the semiconductor substrate 1 and is now

  held to the fixed potential VSS, as it has been predetermined. Similarly, the third conductive plate 16 is maintained at

  fixed potential VSs as an example. If there is a difference

  potential between the potentials of the second

  conductor and the third conductive plate 16 equal to each other and the voltage serving as information applied to the first conductive plate 7, charges

  used as information are stored in the

  3 and in the insulating film 18, which are the parts intervening between the conductive plates, that is to say that said charges are recorded or stored in the storage capacitor C and C 1 of the memory cell, as

this is usually indicated.

  In the case of maintaining the information in the memory cell, the MISFET transistor Q can be placed in the "off" state in the state in which the information has been recorded in the storage capacitor C and C1 of the

memory cell.

  In addition, in the case of reading information from the memory cell, it is possible to

  perform a reverse operation to the recording operation.

  In accordance with the present invention, effects similar to those obtained in the case of

the first embodiment.

  In addition by depositing a third conductive plate on a first conductive plate with the interposition of an insulating film, the amount of

  charges to be stored by the first lead plate

  trice and the second conductive plate and the quantity of

  charges to be stored by the first conductive plate

  trice and the third conductive plate can be

33 2554954

  stored in a storage capacitor. So when we compare the second embodiment to the first form

  realization, we see that it is possible to increase, envi-

  doubled, the amount of storage charges for condensa-

  storage unit by unit area, and that can be achieved

  the integration of the DRAM with an integration density

tion.

  In this respect, when the potential of a sub-

  stratum or of a p-type semiconductor region 4 is a substrate bias potential VBB = -3 V and that the potential of a polycrystalline silicon layer 16 and the ground potential Vss = 0 V, the quantity of charges stored

  becomes equal to about 1.5 times the amount of stored charges.

  in the absence of the polycrystalline silicon layer 16.

  In addition, when the third

  the second conductive plate-16 located at the fixed potential on the first conductive plate, a word transmission line WL, to which a control voltage of variable magnitude is applied, can not affect the first conductive plate 7, so that the quantity loads to be stored in the storage capacitor can

  be stabilized. Consequently, the registration operations

  DRAM can be stabilized, and it is possible to increase the reliability of the memory

DRAM.

  A third embodiment is achieved in that in the second embodiment, absolutely no thick field oxide film 2 isolating the memory cells is formed. Plan views

  and in section of the third embodiment are identi-

  those of Figures 9A and 9B and Figure 10B, in

  which the field oxide film 2 has been removed.

  For this reason, no explanation will be given for the plan and sectional views of the DRAM of the third embodiment, which will be described

  a possible method of manufacturing this form of

  tion, giving a brief description of the structure of the

this embodiment.

  Figures 13, 14 and 15 are plan views of the essential parts of the cell networks of

  moire at different stages of production

  tion, to explain the manufacturing method of the present embodiment. In all the drawings of this embodiment, the elements having the same

  functions only in the first and second forms of

  tion are designated by the same references or symbols and

do not repeat the explanation.

  First, except for part of the memory cell array, a semiconductor substrate 1 is partially covered by a field oxide film

  in order to electrically isolate the semiconductor elements

  (not shown) of a peripheral circuit. As in the first and second embodiments, an insulating film 3 is formed on the entire surface. Then a mask 17 is selectively formed for the introduction

  impurities, consisting for example of a film of nitrile

  1, in the region where the MISFET transistor of a switching element is to be formed in a subsequent operating phase. We cover with the mask 17 an area located outside

  of the memory cell network, namely an area in the

  which one must form the peripheral circuit. Subsequently using the mask 17, p-type impurities are introduced into the part of the semiconductor substrate 1, other than the mask 17, so as to form a p-type semiconductor region 4 which forms the second conducting plate of a capacitor. storing and electrically isolating neighboring memory cells according to the directions of the lines

  and columns, as shown in Figure 13.

  That is, the + p-type semiconductor region is formed over the entire surface of the memory cell array, except in the region where the transistors

MISFET must be available.

  After the implementation of the operational phases

  13, the mask 17 is eliminated, whereupon the insulating film 3 is locally removed so as to form a contact hole 5, in the electrical connection portion between a first conductive plate to be formed in a subsequent operating phase and a semiconductor region for producing the MISFET transistor. The contact hole 5 and the semiconductor region 4

  are arranged so as to be mutually distant. In-

  The polycrystalline silicon film is formed over the entire surface to form the first conductive plate and As is implanted in this film in order to reduce its resistivity and simultaneously to

  locally forming a n + 6 type semiconductor region.

  Subsequently, the silicone film is locally

  polycrystallineium to form the first plate

  conductor 7 as shown in FIG.

  After the operating phases illustrated in FIG. 14, as in the case of the second form of

  embodiment, an insulating film 18 and a third

  conductive plate 16 so as to achieve a conden-

  C1 storage server. After formation of the insulating films

  19 and 9, a gate electrode 10 is formed and a line

  of word transmission (WL) 11. By forming semi-

  12, the MISFET transistor Q is formed. After formation of an insulating film 13 and a contact hole 14, a bit transmission line (BL) 15 is formed as shown in FIG. the insulating films to be provided between the respective conductive layers have not been shown, in order to allow a

better understanding of the drawing.

  As in the first embodiment, it is possible to form the MISFET transistors Q so as to complete the realization of the DRAM memory, without forming the

storage capacitors C1.

  This series of manufacturing process stages

  cation makes it possible to complete the manufacture of the first form

  realization of the DRAM memory. Then we form a pel-

  final passivation as in the first or the

second embodiment.

  In accordance with the present form of

  tion, effects similar to those obtained in

the second embodiment.

  In addition, the cell can be electrically isolated from the DRAM memory with respect to other neighboring memory cells according to the directions of the lines and

  columns, using a semiconductor region constituting

  killing a second conductive plate intended to form a

  storage capacitor. Therefore a film of oxy-

  of field in an array of memory cells becomes useless and one can achieve the integration of memory

  DRAM with higher integration density.

  We will describe a fourth form of

  embodiment of the present invention with reference to the figures

  16A to 23B. This fourth embodiment is an example

  wherein a trench or groove is added to the first embodiment to increase the

  quantity of charges-which can be stored in a conden-

  sateur. In all the drawings of the present embodiment, the elements having the same functions as in the first embodiment are designated by the

  the same symbols or references, and it will not be repeated

  plication. In Figures W6A and 16B, reference 2

  means a film of field oxide. The cells of

  The structure or configuration of a pair of memory cells may be repeated in the direction of the lines as shown in FIG. network of memory cells, film

  field oxide 2 is disposed mainly between the

  neighboring memory blocks in the direction of the columns. Its layout is identical to that provided for in the first or

the second embodiment.

  Reference 21 designates a trench or

  groove, which is formed in a semiconducting substrate

  1 in a zone for forming a capacitor

  storage, and which serves to realize this storage capacitor.

  Kage. This trench 21 increases the amount of

  information per unit area in the storage capacitor. There is a + p-type semiconductor region 4 serving as a second conductive plate in the main surface of the semiconductor substrate 1 in the area provided for the formation of the storage capacitors, and in the surface of the substrate 1 inside the trench 21, and it is made in one piece with the capacitors

  neighboring storage in the direction of the lines. The situation

  such p-type semiconductor regions is

shown in Figure 19.

  Hereinafter, a manufacturing process will be described.

  cation of the fourth embodiment of the invention.

  Firstly, a film of oxide is formed

  field 2 (SiO2 film) and semiconducting regions

  + these p-type 4 using the same method as that of the first embodiment shown in the figures

4A, 4B, 5A and 5B.

  After the implementation of the operational phases

  9A and 5B, an insulating film 22A, an insulating film 22B and an insulating film 22C are formed on the entire surface of a semiconductor substrate 1 so as to form a trench or furrow and a second plate. conductive. The insulating film 22C forms a chemical etching mask for trench formation, and a film of silicon dioxide (SiO 2) may be used as an example for forming the film. The insulating film 22B is a mask vis-a-vis the introduction of impurities for the formation of the second conductive plate, and it can be used as an example to constitute this film a film of silicon nitride (Si3N4). Film

  insulation 22A serves to remove the stresses between the sub-

  semiconductor stratum 1 and the silicon nitride film 22B, and it is possible to use as an example for this film a silicon dioxide film. The insulating film 22A can be formed by thermal oxidation of the surface of the substrate 1. The insulating films 22B, 22C can be formed using CVD vapor deposition. The insulating film 22C is locally structured in a zone intended for the formation of a capacitor of

  storing, in order to form a first mask for the realization

  - the trench. Dry anisotropic etching is carried out using the first mask, resulting in local removal of the insulating films 22B and 22C so as to form a second mask on the outside

  of the insulating film 22B, and furthermore it eliminates local-

  a predetermined portion of the semiconductor substrate 1 so as to form the trench 21 as shown in Figs. 17A and 17B. The width dimension W of the trench 21 may be about 1 - 1.5 micron and its depth from the surface of the semiconductor substrate 1 may be

equal to about 2 - 4 microns.

  After the implementation of the operational phases

  17A and 17B, the insulating film 22C which has served as the first mask is removed, and the insulating film 22B, intended as a second mask, is exposed. Using this second mask, we introduce

  impurities in the vicinity of the surface of the semicon-

  1 to the trench 21, which has the effect that the p-type semiconductor region

  forming the second conductive plate is formed as

  shown in Figures 18A and 18B. By way of example, the semiconductor region 4 is formed by introducing boron ions (B) in a concentration equal to about 1 × 10 18 atoms / cm 3 or more by thermal diffusion at about 900 - 1000 C. In this case, the depth of the the semiconductor region 4 counted

  from the surface of the semiconductor substrate 1, directly

  from the inside, is about 0.3 micron.

  The state of memory cell networks

  after the formation of the semiconductor regions 4 is

  Figure 19. In Figure 19, there is no representation of

  insulating films 22A and 22B. A cut taken

  the cutting plane line B - B in Fig. 19 is

shown in Figure 18B.

  After removal of the insulating films 22B and 22A, the same insulating film 3 is formed as in

  the first embodiment in order to realize the con-

  storage denser, as shown in FIGS. 20A

and 20B.

  After the implementation of the operational phase

  FIG. 20A and 20B show a contact hole 5, an n-type semiconductor region 6 and a first conductive plate 7, as shown in FIGS. 21A and 21B, using the same method as that illustrated on FIGS. Figures 6A and 6B. The trench 21 may be filled with polycrystalline silicon to form the first conductive plate 7, so as to make the

surface of the trench.

  After the firing steps illustrated in Figs. 21A and 21B, primarily using the silicon nitride film of the insulating film 3 as a mask against heat treatment, an insulating film 8 (SiO 2 film) is formed by thermal oxidation. covers the first conductive plate 7. The insulating film 8 is given a thickness equal to about

  - 300 nanometers, so that the first conductive plate

  7 and a word transmission line to be formed by means of a subsequent operating phase can be electrically isolated. Thus, in the case where the portion of the trench 21 is not filled, fill the inside of the groove using a filling material, for example

  example a polycrystalline silicon film or a pel-

  insulating filler. Polycrystalline silicon must be

  formed of an oxidation insulator. Then we eliminate

  the insulating film 3, which has the effect that the same insulating film 9 as in the first embodiment is formed as shown in FIGS.

22A and -22B.

  After the implementation of the operational phases

  FIGS. 22A and 22B illustrate the formation of a MISFET transistor Q and a WL word transmission line as shown in FIGS. 23A and 23B. These are the same elements as those of the first embodiment

  shown in Figures 8A and 8B.

  Then an insulating film 13 and a bit transmission line BL, etc. are formed as in

  the first embodiment. So we get the structure

  resulting image as shown in Figs. 16A and 16B. Next, a PSG film and a silicon nitride film are formed by CVD chemical vapor deposition to form a film.

of final passivation.

  This series of operative peases

* brication allows to complete the realization of this

  embodiment of the DRAM. Operations, which occur in the case of the registration of a

  information in the memory cell of the fourth embodiment, the maintenance of the information and the reading of this information, are identical to those involved in the first embodiment.

  In accordance with the fourth form of

  the same effects as in the case of

first embodiment.

  In addition it is possible to prevent the modification of the quantity of stored charges attributable to carriers

  minorities, as well as the coupling of the impoverished area

  trench with that of another trench in the deep portions of the trenches.

  deep trenches can be made. We can also

  reduce the distance between adjacent trenches,

  know the distance D1 shown in Figure 17A.

  Moreover, since all the

  capacitors are p-type semiconductor regions, it is possible to reduce the distance D2 between a trench and a film

  field oxide as shown in Figure 17A.

  We will describe a fifth form of

  of the present invention with reference to Figs. 24A, 24B and 25. Since the manufacturing method of this embodiment is substantially similar

  to that implemented in the case of the fourth form of -

  realization, we will not give the explanation. The fifth embodiment is an example in which the first conductive plate of the fourth embodiment is

  additionally covered by a third conductive plate

  to which a fixed potential is applied in order to

  increase and stabilize a capadcité.

  In the drawings of this form of

  the elements having the same functions as in the fourth embodiment are designated by the same reference symbols and the explanation will not be repeated. In FIGS. 24A and 24B, reference numeral 18 denotes an insulating film, a similar constitution

  to the previous insulating film 3, which is disposed of

  It is intended to cover at least a first conductive plate 7 and serves to provide a storage capacitor C1. This

  insulating film 18 stores charges through the first

  7 and a third electrode which will be described later (hereinafter referred to as "third conductive plate"). This insulating film electrically isolates the first conductive plates 7 from neighboring memory cells. Reference 16 designates the

  third conductive plate for conducting the conden-

  storage device and which is arranged on the iso-

  18, which is connected and made in one piece with the third conductive plate of the other memory cell located in a network of electrodes. identical memory cells. A fixed potential, for example the same potential as that of a substrate, is applied to this third conductive plate 16. The storage capacitor of the memory cell consists essentially of

  a parallel circuit formed by a capacitor C which is

  of the first conductive plate 7, a semicircular region

  conductor 4 formed of a second conductive plate and the insulating film 3, and by a capacitor C1 which is

  formed by the first conductive plate 7, by the third

  the second conductive plate 16 and the insulating film 18.

  Reference 19 designates an insulating film which is

  placed so as to cover the third conductive plate 16 and which is used to electrically isolate the third plate

  conductor 16 and a word transmission line (WL) 11.

  When we realize the networks of cellu-

  practical storage using the memory cells as shown in FIGS. 24A and 24B,

  the assembly shown in FIG.

  FIG. 25 is a plan view of the essential parts of the schematic networks of

  memory, making it possible to explain the fifth form of

  of the present invention. In Figure 25, in order to

  to make the understanding of drawing easy, we have not

  the insulating films to be placed between

respective conductive layers.

  A figure obtained by omitting the three

  conductive plates 16 in Figure 25 is identical

  in the plan view of the fourth embodiment.

  The operations involved in the fifth

  me form of realization are the same as those intervening

  in the second embodiment.

  In accordance with the fifth form of

  the effects, the effects are similar to those

  fourth or fourth embodiment.

  We will describe a sixth form of reali-

  FIG. 26, 27 and 28. The sixth embodiment is an example in which omitted

  the field oxide film 2 of the fifth form of

  electrically isolated the memory cells

  sines in the direction of the columns, and in which absolutely no film of field oxide is disposed

  inside the memory cell network.

  Figures 26 to 28 are plan views

  essential parts of memory cell networks

  during different phases of manufacturing operations, allow-

  both to explain the manufacturing method of the present embodiment. In all the drawings of this

  embodiment, the elements possessing the same functions

  that in the case of the third and fourth embodiments are designated by the same symbols or references,

  and we will not repeat the explanation.

  Firstly, except for a portion of memory cell arrays, a semiconductor substrate 1 is partially covered by a field oxide film by means of the local thermal oxidation of the substrate 1 so

  electrically isolating the semiconductor elements (not

  presented) of a peripheral circuit. A trench or groove 21 and the insulating film 3 are formed. Next, a p-type semiconductor region 4 is formed in the entire network surface of the memory cell except in an area covered by a mask 17, using the same process

  than that illustrated in Figure 13.

  After the operating phases illustrated in FIG. 26, a contact hole 5, an n + type semiconductor region 6 and a first conductive plate 7 are formed using the same method as in FIG. 14. A section of FIG. identical to FIG. 21B, on which the field oxide film 2 is replaced by the +

p-type semiconductor 4.

  After the implementation of the operational phases

  illustrated in Fig. 27, as in the third embodiment, an insulating film 18 and a third conductive plate 16 are formed so as to realize

  a storage capacitor C1. After formation of the pellicu-

  insulators 19 and 9, a gate electrode 10 and a word transmission line (WL) 11 are formed, and semiconductor regions 12 are formed so as to thereby provide a MISFET transistor Q. After forming an insulating film

  13 and a contact hole 14, a transmission line 14 is

  bit mission (BL) 15 as shown in FIG.

  In this figure 28, in order to make the drawing more comprehensible, the insulating films to be arranged between the respective conductive layers have not been shown. In addition, a section of FIG. 28 is identical to FIG. 24B, in which the field oxide film 2 is replaced by the p-type semiconductor region. Then one carries out the treatment of a protective film, etc. as in the

first embodiment.

  In the present embodiment, the +

  p-type semiconductor region and the semiconducting region

+

  type 6 do not need to be

  this one of the other as in the other forms of realization. The operations involved in the sixth embodiment are the same as those intervening

  in the second embodiment.

  In accordance with the sixth form of

  tion, effects similar to those obtained in

  third and fourth embodiments.

  In the present embodiment, it

  It goes without saying that the formation of the third conductive

  this can be perfectly omitted. This is identical to the

  relationship between the third embodiment and the first

  re embodiment. The plan and sectional views of

  lules of the DRAM memory in this case and the sectional views of the latter during the manufacturing process phases

  are contained in the description of the third and fourth

embodiments.

  The present embodiment has the following effects: A storage capacitor is an insulating film which is disposed on the surface of a semiconductor substrate by a first conductive plate having an end portion disposed on the insulating film and the other part of which is arranged to be electrically connected to a semiconductor region of a MISFET transistor and to a semiconductor region for serving as a second conductive plate, which is arranged in a

  a predetermined surface area of the semiconductor substrate.

  This removes the coupling between the depletion layers

  neighboring storage capacitors, and the leakage of

between them.

  Since the leakage of charges is

  eliminated, the duration of retention of charges in the conden-

  storage is increased and the frequency of operations

  refresh or regeneration is reduced. As a result

  The speed of operation of the DRAM is increased. As charges to be stored in a storage capacitor, the charges located in an accumulation layer or in a narrow depletion layer are used. Therefore it becomes unnecessary to use electrons that are stored in a depletion layer

  extended or in an inversion layer, so that the memory

  DRAM DR is not affected by minority holders.

  Since the degree of influence of the minority carriers on a storage capacitor does not need to be taken into account, it is possible to reduce the occupation area of a storage capacitor. This is why we realize the integration of the DRAM memory with a

  higher integration density.

  Since the charges can be stored between a first conductive plate and a second conductive plate and between the first conductive plate and a third conductive plate, the amount of charges stored in a storage capacitor per unit area

increases.

  A memory cell is electrically isolated

  only relative to another memory cell, which is adjacent to it in the direction of the lines and / or in the direction of the columns, by a semiconductor region which

  forms a second conductive plate constituting a condensa-

  storage. An insulating region consisting of a pel-

  insulating filler becomes useless and the integration of memory4

  DRAM can be realized with a higher integration density

  pool. The occupancy area of a cell of

  memory can be significantly reduced and it is possible to

  to integrate the DRAM memory with an even higher integration density.

  By arranging a third conductive plate

  trice placed at a fixed potential on a first plate

  driver, the influence of a transmission line is eliminated.

  words on the first conductive plate, and

  read the quantity of loads to be stored in a

  storage denser. Registration and

  reading of the DRAM are also stabilized.

  Since a semiconductor region having a first conductivity type and constituting the

  capacitor of a memory cell and a semicon-

  conductor having a second conductivity type and connected to the MISFET transistor of the memory cell are arranged so as to be distant from each other, the voltage of the

  reverse breakdown of a voltage is not impaired.

  Although, in the foregoing, the invention has been concretely described with reference to certain embodiments, it goes without saying that the present invention

  not limited to the embodiments indicated above.

  and you can make changes

  without departing from the scope of the invention.

  For example, we can also

  to locate a region of p-type wells in a semicon-

  n-type conductor and forming the cells of a DRAM in the well region. In addition it is possible to use an n-type semiconductor substrate and to use a region

  n-type semiconductor as a second conductive plate

  trice to store information loads. Apart from this it is possible to form a well area of

  type n in a p-type semiconductor substrate and realize

  the cells of a DRAM memory inside the

wells.

  In the fourth, the fifth or the

  twelfth embodiments, one can quite use a

  ion implantation process as a method of forming

  a semiconductor region which forms a second conductive plate. In this case, ion implantation is performed in the state shown in Fig. 18B. The implanted impurity element, for example boron, is introduced into the bottom of a trench 21. The boron can be diffused under the effect of a

  subsequent annealing so as to form a semiconducting region

  in the bottom of the trench 21 and crotch it along the sidewall of the trench toward the surface of the substrate. This is why the semiconductor region is also formed in a part of the side wall of the trench. The semiconductor region extending along the sidewall does not reach the vicinity of the surface of the

  substrate (a region where a semicircular region

  conductor 6 having the opposite conductivity type). With this arrangement, the capacity of a memory cell is reduced to a certain degree, but a mask alignment margin can not be used to spatially

  semiconductor regions 4 and 6 having the types of

  mutually opposite

Claims (18)

  1. Semiconductor memory device   characterized in that it comprises networks of   memory cells (M11, M12, M21, M22, ...), wherein the memory cells are arranged in the form of a matrix and each comprise a switching element (Q) and a capacitor (C, C1) formed on a main surface of a semiconductor substrate (1) having a   first type of conductivity and which is connected to this   switching capacitor (Q), that said capacitor (C, C1) is constituted by a first insulating film (3), which is   formed on the main surface of said semiconductor substrate   a first electrode (7), a part of which is electrically connected to said switching element (Q) and which is formed on said first insulating film (3) and which is independent for each memory cell, and by a first semiconductor region (4) for   forming a second electrode, which is formed in said subset   semiconductor substrate below said first insulating film (3) and which has the first conductivity type and an impurity concentration higher than that of said first   semiconductor substrate (1), and that the first semiconductor region   conductor (4) of a memory cell is connected to the first semiconductor region (4) of at least one of the memory cells, which adjoins said memory cell to   inside the same network of memory cells, by   intermediate of a second semiconductor region which is formed in said semiconductor substrate and which has the   first type of conductivity and a concentration of impure-   higher than that of said semiconductor substrate.   2. Semiconductor memory device   in accordance with claim 1, characterized in that said capacitor (C, C1) is formed by use of a trench (21) which is formed by removing said semiconductor substrate (1) from said main surface of   the latter, in the direction of the interior, and that said first   first semiconductor region (7) is formed in said   main face of said semiconductor substrate and in a surface of said trench.   A semiconductor memory device according to claim 1, characterized in that the first semiconductor region (7) of a memory cell is connected to the first semiconductor region (7) of a   memory cell, which is close to said cell of   within the same memory cell array and which is connected to a bit transmission line (15,   BL) identical to that of said memory cell and also   to a word transmission line (11, WL) adjacent to said memory cell.   4. Semiconductor memory device   in accordance with claim 1, characterized in that said capacitor (C, C1) comprises a first capacitor (C) and a second capacitor (C1), which is formed on said first capacitor, that said first capacitor (C) is constituted by the first insulating film (3) which is   formed on the main surface of said semiconductor substrate   the first electrode (7), a part of which is electrically connected to said switching element (Q) and which is formed on said first insulating film and is independent for each memory cell, and by the   first semiconductor region (4) serving as the second   trode, which is formed in said semiconductor substrate (1)   below said first insulating film and which   the first type of conductivity and an impurity concentration higher than that of said semiconductor substrate, and that said second capacitor (C1) is constituted by the first electrode (7), by a second insulating film (18) which is formed on at least said first electrode, and by a third electrode (16) which is formed on at least said insulating film.   5. Semiconductor memory device   in accordance with claim 4, characterized in that said third electrode (16) is an electrode common to all memory cells of the same memory cell array and is integrally formed within the memory array. memory cells.   6. Semiconductor memory device   according to claim 5, characterized in that said second insulating film (18) is formed below   the whole of the third electrode.   7. Semiconductor memory device   in accordance with claim 5, characterized in that   the third electrode (16) is connected to a potential of   mass of said semiconductor memory device.   8. Semiconductor memory device   in accordance with claim 4, characterized in that said capacitor (C, C1) is formed by the use of a trench (21) which is formed by removing said semiconductor substrate (1) from said main surface of   the latter, in the direction of the interior, and that said first   first semiconductor region (7) is formed in said   main face of said semiconductor substrate and in a surface of said trench.   9. Semiconductor memory device   in accordance with claim 4, characterized in that the   first semiconductor region (4) of a memory cell   re is connected to the first semiconductor region (7) of a memory cell, which is near said cell   of memory within the same network of cells of   which is connected to a transmission line of   bits (15, BL) identical to that of said memory cell.   re and also to a word transmission line (11, WL)   adjacent to said memory cell.   10. Semiconductor memory device   in accordance with claim 1, characterized in that the   seems from said first semiconductor regions (4) to   within the same network of memory cells are connected   corded to each other by means of said second resection semiconductor.   A semiconductor memory device according to claim 10, characterized in that said capacitor (C, C1) is formed by the use of a trench (21) which is formed by removal of said semiconductor substrate (1) from said main surface of   the latter, in the direction of the interior, and that said first   first semiconductor region (7) is formed in said   main face of said semiconductor substrate and in a surface of said trench.   12. Semiconductor memory device   in accordance with claim 10, characterized in that said capacitor (C, C1) comprises a first capacitor (C) and a second capacitor (C1), which is formed on said first capacitor, that said first capacitor (C) is constituted by the first insulating film (3) which is   formed on the main surface of said semiconductor substrate   the first electrode (7), a part of which is electrically connected to said switching element (Q) and which is formed on said first insulating film and is independent for each memory cell, and by the   first semiconductor region (4) serving as the second   trode, which is formed in said semiconductor substrate (1)   below said first insulating film and which   the first type of conductivity and an impurity concentration higher than that of said semiconductor substrate, and that said second capacitor (C1) is constituted by the first electrode (7), by a second insulating film (18) which is formed on at least said first electrode, and by a third electrode (16) which is formed on at least said insulating film.   13. Semiconductor memory device   in accordance with claim 12, characterized in that   said third electrode (16) is an electrode common to all memory cells of the same memory cell array and is formed integrally within the memory cell array.   14. Semiconductor memory device   in accordance with claim 12, characterized in that   said second insulating film (18) is formed under the appears from the third electrode.   15. Semiconductor memory device   in accordance with claim 13, characterized in that said third electrode (16) is connected to a potential of   mass of said semiconductor memory device.   16. Semiconductor memory device   according to claim 12, characterized in that said capacitor (C, C1) is formed by the use of a trench (21) which is formed by removing said semiconductor substrate (1) from said main surface of   the latter, in the direction of the interior, and that said first   first semiconductor region (7) is formed in said   main face of said semiconductor substrate and in a surface of said trench.   17. Semiconductor memory device   characterized in that it comprises networks of   memory cells (M11, M12, M21, M22, ...), wherein the memory cells are arranged in the form of a matrix and each comprise a switching element (Q) and a capacitor (C, C1) formed on a main surface of a semiconductor substrate (1) having a   first type of conductivity and which is connected to this   switching capacitor (Q), that said capacitor (C, C1) is constituted by a first insulating film (3), which is   formed on the main surface of the semiconductor substrate   a first electrode (7), a part of which is electrically connected to said switching element (Q) and which is formed on said first insulating film (3) and which is independent for each memory cell, and by a first semiconductor region (4) for   forming a second electrode, which is formed in said subs-   semiconductor substrate below said first insulating film (3) and which has the first type of conductivity and an impurity concentration higher than that of said semiconductor substrate (1), said capacitor causing a   amount of space charge of at least one layer of   the expression within that second   semiconductor, in first and second con-   first and second potentials which are   said first electrode.   18. Semiconductor memory device   The apparatus according to claim 17, wherein said capacitor changes the amount of space charge of the depletion layer appearing in said second capacitor.   semiconductor region and a quantity of charges of one   accumulator within said second semiconductor region, in first and second states in accordance with   to first and second potentials that are applied to the- said first electrode.