GB2115191A - Apparatus for the synchronization of pulse controlled data processing equipment - Google Patents

Abstract

Apparatus for synchronizing pulse controlled units of data processing equipment (1, 2) with which are associated respective external pulse generators (CLa, CLb) which are in operative association with internal poly-phase pulse generators (10a, 10b) which generate pulse signals ( phi 1a, phi 2a, phi 1b, phi 2b), wherein a pulse signal ( phi 2a) of one unit (1) is compared (14a, 14b) with a pulse signal ( phi 2b) of another unit (2) to provide temporal synchronization. The signal from the associated pulse generator (CLa, CLb) fed to one unit of data processing equipment (1, 2) is suppressed (17a, 17b) for at least one signal period, on exceeding a predetermined temporal deviation between the pulse signals ( phi 2a, phi 2b). The apparatus is especially suited to the synchronization of a plurality of anti-locking systems in a motor vehicle. <IMAGE>

Description

SPECIFICATION Apparatus for synchronizing pulse controlled data processing equipment State of the Art The invention originates from an apparatus according to the preamble to the main claim.

It is known to operate a plurality of pieces of data processing equipment in parallel each pulse controlled by an external pulse generator. Moreover, an asynchronous or a synchronous operation is possible. In so doing, it is usual to provide in the data processing equipment a poly-phase pulse generator which generates a plurality of fixed phase coupled pulse signals of different phase relationship. Finally, in order to monitor the temporal synchronization of the pieces of data processing equipment it is known to monitor these pulse signals having regard to temporal synchronization.

Advantages of the Invention The apparatus in accordance with the invention comprising the characterising features of the main claim has the advantage that, with simple means, a digital synchronization monitoring is possible wherein a synchronization is set collectively and which lies within a permissible region, preferably one period of the supplied external pulse signal.

Advantageous further developments of the apparatus set forth in the main claim are made possible by the measures set forth in the sub claims.

Thus, in a preferred form of the invention with two pieces of data processing equipment operating in parallel, a synchronous monitoring is undertaken through a cross-over wherein on the one hand a redundant nonsynchronous indication is possible and on the other hand that particular data processing system which lags or leads can be re-set.

By monitoring the temporal frequency of resetting operations in two redundant systems, it is furthermore ensured that unallowable variations are indicated reliably and in good time.

In a further form of the invention, the two pieces of data processing equipment are driven in the master-slave operation wherein the poly-phase pulse generator of the slave system only serves for monitoring functions, for example of the synchronization. In that way, it is guaranteed, on the one hand, that all pieces of equipment operate in strict synchronization with respect to one pulse generator and on the other hand the temporal constancy of the generator is monitored. Moreover, in a further advantageous manner, it is possible by switching over the master-slave operation to switch over the pieces of data processing equipment to another pulse generator if one pulse generator should fail.

A particularly advantageous inventive use of the apparatus in accordance with the invention is provided for data processing equipment requiring a high degree of safety, for example in anti-locking systems in motor vehicles.

Further advantages will become apparent from the description and the accompanying drawing.

Drawing The invention is illustrated in the drawing and is explained in detail in the following description. Fig. 1 shows a fundamental representation of an apparatus comprising a plurality of synchronized pulse controlled pieces of data processing equipment operating in parallel; Fig. 2 is a detailed block circuit diagram of a first embodiment of an apparatus in accordance with the invention comprising two pieces of data processing equipment operating in parallel; Figs. 3 and 4 are temporal representations of signal curves for explaining the apparatus illustrated in Fig. 2; Fig. 5 is a block circuit diagram of a further embodiment of an apparatus in accordance with the invention; Fig. 6 shows time diagrams of signals for explaining the embodiment according to Fig. 5.

Description of the Embodiments Three pieces of data processing equipment 1, 2, 3 operating in parallel are illustrated in Fig. 1 each of which is provided with an external pulse generator CLa, CLb, CLc. The pieces of data processing equipment 1, 2, 3 are on the one hand connected to one another by a pulse line f and on the other hand by a data line D.The pieces of data processing equipment 1, 2, 3 can be optional equipment in which data is processed and/or exchanged wherein a synchronous operation of the pieces of data processing equipment 1, 2, 3 is ensured by the pulse line +. In the illustrated embodiment, the pieces of data processing equipment 1, 2, 3 comprise anti-locking systems 1 1 a, 1 1 b, 1 1 c in which operational parameters of a vehicle are processed in known manner in order to derive therefrom control signals for the brake system of the motor vehicle under critical driving situations.

The co-operation between two of the pieces of data processing equipment 1, 2 is illustrated in more detail in the block circuit diagram according to Fig. 2. As can be seen, pieces of data processing equipment 1, 2 are of identical construction and are connected to one another by a cross-over. Moreover, each piece of data processing equipment 1, 2 includes a poly-phase pulse generator 1 ova, 1 0b to which the signals are supplied from the external pulse generator CLa, or CLb. Polyphase pulse generators of that kind generate fixed phase pulse signals coupled to one another, in known manner, in the illustrated example two signals 4 > 1at02a; 01bw 2b.In the illustrated embodiment, these fixed phase coupled pulse signals serve for controlling the subsequently connected anti-locking system 1 1 a, 1 1 b with respect to time.

In the apparatus illustrated in Fig. 2, the synchronizing of the pieces of data processing equipment 1, 2 is undertaken by the respective second pulse signal 2a or 02b. In addition, these signals are transmitted through amplifiers 1 2a or 1 2b to the respective other pieces of data processing equipment where they are processed in amplifiers 1 3a or 1 3b and are transmitted to an exclusive OR-gate 1 4a or 14b the other input to which is influenced by the respective pulse signal of the said piece of data processing equipment. The output from the exclusive OR-gate 14a, 14b is fed through an AND-gate 1 5a or 1 5b to the input to a synchronizing circuit 1 6a or 1 6b to which the signals from the external pulse generators CLa or CLb are transmitted.On control by the AND-gate 1 5a or 1 sub, synchronizing circuit 1 6a or 1 6b forms a positive output signal Sa, Sb of the length of one or more periods of the signals from the external pulse generators CLa or CLb. These output signals Sa, Sb are transmitted to an inverting input to an ANDgate 1 7a or 1 7b through which the signals from the external pulse generators CLa or CLb are transmitted to the poly-phase pulse generators 1 Oa and 1 Ob. Thus, when the synchronizing circuits 1 6a or 1 6b respond, these signals are suppressed for one or more periods.

Furthermore, the outputs from the exclusive OR-gate 14a or 14b are transmitted to counting inputs T of counters 1 9a, 1 9b the resetting inputs R of which are controlled by a further counter 1 8a or 1 8b the counting inputs T of which are directly controlled by the monitored pulse signal 2a or 2b. Finally, the overflow outputs Q from the counters 1 9a and 1 9b are transmitted to output terminals 20a and 20b.

The method of operation of the apparatus illustrated in Fig. 2 will be explained in the following with the aid of the signal curves in Fig. 3: Moreover, Fig. 3a shows the output signal from one external pulse generator CL; Figs.

3b and 3c pulse signals 2, +1 generated by a poly-phase pulse generator 1 ova, 1 Ob; Figs.

3d and 3e show the monitor pulse signals 02at < > 2b illustrated in the embodiment of Fig. 2 and Figs. 3f and 3g shows the output signals from the synchronizing circuit 1 6a and 1 6b.

As already stated, poly-phase pulse generators 1 Oa, 1 Ob generate pulse signals 2, ft in accordance with signals supplied from the external pulse generator CLa or CLb. These pulse signals are fixed phase coupled and have a relative phase location which is matched to the requirements of the substantially connected anti-locking system 11 a, 11 b.

Since the signals +2 < )1 are fixed phase coupled, only a plurality of pieces of data processing equipment 1, 2 connected in parallel are necessary for monitoring the synchronization, each arranged to monitor one of the said signals with the corresponding respective signal of the other piece of data processing equipment. In the embodiment illustrated in Fig. 2, these are the signals < )2a and 2b. As can be seen from the left-hand half of Figs.

3d and 3e the case is illustrated in which the signal < 22a is advanced with respect to signal 2b. If these signals are now compared to one another in the exclusive OR-gates 1 4a, 14b an output signal is present at these gates during the period T1. It is then ensured by the subsequently connected AND-gate 1 spa, 1 5b that the synchronizing circuit 1 6a, 1 6b only activates that particular piece of data processing equipment 1, 2 the pulse signal of which is advanced with respect to time.This is effected by the fact that the pulse signal is transmitted to an inverting input to the ANDgate 1 5a or 1 5b so that the particular synchronizing circuit 1 6a or 1 6b is operated the associated pulse signal of which is practically zero during the time interval T,. In the illustrated example, this is the signal < )2a so that the synchronizing circuit 1 6a is operated but is so designed that it only delivers an output signal when the temporal deviation established by the logic elements 1 4a, 1 5a is greater than one period duration of the CL signal. This threshold can be established because synchronizing deviations below the period duration of an external pulse signal are generally not critical for the further data processing.Since, in the illustrated example, the time period T, is longer than a period duration of the CL signal, the output signal Sa is generated after the period duration has passed corresponding to Fig. 3f of the synchronizing circuit 1 6a and which in the present case has the duration of one CL period. However, it is clearly also possible to so design the synchronizing circuit 1 6a that when the time interval T, is longer than a plurality of CL periods, the Sa signal also has a corresponding number of CL period durations.

The signal Sa causes blocking of the ANDgate 1 7a for the duration of one or more CL periods so that the poly-phase pulse generator 1 0a is re-set by this time. Consequently, an output signal 2a is produced which instead of the dotted line curve illustrated in Fig. 3d has the full line curve. As can be seen from Figs.

3e and 3d a complete synchronization of the signals #2a' +2b is still not produced thereby however, the remaining synchronization deviation is less than one CL period duration so that no further re-setting then takes place since this synchronization deviation is within the tolerance range.

The case is then illustrated in the right-hand half of Figs. 3d, 3e and 3g where the signal #2b is advanced. In this case, the 2a signal occurs during one time duration T2 but not the < t2b signal. An operation of the exclusive OR-gate .1 4a, 14b then takes place in a corresponding manner but only the AND-gate 1 5b becomes conductive since the b2b signal is then zero. Consequently, the poly-phase pulse generator 1 Ob is re-set in a similar manner to the above description by a signal Sb as shown in Fig. 3g so that instead of the dotted curve of < > 2b in Fig. 3e the full line curve is produced.

It is of course to be understood that the particular temporal over running poly-phase pulse generator can be re-set by a corresponding inversion of the logic used.

As described above, with any interference in the synchronization of the signals zi > 2at +2but both exclusive OR-gates 1 4a, 1 4b respond since the selection with respect to the particular advancing signal first of all takes place in the subsequently connected AND-gate 1 5a or 1 sub. The output signals from the exclusive OR-gate 1 4a, 1 4b are always counted in the counter 1 9a or 1 9b when the interference to synchronization is longer than a CL pulse.

However, this counter 1 9a or 1 9b is periodically re-set and indeed in accordance with the over run output Q from the counter 1 8a or 1 8b which are directly influenced by the pulse signals +2a and F2b. The behaviour with respect to time of the counter condition Z, of the pulse input T, the re-setting input R and of the over run output Q of the counter 1 9a or 19b are illustrated in Figs. 4a to 4d. As is recognised, only four signals occur at the input T during the first illustrated phase I and which signal the response of the exclusive OR-gate 1 4a, 1 4b so that the over run Q of the particular counter 1 9a or 1 9b is not reached before the re-setting signal R arrives from the counter 1 8a or 1 8b.Since these counters 1 8a and 1 8b are likewise influenced by the signals (t12a and g2b the combined circuit of the two counters produce a determination of the frequency of the response of the exclusive OR-gate 14a or 14b. In phase II illustrated in Fig. 4, can be appreciated a substantially greater frequency of these resetting operations symbolised by the signals T so that in this second phase the over run Q is reached before the arrival of the re-setting signal R. This signal 0 is then forwarded to the terminals 20a or 20b so that it can be used for releasing indicating devices or alarm devices or for influencing the anti-locking system 11a, 11b.

Since both exclusive OR-gates 14a, 14b always respond, the counters 1 8a, 1 9a or 1 8b, 1 9b operate identically so that the signals also occur simultaneously at the terminals 20a, 20b. Furthermore, a monitoring of its method of operation is possible through this redundant arrangement.

Fig. 5 shows a further embodiment of an apparatus in accordance with the invention.

Whereas with the embodiment according to Fig. 2, each piece of data processing equipment 1 or 2 has fed the respective internally generated pulse signals q > 1at 652a or 6i1b +2b to the anti-locking system 1 1 a or 1 1 b, a masterslave arrangement is used in the embodiment according to Fig. 5 in which only one piece of data processing equipment generates the pulse signals f" < S > 2for all the anti-locking systems 1 1 a, 1 1 b connected in parallel whilst the pulse signals from the other piece of data processing equipment are used only for monitoring purposes.To this end, switches 30a, 31a and 30b and 31b are used in the embodiment illustrated in Fig. 5 in the output from the poly-phase pulse generators 1 Oa and 10b which can be controlled by external means MSU. In the case illustrated in Fig. 5, the switches 30a, 31 a of the piece of data processing equipment 1 are controlled by a positive signal so that they conduct whereas the switches 30b, 31 b of the piece of data processing equipment 2 are blocked by the earth signal MSU at the terminal 32b. Consequently, the equipment 1 operates as a master and the equipment 2 operates as a slave.

The external pulse generator CLb or the signals generated by the poly-phase pulse generator 1 Ob are only used for monitoring purposes, for example for monitoring the temporal consistency of the pulse signals f" 4 > 2 generated by the piece of data processing equipment 1. For this purpose, counters 33b, 34b are provided in the piece of data processing equipment 2 which then generate an output signal Q1, Q2 or Q3, Q4 when predetermined counter condition regions are reached which are illustrated in the left-hand margin of Fig. 6.Moreover, the counter 33b is counted by the master signal < > 2* the counter 34b by the slave signal +2b. The output Q3 from the counter 34b is connected to the re-setting input R to the counter 33b. The outputs Q2 and Q4 are fed to an AND-gate 35 which is connected to an OR-gate 36 the further output from which is connected to the output Q1.

The outputs from the OR-gate 36 are preferably fed to terminals 1 6a and 1 6b which lead to synchronizing devices for the pieces of data processing equipment 1 and 2, not illustrated in Fig. 5. Through a flip-flop 37, the output from the OR-gate 36 controls an error signal output FS.

The method of operation of the apparatus illustrated in Fig. 5 will be described in the following with the aid of Fig. 6 in which are illustrated the counter conditions, the output signals derived therefrom as well as the error signal FS for the case of synchronization (Fig.

6a), of lag of the slave arrangement (Fig. 6b) and of lag of the master arrangement (Fig.

6c).

In Fig. 6a, the counter conditions then proceed equally due to the synchronization of the controllinng pulse signals. Since neither the signal Q4 nor the signal Q2 then appears, the AND-gate 35 remains blocked. Q2 then occurs as a first output signal and further maintains the AND-gate 35 blocked through the inverting input, even when 04 finally occurs. The signal Q3 then occurs next so that the counter 33b is re-set. This means that the condition Q1 is not reached in the counter 33b so that collectively the OR-gate 36 and the terminals 16a, 16b are not controlled.

The signal Q2 is then generated with a lagging slave according to Fig. 6b so that the AND-gate 35 is blocked. However, due to the lagging of the slave, the re-setting signal Q3 is generated so late in this case that the counter 33b first of all generates the signal Q1 which controls both the terminal 16b and the ORgate 36 so that an error signal FS is generated by the flip-flop 37.

Finally, in the case of Fig. 6c, the master is so slow that the signal Q4 exists at the slave counter 34d before the master signal Q2 is generated. However, this causes the AND-gate 35 to respond so that the terminal 16a and the OR-gate 36 are controlled which likewise results in the appearance of an error signal FS through the flip-flop 37.

Claims (13)

1. Apparatus for synchronizing pulse controlled data processing equipment (1, 2, 3) with which are associated respective external pulse generators (CLa, CLb, CLc) which are in operative association with internal poly-phase pulse generators (1 ova. 1 0b) which generate pulse signals (01at +2a; +1b (P2b) wherein one pulse signal (#2a) of one equipment (1) is monitored together with a pulse signal (552b) of another equipment (2) to provide synchronization, characterised in that, when the pulse signals (4)2at 2b) fall below a predetermined temporal deviation, the signal supplied to one of the pieces of data processing equipment (1, 2,3) by the associated pulse generator (CLa, CLb, CLc) is suppressed for at least one signal period.

2. Apparatus according to claim 1, characterised in that, the temporal synchronization with two pieces of data processing (1,2) is monitored respectively through a cross-over and the signal of that pulse generator (CLa, CLb) is suppressed which deviates in a predetermined direction with respect to time.

3. Apparatus according to claim 1, characterised in that, for monitoring the synchronization, the pulse signals (#2a, (P2b) are each fed to an exclusive OR-gate (14a, 14b) the output from which controls a synchronizing circuit (16a, 16b) for suppressing the signals from the pulse generators (CLa, CLb, CLc).

4. Apparatus according to claim 2 and 3, characterised in that, an AND-gate (15a, 15b) the further inverting input to which is connected to the pulse signal (tP2a, < t2b) of the respective piece of data processing equipment (1 ,2) is arranged beyond the respective exclusive OR-gate (1 4a, 1 4b) so that the signal of the pulse generator of the leading data processing equipment is suppressed.

5. Apparatus according to one of the preceding claims. characterised in that, the signals effecting the suppression of the signals of the pulse generators (CLa, CLb, CLc) are counted in at least one counter (1 9a, 1 9b) and indicating or alarm means are released on exceeding a predetermined limit value (cut).

6. Apparatus according to claim 5, characterised in that, the at least one counter (1 9a, 1 9b) is periodically re-set preferably by the overflow signal of a respective further counter (1 8a, 1 8b) influenced by the pulse signals (#a, 02b)-

7. Apparatus according to one of claims 3 to 6, characterised in that, the at least one counter (1 9a, 1 9b) is counted by the output signals from the particular exclusive OR-gate (14a, 14b).

8. Apparatus according to claim 1, characterised in that, two pieces of data processing equipment (1,2) are operated in a masterslave arrangement by external means (MSU) in that the respective outputs from a polyphase pulse generator (1 Ob) are separated and the outputs from the respective other poly-phase pulse generator (1 0a) are both fed to the pieces of data processing equipment (1, 2).

9. Apparatus according to claim 8, characterised in that, the outputs from the nonseparated (10a) and from the separated (lOb) poly-phase pulse generator are fed to a respective counter (34b, 33b) which generate output signals within defined ranges (Q1, Q2, Q3, Q4) of the counter conditions wherein the output signals are fed to the re-setting input to the respective other counter (33b) or to a logic circuit arrangement (35, 36) in such a manner that logic signals are generated when the deviation of the monitored pulse signals (ss2aZ (P2b) with respect to time is exceeded by more than a predetermined amount in one direction or the other.

10. Apparatus according to one of the preceding claims, characterised in that, the pieces of data processing equipment (1,2,3) are anti-locking systems of motor vehicles.

11. Apparatus for the synchronizing of pulse controlled data processing equipment substantially as herein described with reference to Fig. 1, Figs. 2 to 4 or Figs. 5 and 6 of the accompanying drawings.

12. An anti-locking braking system for a motor vehicle in association with apparatus as set forth in any preceding claim.

13. A motor vehicle provided with an antilocking braking system and apparatus according to any one of claims 1 to 11.