JPS5822429A - Clock switching circuit - Google Patents

Abstract

PURPOSE:To secure switching at a clock boundary and to perform succeeding recovery at a high speed, by detecting respective clock boundaries in a polyphase clock groups from its system or another system, and indicating the stop, switching, and transmission of the clock group stepwise adequately. CONSTITUTION:A clock group selecting circuit 340 selects the polyphase clock group of its system or another system to supply the clock group to the system. Then, detecting circuits 320 and 330 for clock boundaries of its system and another system detect clock boundaries in the clock groups of its system and another system to control the clock group selecting circuit 340 so that the stop, switching and transmission of the clock groups are performed stepwise. For the switching of the clocks, the detecting circuit 320 is started by using a switching indication starting circuit 310.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly to an improved clock switching circuit used for system control in a dual system K.

Conventionally, in this type of information processing equipment, a general (multi-phase) clock group has been adopted instead of a single-phase clock.In a highly reliable dual system, a duplexed clock group is used in case of a failure. With zero energization, the system is operated in this synchronous mode, which ensures high reliability.
During this operation, the entire system is controlled by one of the polyphase clover groups. Furthermore, due to the occurrence of a failure or the like, it is often necessary to switch to the other multiphase clock group. At this time, this type of clock switching circuit using a group of polyphase clocks does not guarantee switching at clock boundaries, which causes performance degradation, and has the disadvantage that it takes a long time to recover after system switching. .

The purpose of the present invention is to ensure switching at one block boundary by establishing switching at one clock boundary in this multiphase clock group, and to reduce the recovery time after four-way switching due to the occurrence of a failure, etc. It is an object of the present invention to provide a cross-circuit switching circuit that can be shortened and speeded up.

In order to achieve the above object, the present invention provides an information processing apparatus having a duplex configuration, in which the 51111I of the entire system is performed by a group of multiphase clocks from its own system or from another system,
In a clock switching circuit that switches between the own-system clock group and the other-system clock group, one of the own-system multiphase clock group and the other-system multiphase clock group is selected and the clock group is supplied to the system. The clock group selection circuit detects each clock boundary among the multiphase clock groups from the own system and the other system, and stops, switches, and sends the clock groups to the clock group selection circuit in a stepwise manner. The control system is configured to include a self-system clock boundary detection circuit, an other-system clock boundary detection circuit, and a switching instruction activation circuit that activates the self-system clock boundary detection circuit upon clock switching.

Hereinafter, the present invention will be explained based on embodiments shown in the drawings.

FIG. 1 is a block diagram conceptually showing clock group switching of an information processing apparatus having a duplex configuration to which the present invention is applied. An information processing device with a duplex configuration that ensures high reliability is normally operated in a synchronous mode. During this operation, two information processing devices (system a, system b)
Parallel processing is performed, and in order to compare and execute the results of both processes, the entire system is controlled by one of the duplexed good multiphase clock groups. .

The two duplexed information processing devices (System 1 and System B) each independently oscillate at 11,100 m.

100b, and the individual multiphase clock group generation circuits 200m, 200b connected thereto generate the multiphase clock groups 400m, 400 to be consumed within the system.
b.

It produces 500 m and 500 b. The clock switching circuits 300 m and 300 b switch the operating system clock groups 600 m and 600 b to the own system clock group 400 a.

400b or other tarok group 500m, 500
Select and supply either one of b. The clock switching circuits 300a and 300b correspond to the present invention.

Second! ! i1 is a block diagram showing the outline of the configuration of one embodiment of the clock switching circuit of the present invention, and FIG. 3 is a circuit diagram showing its details. In these figures, the clock switching circuit of the present invention includes a clock group selection circuit 340 that selects either the self-system multiphase clock group or the other-system multiphase clock group and supplies the clock group to the system; A self-system clock boundary detection circuit 320 serves as a control unit that controls the selection circuit 340.
, an other-system clock boundary detection circuit 330 , and a switching instruction activation circuit 310 .

Respective clocks generated by own system and other system #4
00 and 500 are connected to the clock selection circuit 340K11, and the four clocks selected by the clock group selection circuit 340 become the system clock group 600.

As shown in FIG. 3, the four-group selection circuit 340 includes an AND gate group 344 to which clock groups 410-44G of the own system are input, and a clock group 510-5 of the other system.
40, and an OR gate group 346 which calculates the logical sum of both the AND gate groups 344 and 345.

Both AND gate groups 344 and 345 each include a self-system clock boundary detection circuit 320 . A control signal for the other system clock boundary detection circuit 3300 is input. ANDGATE GROUP 34
4, the self-system clock boundary control signal 321 is applied to the first AND gate corresponding to the first phase clock 410, and the self-system clock boundary control signal 321 is applied to the other second AND gate group corresponding to the second and subsequent phase clocks 420 to 440K. The system clock boundary control signal 322 is
II! l! On the other hand, the AND gate group 345K sends the other system link boundary control signal 331 to the first phase gate 510K corresponding to the first phase gate 510K, and sends the other system link boundary control signal 331 to the first phase clock gate 510K. The other system clock boundary control signal 332 is connected to the other second group of ANDGs corresponding to 540K.

The self-system clock boundary detection circuit 320
Tube circuit 320e and D7 lip-flop circuit 320
d, and the outputs are connected to the 8 terminals and R terminals of the RS flip 70 tube l path 320C, respectively)
320 m, 320 b, and the above Ando Goo)
320b, and the Q output of the R8 flip 70 tube circuit 320C and the switching instruction activation signal 311 are ANDed.
320 f. This detection port 1132
Gtli, the R8 flip-flop circuit 320c is reset by the AND of the switching instruction start signal 311 and the own system clock 440, inputs its Q output to the D terminal of the p 7 flip-flop circuit, and inputs the Q output to the D terminal of the p7 flip-flop circuit. 440
It is reset by the logic @IK of the switching instruction start signal 311 or the other system clock boundary control signal 333, outputs the output as the own system clock boundary control signal 321, and further outputs the output of the %D71J block flop circuit a2odo7:1 as the own system clock boundary control signal 321. It is output as a system clock boundary control signal 322.

The other-system clock boundary detection circuit 330 includes D flip-flop circuits 330 m and 330 b.

The D flip-flop circuit 330a connects the self-system clock boundary control signal 323 output from the above-mentioned amplifier gate 320f to the D terminal, and connects the other-system clock boundary control signal 323 to the CK terminal.
and connect its Q output to the other system clock boundary control signal 3.
31 as well as the D flip-flop circuit 3.
Input it to the D terminal of 30b.

This D flip-flop circuit 330b has an external clock 510 connected to its CK terminal, and outputs its Q and 75 outputs as external clock boundary control signals 332 and 333, respectively.

When system control of clock group switching becomes necessary, this cross-circuit switching circuit starts switching control when the switching instruction activation signal 311 is sent from the switching instruction activation circuit 310 to the self-system cross-circuit boundary detection circuit 320.

Next, we will discuss the operation of the clock switching circuit according to the present invention in the fourth section.
This will be explained with reference to the time chart shown in FIG.

First, from the own system clock group 400 to the other system clock group 50
The operation of transitioning to 0 will be explained using the above figures and Figure 4. Clock group selection path: nO#i, current,
The self-system polyphase clock operates by selecting the groups 410 to 440. The own-system clock boundary detection circuit 320 activated by the switching instruction activation signal 311 monitors the own-system clock group 400 and starts searching for clock boundaries.

When the detection circuit 320Fi% clock boundary approaches, the self-system clock boundary control signal 321 is activated and the transmission of the self-system clock 410 is stopped. Here, in order to prevent a buzz at the time of switching, the clock group is divided into two stages, and in the first stage, the clock of the first phase stops outputting at the last phase in the same clock group.

Further, when the own-system clock boundary detection circuit 320 detects the own-system O clock boundary (indicated by a broken line in FIG. 4), it activates the own-system clock boundary control signal 322, and the strange own-system clocks 420 to 420 are activated. 440 O Stop sending. Here, as the iris 2 stage, the clocks from 2nd #1 onwards stop going out at the beginning of the first phase of the next clock group, that is, at the boundary with the previous clock group.

On the other hand, when approaching the own system clock boundary, the other system clock boundary detection circuit @330 is activated by the own system clock boundary control signal 323K. When the clock boundary of the other system approaches, the carcass detection circuit 330 activates the other system-clock boundary control signal 331 to enable sending of the other system's clock 510. Further, when detecting a clock boundary of the other system, the skeleton detection circuit 330 activates the other system clock boundary control signal 332 to enable transmission of the remaining clocks 520 to 54G of the other system.

In this manner, the switching from the self-system multiphase clock group 400 to the other-system multiphase clock group 500 is completed.

Next, the operation of transferring from the other system multiphase clock group 500 to the own system multiphase clock group 400 will be explained using FIG. 5. The clock group selection circuit 340 is currently operating by selecting other multiphase clock groups 510 to 540. Switching instruction activation signal 311 K: Therefore, the self-system clock boundary detection a1 time N320 activated first deactivates the control signal 323. As a result, the other system clock boundary detection circuit 11
330 starts to move, and the currently selected other system multiphase clock group 5
Start monitoring 00.・Other system clock boundary detection circuit 33
0Fi, when the other system's clock boundary approaches, the other system's clock boundary control signal 331 is inactivated to the clock group selection circuit 340 to
10 is stopped. Furthermore, when a clock boundary of the other system is detected, the other system clock boundary control signal 332 is inactivated for the clock group selection circuit 340K, thereby stopping the transmission of the remaining other system clock groups 520 to 540. At this time, the control signal 333 causes the local clock boundary detection circuit 320 to start operating again.

The starting optical self-system clock boundary detection circuit 320 starts monitoring the self-system multiphase clock group 400. Corpse detection circuit 32
0 enables the transmission of the own clock 410 by inactivating the own clock boundary control signal 321 for the clock group selection circuit 340K when the own clock boundary approaches. Furthermore, when one own-system clock boundary is detected, the own-system clock boundary control signal 322 is inactivated for the clock group selection circuit 340, thereby enabling the remaining own-system clock groups 420 to 440 to be sent.

With the above arrangement, the switching from the other system multiphase clock group 500 to the own system multiphase clock group 400 is completed.

As explained above, in order to establish switching at clock boundaries, the present invention detects each clock boundary from among multiphase clock groups from the own system and other systems, and sends the clock group selection circuit to the clock group selection circuit. By providing two types of clock boundary detection circuits that step-by-step and appropriately instruct the stopping, switching, and sending of clock groups, it is possible to guarantee switching at clock boundaries and speed up recovery after switching clock groups. There is a potential effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram conceptually showing clock group switching of an information processing device having a duplex configuration to which the present invention is applied;
811 is a block diagram showing the outline of the configuration of an embodiment of the clock switching circuit of the present invention, and FIG. 3 is a circuit diagram showing the details thereof.
4 and 5 are time charts for explaining the operation of the clock switching circuit of the present invention. 111%, 100b --- Oscillation source 200m, 200b --- Multiphase clock group generation circuit 30
0a, 300b...clock switching circuit 400.400
m, 400b ... Self-system multiphase clock group 5 (10,5
110;, 500b-...Other system polymorphic tarok group 6 (10
, 600m, 600b--System clock group 310
...Switching instruction activation circuit 311...Switching instruction activation signal 320... Own system clock boundary detection circuit 321.32
2,323... Own system clock boundary control signal 330...
・Other system cross border detection circuit 331.332.333・
・・Other system clock boundary control signal 340 ・・Clock group selection circuit 410 to 440 ・・Self system multiphase clock 510 to 540
...Other system multiphase clock applicant NEC Corporation Figure 1 Figure 2 Figure 3 157

Claims (1)

[Scope of Claims] An information processing device which has a duplex configuration and whose entire system is controlled by a multiphase clock group from its own system or another system, wherein In the clock switching circuit that performs switching, a clock group selection circuit selects either the own system multiphase clock group or the other system multiphase clock group and supplies the clock group to the system; Detects each clock boundary from the multiphase clock group, and causes the clock group selection circuit to stop or switch the clock group. The clock is configured to include a self-system clock boundary detection circuit and an other-system clock boundary detection circuit that control transmission in stages, and a clock switching (in this case, a switching instruction activation circuit that activates the self-system clock boundary detection circuit). A clock switching circuit characterized by: