JPS6017533A - Double buffer switching control - Google Patents

Double buffer switching control

Info

Publication number
JPS6017533A
JPS6017533A JP12409983A JP12409983A JPS6017533A JP S6017533 A JPS6017533 A JP S6017533A JP 12409983 A JP12409983 A JP 12409983A JP 12409983 A JP12409983 A JP 12409983A JP S6017533 A JPS6017533 A JP S6017533A
Authority
JP
Japan
Prior art keywords
tcff
data transfer
circuit
interruption signal
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12409983A
Inventor
Yasunori Tsukioka
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP12409983A priority Critical patent/JPS6017533A/en
Publication of JPS6017533A publication Critical patent/JPS6017533A/en
Application status is Pending legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16Multiplexed systems, i.e. using two or more similar devices that are alternately accessed for enqueue and dequeue operations, e.g. ping pong buffers

Abstract

PURPOSE:To simplify processing procedure and to shorten data transfer processing time by detecting the end of data transfer of a line buffer and providing a means, etc., which generate an interruption signal in accordance with the detected signal. CONSTITUTION:Detecting the end of data transfer of the line buffer, and the circuit, etc., which generate the interruption signal in accordance with the detection signal are provided. For example, when data transfer begins, data with prescribed length is inputted to the buffer 11A, simultaneously a transfer starting flip-flop TCFF 12A is set, and the other terminal counting flip-flop TCFF 13A, TCFF 13B and TSFF 12B are reset. Next, when the storing of the prescribed- length data is closed, the TCFF 13A is set to output ''1'', then the interruption signal IR with prescribed length through an AND circuit 15 generated the interruption signal IR is inputted to CPU through an OR circuit 18, and the processing is transferred from the main routine to the interruption routine.
JP12409983A 1983-07-09 1983-07-09 Double buffer switching control Pending JPS6017533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12409983A JPS6017533A (en) 1983-07-09 1983-07-09 Double buffer switching control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12409983A JPS6017533A (en) 1983-07-09 1983-07-09 Double buffer switching control

Publications (1)

Publication Number Publication Date
JPS6017533A true JPS6017533A (en) 1985-01-29

Family

ID=14876897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12409983A Pending JPS6017533A (en) 1983-07-09 1983-07-09 Double buffer switching control

Country Status (1)

Country Link
JP (1) JPS6017533A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6293728A (en) * 1985-10-18 1987-04-30 Fujitsu Ltd Fifo memory system
JPS62110798U (en) * 1985-12-27 1987-07-15
JPS6371766A (en) * 1986-09-12 1988-04-01 Fuji Facom Corp Buffer transferring system
JPS63107040U (en) * 1986-12-27 1988-07-11
JPS63175190A (en) * 1987-01-08 1988-07-19 Yokogawa Electric Corp Control apparatus of papermaking machine or coating machine
JPS63216156A (en) * 1987-03-05 1988-09-08 Fuji Electric Co Ltd Data communication system
JPH01315859A (en) * 1987-12-31 1989-12-20 Texas Instr Inc <Ti> Processor having communication interface
JPH02265340A (en) * 1989-04-05 1990-10-30 Mioji Tsumura Music information processing system

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6293728A (en) * 1985-10-18 1987-04-30 Fujitsu Ltd Fifo memory system
JPH0479011B2 (en) * 1985-10-18 1992-12-14 Fujitsu Ltd
JPS62110798U (en) * 1985-12-27 1987-07-15
JPS6371766A (en) * 1986-09-12 1988-04-01 Fuji Facom Corp Buffer transferring system
JPS63107040U (en) * 1986-12-27 1988-07-11
JPS63175190A (en) * 1987-01-08 1988-07-19 Yokogawa Electric Corp Control apparatus of papermaking machine or coating machine
JPS63216156A (en) * 1987-03-05 1988-09-08 Fuji Electric Co Ltd Data communication system
JPH01315859A (en) * 1987-12-31 1989-12-20 Texas Instr Inc <Ti> Processor having communication interface
JPH02265340A (en) * 1989-04-05 1990-10-30 Mioji Tsumura Music information processing system

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