JPS60110002A - Clock pulse synchronizing device for triple system - Google Patents

Abstract

PURPOSE:To prevent the evil effect of a division clock of a certain system to other systems with a clock pulse synchronizing device of a triple system, by breaking the input to majority circuit of a system having its shift larger than a prescribed degree. CONSTITUTION:A division clock dcp1 given from a dividing counter 1 which advances its counting action with impression of an original clock OCP1 of its own system is supplied to a majority circuit 2 together with division clocks dcp2 and dcp3 given from other two systems. A fault detecting circuit 4 detects the presence or absence of shift between the clock dcp1 of the own system and a majority clock mjcp and then delivers a fault detection signal dos1 when said shift is larger than a prescribed degree. A gate 5 breaks the input of the division clock to the circuit 2 by the signal dos1. In this way, the evil effect due to the disturbance of the division clock of a certain system to other systems is prevented.

Description

[Detailed Description of the Invention] This invention aims to synchronize the clock pulses of each prefecture (hereinafter referred to as ()1 ni [] tsuku 3゜l) in a triple system, and to synchronize the clock pulses of each prefecture to (J() for supplying clocks to the same 1111 device.

In the conventional triplex system (in the case of a failure of the synchronizing circuit of one system, the branching point D and link of that system deviates significantly from INI 11),
1-Rit, 11 on the majority decision of all systems.
This happened, and I was disappointed in the latter part of the discussion! (Biao Party) in some cases.

Fig. 1 shows an example in which the above-mentioned drawbacks of the conventional device are affected by a failure of the synchronous circuit in the third system, which has a negative effect on the majority clock. The divided clock, mjcp, is a majority clock, and indicates the occurrence of Sp less than 1. This invention compares the clock of each prefecture with the majority clock, and if the deviation is more than a specified value, By determining that the clock synchronization circuit of the system is faulty and determining whether the clock synchronization circuit of the system is faulty or not, the disturbance of the frequency-divided clock of one system can be detected. Be careful not to adversely affect other systems! The purpose is to:

Next, one embodiment of the present invention will be described based on the drawings from FIG. 2 onwards.

The prefectures A, B, and C that make up the three-handed system will be described later.
'r Clock synchronization circuits a and h with the same configuration.

C, and each circuit has a glue (not shown) provided for each system [
゛]The same frequency is required from the rack raw circuit.[)Tsuku0Cpt, OCI'+2.

0011, , is applied, 161 of J: reflock is applied to the same effect, and the majority decision of the same frequency []Tsuku Hjcρ1, m J C+12, Il
l, I CIT: Outputs +.

Therefore, here, the clock synchronization circuit a of the first system Δ will be representatively explained.

As shown in Figures 3 to 3, the clock synchronization circuit a is
Precera 1 which increments upon application of white original clock ocp to possible frequency division counter 1, frequency division clock dcp from this counter 1. Divided clocks from similar counters in the other two systems dcp , , dcp 3
The majority circuit 2 is manually operated with a certain gate line '1'b, and the majority circuit 2 is 70 ts dcp 1 for the white part.
A counter control circuit 3 that compares the majority clock mjcp from the output with respect to the precedence relationship of the output, determines whether the white system is a leading system, an intermediate system, or a delayed system, and controls the counter 1 according to the comparison result; white frequency divided clock dc
p, and the majority clock m j c p, detect the presence or absence of a deviation, if there is a deviation, measure the magnitude, and output a failure detection signal dos if the measured value is the specified value twin. Human power &[
Goo 1 which cuts off the input of the divided clock of the other system to the majority decision 11N circuit 2 by disconnecting or by a failure detection signal of the other system.
~Circuit 5.

In the above 17/, to explain the operation when there is no failure in the frequency dividing counter of any system, the original [I
When the frequency dividing counter 1 is incremented by the application of cp 1 and outputs the frequency divided clock dcpL, if the majority circuit 2 does not output the majority clock C1)1, that is, the second and third systems' division clock [ ] Tsuku C1cp 2. dcli
3 is not output (in this case, the first
A system is called a progressive system. ), the majority clock m j c +1 is outputted by the inverter 6 and the OR gate 7 constituting the counter control circuit 3; 1. Then, remove the minute l731 signal from either the 2nd or 3rd system [until the 1st tick is output, the increment of the counter 1 (from the Sa1!ru.

To this, the output of the rack IcITI is the same as the output of the rack IcITI, and the majority circuit 2 determines the majority.
j If Cl(l is output, that is, if either the second system or the third thread is outputting the minute IN evening own ivy before the output of the first system [-1 ivy) (The first system in this case is called the intermediate system.) (Well, the enable signal S1
When the input is continued, the counter continues counting by 1 (+1).

In addition, before the output of the first system's minute circuit "Itsuk+Icp 1, the divided clocks of the second and third systems are outputted, and the majority decision 1] rack jcIT+ is outputted. 41.7.=If In this case, the first system is called a delay system.) constitutes the counter control circuit 3, and when the AND condition is satisfied, it outputs the low 1 to signal S2, which is input to the counter 1. This n l'' (n number causes the counter to output the data S3 from the pre-seller 1 to the counter, and the counter outputs the minute rotation [1 ts dCρ1.

2nd system, 3rd system glue [1 piece 1611 1 circuit 1], C
Let us now describe the effects of the same four factors as mentioned above. ? ,Y knee)te,i,
11. Each frequency division counter is a 16 frequency division counter, q) The first system is a forward system, the second system is an intermediate system, and the third system is an iIi backward system. = l-, it becomes as shown in Figure 3, and since the enable signal S1 disappears due to the rising edge of the divided clock (IC11), the frequency division counter of the first system is in the next position after the value "8" from the number 1. The increment of is multiplied by 171 by j, which outputs the majority clock 2 based on the output of the divided clock dap2 of the second system, and the third
The frequency division counters of the systems are divided by the frequency division clocks dcp,+ of the first system and the second system.

Since the load signal S2 was output by the output of dcp 3, the data from BRILEF 1 was set and the process continued)
If the frequency division clock dcp3 should be output at the position indicated by the chain line, the frequency division clock dcp3 is forcibly output at the fall of the load signal s2.

The frequency division counter 1 of the first system is outputted from the frequency division clock of the second system by the original clock (J: J) after the re-enable signal S1 suddenly rises, and continues to be incremented by 41 again. In this way, the minute rotation of the three-handed system [1 tsuku (lcp, , dcl
[ko2, flcI] 31;l Synchronization is established, and the majority clock obtained in each prefecture is always the same clock for the same prefecture.

This invention adds the above-mentioned failure detection circuit 4, circuit 1 to circuit 1, to the conventional clock circuit 7y1 device in which the frequency dividing counter, majority circuit 2, and counter control circuit 3 are ) is added and becomes Δ.

Therefore, as described above, the detection circuit 4 detects the presence or absence of a deviation between the white frequency divided clock (lcp 1 and the majority clock mjcp), and uses the clock around the minute dcp, and It has an altruistic A gate 9 which receives the majority clock mjcp, and operates on the J, l, and shift detection signals to measure the human jaggedness of the other side, and the preset value becomes the specified value. The bar outputs a failure detection signal to the platform and has a counter 0.

This counter 0 receives the inverted signal of its output through the inverter 11, and outputs the logical product of the output signal from the output signal stations 1 to 9 of the output signal 1 to 9 as input through the gate 1. As a result, when there is a deviation between the divided clock dcp and the majority clock mjclT+, the original clock ocp given to the cell 1 while there is human power advances by J:, and the inverter 13 advances by J: Before the magnitude of the synchronization difference reaches the counter j treasure 11T1, the output of the divided clock dcp is multiplied by @'1. Rule 1] Tsuku mj
When synchronized with the output of c11+ (,1, the Richts I- signal is manually input to counter 19 via 14 to Antogame 1.

and set the difference between the mountain system clock and the majority clock to the specified value by 1. - (If the counter 10 detects a failure
flO3+ is output, and via the inverter 11, the above-mentioned Antoge-1 to 12.14 are closed, and the measured value of Force-Nonta is fixed. ~Close gate 15, cut off human power to the majority circuit of the frequency division clock of the mountain system, and also do the following in 11). 5.The detection signal dOS is sent to the gate circuit of the 1st synchronous circuit of another system, and the minute rotation from this thread [1st d
By closing the circuits 1 to 1 for inputting cp to the majority circuit of the other system, we can cut off the input of this frequency-divided clock dcp 1 to the majority circuit of the entire system.

Shiraito's circuit (1-1 clock input to the majority circuit) is determined to be a failure and the input to the majority circuit of the circuit is cut off. It can be determined by setting the counter value ゛η.For example, -J'4'l or 1-original 0''\'I
``If the time is more than I34, 1, ε0'j゛rel)゛1
When monitoring a triple clock circuit whose voltage is stepped down within the original clock pulse time, it is necessary to judge it as a failure when a deviation of 2-original clock pulse time or more occurs. The current setting of the counter 10 of the late llQ detection circuit 4 is set to ``3'', and the frequency division of the faulty system in lh, Shiraito, and other systems where the signal 1 of ``3'' is output from the counter is correct. The clock's majority power is cut off.

Also, is there a difference between the white frequency divided clock and the majority decision 1]?
If you want to monitor a tarot circuit that will not be repaired within 2.1 quintillion clock pulse times when the 2-way clock pulse time is -L, put +'+Q on the platform that has a deviation of 3-way clock pulse tie 11 or more. To determine a failure, set the counter value of the failure detection circuit to 4''.

Figure 15 shows that the deviation between the divided clock of 6 threads and the majority decision []tsuku is within 1 original clock pulse time.
Original clock, divided clock, and majority decision [n of 1:! The relationship between r and quantity is shown.

FIG. 6 does not show the relationship between the majority vote power, the output, and the counter value when the third system is an advanced system and the deviation is small and a failure is detected. When the counter value reaches '3', a failure detection signal is output, and the majority input of the third system is not continued as shown by the dotted line, but is cut off.

As described above, the clock synchronization device 6 according to the present invention is a failure detection circuit that outputs a failure detection signal when the difference between the divided clock of its own system and the majority clock reaches a specified value. , the late To? 1, the detection signal station is manually input to the majority circuit of the divided clock of the own system.
A circuit consisting of a circuit 1 and a circuit 1 which receives a detection code from another system and connects the input of a frequency-divided clock from the other system to the majority circuit. Since each prefecture is equipped with and 1′
11 and immediately shut off from the input of the majority circuit, thereby preventing disturbances in the circuits of one system from adversely affecting other systems.

[Brief explanation of the drawing]

FIG. 1 is a time chart 1 to explain the large fish of the conventional device. Figure 2 and below show examples of the present invention.
Figure 2 is a block diagram showing the triple tarok system, Figure 3
The figure shows a block diagram showing an example of the configuration of the first system clock synchronization circuit. 11-Time chart of each clock at all times-1~, Figure 6 is 1 because the 3rd system is
(?The time chart 1~ for the battle. △, B, C... System a, b, c... Clock same city j 1st road OCp ,~o
cp co... Harari [1 tsuku dcp 1- (lC(+
3...Divided clock dos, ~(los3...Failure detection signal 111j(11+ ~mjcp3+++Majority decision [1 twinoto...Divided counter 2...Majority circuit 3...Counter control 1O1 path 4...・Failure detection circuit 5...Goo 1~Circuit special 6'F Applicant 1] This signal stock meeting shi 11;'Z-1 Figure 1 Figure 2 Figure 4 Figure 5 Figure 5 0Cp11 l I I l 1 l l I I I
ocp2I l l I I 11111ocp311
11111jllll □,. , 1 ′ Figure 6

Claims (1)

[Claims] Each prefecture has a counter that divides the frequency of 1 quintillion clock pulses (1 quintillion clock pulses).
, compares the frequency division clock pulse outputted by the frequency division counter with the majority decision of the frequency division clock pulse of the gold thread, and controls the frequency division counter of its own system according to the comparison result. -C1 Each prefecture is provided with means for detecting and overturning the deviation between the white frequency division clock pulse and the majority vote clock pulse, and a means for detecting the deviation from the majority clock pulse, and a means for detecting the deviation. Measure the size by 61, h1
Mydriasis detection means 101, which outputs failure detection information when the measured value reaches a specified value; ntj frequency-divided clock pulses input to the majority circuit, and a gate that cuts off and covers the input of the frequency-divided clock pulses from the other system to the majority circuit, and the input of the frequency-divided clock pulses from the other system to the majority circuit, given as a disconnection signal. A clock pulse indicator device in a triple system, characterized in that it is equipped with a clock synchronization circuit comprising: a gate corresponding to each other system that interrupts the clock synchronization circuit;