GB2098931B - Methods of plasma etching microminiature devices - Google Patents
Methods of plasma etching microminiature devicesInfo
- Publication number
- GB2098931B GB2098931B GB8214402A GB8214402A GB2098931B GB 2098931 B GB2098931 B GB 2098931B GB 8214402 A GB8214402 A GB 8214402A GB 8214402 A GB8214402 A GB 8214402A GB 2098931 B GB2098931 B GB 2098931B
- Authority
- GB
- United Kingdom
- Prior art keywords
- methods
- plasma etching
- microminiature devices
- microminiature
- devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 title 1
- 238000001020 plasma etching Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US26643381A | 1981-05-22 | 1981-05-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
GB2098931A GB2098931A (en) | 1982-12-01 |
GB2098931B true GB2098931B (en) | 1985-02-06 |
Family
ID=23014579
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8214402A Expired GB2098931B (en) | 1981-05-22 | 1982-05-18 | Methods of plasma etching microminiature devices |
Country Status (8)
Country | Link |
---|---|
JP (1) | JPS57198633A (nl) |
BE (1) | BE893251A (nl) |
CA (1) | CA1202597A (nl) |
DE (1) | DE3219284A1 (nl) |
FR (1) | FR2506519B1 (nl) |
GB (1) | GB2098931B (nl) |
IT (1) | IT1151209B (nl) |
NL (1) | NL8202103A (nl) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3216823A1 (de) * | 1982-05-05 | 1983-11-10 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von strukturen von aus metallsilizid und polysilizium bestehenden doppelschichten auf integrierte halbleiterschaltungen enthaltenden substraten durch reaktives ionenaetzen |
US4414057A (en) * | 1982-12-03 | 1983-11-08 | Inmos Corporation | Anisotropic silicide etching process |
DE3315719A1 (de) * | 1983-04-29 | 1984-10-31 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von strukturen von aus metallsiliziden bzw. silizid-polysilizium bestehenden doppelschichten fuer integrierte halbleiterschaltungen durch reaktives ionenaetzen |
US4528066A (en) * | 1984-07-06 | 1985-07-09 | Ibm Corporation | Selective anisotropic reactive ion etching process for polysilicide composite structures |
NL8500771A (nl) * | 1985-03-18 | 1986-10-16 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij een op een laag siliciumoxide aanwezige dubbellaag - bestaande uit poly-si en een silicide - in een plasma wordt geetst. |
WO1987000345A1 (en) * | 1985-06-28 | 1987-01-15 | American Telephone & Telegraph Company | Procedure for fabricating devices involving dry etching |
DE4114741C2 (de) * | 1990-07-04 | 1998-11-12 | Mitsubishi Electric Corp | Verfahren zur Bildung einer Leiterbahn auf einem Halbleitersubstrat |
US6177337B1 (en) * | 1998-01-06 | 2001-01-23 | International Business Machines Corporation | Method of reducing metal voids in semiconductor device interconnection |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5519873A (en) * | 1978-07-28 | 1980-02-12 | Mitsubishi Electric Corp | Forming method of metallic layer pattern for semiconductor |
-
1982
- 1982-04-15 CA CA000401014A patent/CA1202597A/en not_active Expired
- 1982-05-18 GB GB8214402A patent/GB2098931B/en not_active Expired
- 1982-05-18 FR FR828208669A patent/FR2506519B1/fr not_active Expired
- 1982-05-19 BE BE0/208144A patent/BE893251A/fr not_active IP Right Cessation
- 1982-05-20 JP JP57084147A patent/JPS57198633A/ja active Pending
- 1982-05-21 NL NL8202103A patent/NL8202103A/nl not_active Application Discontinuation
- 1982-05-21 IT IT21430/82A patent/IT1151209B/it active
- 1982-05-22 DE DE19823219284 patent/DE3219284A1/de active Granted
Also Published As
Publication number | Publication date |
---|---|
FR2506519B1 (fr) | 1985-07-26 |
IT8221430A0 (it) | 1982-05-21 |
DE3219284A1 (de) | 1982-12-16 |
GB2098931A (en) | 1982-12-01 |
CA1202597A (en) | 1986-04-01 |
IT1151209B (it) | 1986-12-17 |
FR2506519A1 (fr) | 1982-11-26 |
JPS57198633A (en) | 1982-12-06 |
NL8202103A (nl) | 1982-12-16 |
DE3219284C2 (nl) | 1989-08-10 |
BE893251A (fr) | 1982-09-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20000518 |