GB2088103B - Memory control circuit - Google Patents

Memory control circuit

Info

Publication number
GB2088103B
GB2088103B GB8130756A GB8130756A GB2088103B GB 2088103 B GB2088103 B GB 2088103B GB 8130756 A GB8130756 A GB 8130756A GB 8130756 A GB8130756 A GB 8130756A GB 2088103 B GB2088103 B GB 2088103B
Authority
GB
United Kingdom
Prior art keywords
control circuit
memory control
memory
circuit
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB8130756A
Other versions
GB2088103A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Nippon Victor KK
Original Assignee
Victor Company of Japan Ltd
Nippon Victor KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd, Nippon Victor KK filed Critical Victor Company of Japan Ltd
Publication of GB2088103A publication Critical patent/GB2088103A/en
Application granted granted Critical
Publication of GB2088103B publication Critical patent/GB2088103B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/00007—Time or data compression or expansion
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10527—Audio or video recording; Data buffering arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/22—Signal processing not specific to the method of recording or reproducing; Circuits therefor for reducing distortions
    • G11B20/225—Signal processing not specific to the method of recording or reproducing; Circuits therefor for reducing distortions for reducing wow or flutter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10527—Audio or video recording; Data buffering arrangements
    • G11B2020/1062—Data buffering arrangements, e.g. recording or playback buffers
    • G11B2020/10675—Data buffering arrangements, e.g. recording or playback buffers aspects of buffer control
    • G11B2020/10694—Data buffering arrangements, e.g. recording or playback buffers aspects of buffer control output interface, i.e. the way data leave the buffer, e.g. by adjusting the clock rate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10527—Audio or video recording; Data buffering arrangements
    • G11B2020/1062—Data buffering arrangements, e.g. recording or playback buffers
    • G11B2020/10675—Data buffering arrangements, e.g. recording or playback buffers aspects of buffer control
    • G11B2020/10703—Data buffering arrangements, e.g. recording or playback buffers aspects of buffer control processing rate of the buffer, e.g. by accelerating the data output
GB8130756A 1980-10-13 1981-10-12 Memory control circuit Expired GB2088103B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55142755A JPS5766515A (en) 1980-10-13 1980-10-13 Memory address control system

Publications (2)

Publication Number Publication Date
GB2088103A GB2088103A (en) 1982-06-03
GB2088103B true GB2088103B (en) 1985-07-31

Family

ID=15322816

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8130756A Expired GB2088103B (en) 1980-10-13 1981-10-12 Memory control circuit

Country Status (4)

Country Link
JP (1) JPS5766515A (en)
DE (1) DE3140683C2 (en)
FR (1) FR2492149A1 (en)
GB (1) GB2088103B (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58205906A (en) * 1982-05-26 1983-12-01 Victor Co Of Japan Ltd Writing system to memory circuit
DE3345142C1 (en) * 1983-12-14 1985-02-14 Telefunken Fernseh Und Rundfunk Gmbh, 3000 Hannover Circuit for time compression or time expansion of a video signal
JPS60111556U (en) * 1983-12-29 1985-07-29 パイオニア株式会社 information reproducing device
US4675749A (en) * 1984-03-16 1987-06-23 Pioneer Electronic Corporation Disc player system with digital information demodulation operation
JPH0673225B2 (en) * 1984-11-06 1994-09-14 株式会社日立製作所 Time axis correction device in digital information reproducing device
JPH0632164B2 (en) * 1985-02-11 1994-04-27 アムペックス コーポレーシヨン Memory control circuit
JPH084340B2 (en) * 1985-08-07 1996-01-17 セイコーエプソン株式会社 Interface device
US5179692A (en) * 1985-08-07 1993-01-12 Seiko Epson Corporation Emulation device for driving a LCD with signals formatted for a CRT display
US4860246A (en) * 1985-08-07 1989-08-22 Seiko Epson Corporation Emulation device for driving a LCD with a CRT display
NL191249C (en) * 1985-09-12 1995-04-03 Pioneer Electronic Corp System for displaying digital information recorded on a record plate.
GB2199469A (en) * 1986-12-23 1988-07-06 Philips Electronic Associated Clock signal generator
GB2203616B (en) * 1987-04-01 1991-10-02 Digital Equipment Int Improvements in or relating to data communication systems
GB2229067A (en) * 1989-02-02 1990-09-12 Motorola Canada Ltd Retiming buffer for connecting binary data channels
GB2231981A (en) * 1989-04-27 1990-11-28 Stc Plc Memory read/write arrangement
JPH0352471A (en) * 1989-07-20 1991-03-06 Matsushita Electric Ind Co Ltd Specific reproducing device for video
US5323272A (en) * 1992-07-01 1994-06-21 Ampex Systems Corporation Time delay control for serial digital video interface audio receiver buffer
SG42830A1 (en) * 1993-08-14 1997-10-17 Toshiba Kk Disc data reproducing apparatus and signal processing circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3836891A (en) * 1973-07-05 1974-09-17 Bendix Corp Tape reader system with buffer memory
US4054921A (en) * 1975-05-19 1977-10-18 Sony Corporation Automatic time-base error correction system
JPS6052499B2 (en) * 1976-02-24 1985-11-19 ソニー株式会社 memory device
DE2639895C2 (en) * 1976-09-04 1983-06-16 Nixdorf Computer Ag, 4790 Paderborn Method for the transmission of information signals from an information memory in a data channel in data processing systems and device for carrying out the method
FR2383563A1 (en) * 1977-03-11 1978-10-06 Sony Corp Audio frequency signal recording on video - is performed as pulses using memory to modify repetition rate and has converter to provide serial data from parallel input

Also Published As

Publication number Publication date
DE3140683A1 (en) 1982-05-27
GB2088103A (en) 1982-06-03
FR2492149B1 (en) 1984-12-14
FR2492149A1 (en) 1982-04-16
DE3140683C2 (en) 1984-07-26
JPS5766515A (en) 1982-04-22
JPS628858B2 (en) 1987-02-25

Similar Documents

Publication Publication Date Title
JPS5710038A (en) Double stage control circuit
GB8300855D0 (en) Starting control circuit
DE3176673D1 (en) Memory security circuit
GB2082854B (en) Charge control circuit
GB2088103B (en) Memory control circuit
GB2133944B (en) Gain control circuit
DE3272734D1 (en) Control circuit
GB2080058B (en) Volume control circuit
GB2075729B (en) Microprogramm control circuit
DE3279896D1 (en) Memory circuit
GB2109652B (en) Memory circuit
DE3279521D1 (en) Memory circuit
DE3364541D1 (en) Control memory organization
GB2029147B (en) Memory control circuits
EP0060115A3 (en) Memory circuit
JPS5755595A (en) Circuit device for read-only memory
JPS57160103A (en) Control circuit
DE3072119D1 (en) Control circuit
GB2091962B (en) Volume control circuit
GB2067866B (en) Control interface circuit
DE3279996D1 (en) Memory circuit
JPS57105020A (en) Buss access control circuit
GB8310749D0 (en) Control circuit
JPS5752995A (en) Memory
GB8331806D0 (en) Control circuit

Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Effective date: 20011011