JPH0352471A - Specific reproducing device for video - Google Patents

Abstract

PURPOSE:To obtain an image without generating fluctuation on which interlace is applied by generating a readout address by delaying a vertical synchronizing signal for readout by a prescribed quantity when a vertical synchronizing signal for write is neighbored to the vertical synchronizing signal for readout. CONSTITUTION:The above device contains a memory 6, a reference synchronizing signal generation circuit 10, a readout address generation circuit 11, a delay control circuit 14, and a neighborhood detection circuit 15, and it is comprised in such a way that the vertical synchronizing signal for readout is delayed by the prescribed quantity when the vertical synchronizing signal for write is neighbored to the vertical synchronizing signal for readout within a prescribed range, and the vertical synchronizing for write always takes the precedence over the vertical synchronizing signal for readout. Therefore, no crossing in point of time of a write address and a readout address occurs even when a video signal is written on the memory 6 at every field. In such a way, it is possible to surely obtain the video signal interlaced as a read out video signal, and also, to obtain the image without generating the fluctuation as a reproducing image.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is suitable for video equipment such as video tape recorders and video disk players, and is suitable for special playback such as still image playback and slot/ropo playback using field memory. The present invention relates to a video special playback device that performs.

2. Description of the Related Art In video tape recorders, video disk players, and the like, when performing special playback such as still image playback and strobe playback, a memory for one field is usually used from the viewpoint of memory capacity. Such a special playback device for video signals using field memory can perform special playback by writing one field worth of video signals into the field memory and then reading out the video signals from this field memory at an appropriate timing. A method has been proposed (Japanese Unexamined Patent Publication No. 63-288588).

FIG. 5 is a block diagram showing the configuration of a conventional video special playback device. This conventional video special playback device has a configuration in which data is written into the field memory using a clock synchronized with the vertical synchronization signal of the input video signal, and then read from the field memory using the vertical synchronization signal created on the reading side. have.

A conventional video special playback device will be described below with reference to FIG.

In FIG. 5, 1 is an input terminal for a video signal, 2 is an output terminal for a video signal, 3 is an input terminal for a system clock, and 4 is an input terminal for a write permission signal instructing writing to the memory. 1, 5 is an analog/digital (A/D) converter that converts an analog video signal into a digital signal, 8 is a memory consisting of a random access memory (RAM), etc., and 7 is a memory that converts a digital video signal. Digital/L//Analog (D/A) to convert to analog signal
It is a converter. Furthermore, 8 is a synchronization separation circuit that separates the vertical synchronization signal in the composite video signal, 9 is a write address generation circuit that generates a write address to the memory 6, and 10
11 is a read address generation circuit that generates a read address to the memory 6; 12 is a reference synchronization signal generation circuit that generates a reference vertical synchronization signal during reading;
A selector 13 supplied to the address input terminal of the memory 6 is a timing generation circuit that generates a control signal necessary for operating the memory 6.

The operation of the conventional video special playback device configured as described above will be described below.

The video signal input from input terminal 1 is sent to A/D converter 6.
The vertical synchronization signal is input to the synchronization separation circuit 8, and the vertical synchronization signal is separated. The analog video signal input to the A/D converter 6 is converted into a digital μ video signal and sent to the memory 6. The write address generation circuit 9 generates a write address signal in synchronization with the vertical synchronization signal separated by the synchronization separation circuit 8 in response to the write enable signal input from the terminal 4. On the other hand, the read address generation circuit 11 generates a read address signal in synchronization with the read vertical synchronization signal generated by the reference synchronization signal generation circuit 10. The timing generation circuit 13 generates a control signal for the memory e, and outputs a write command signal button and a read command signal to the memory 6. The selector 12 switches and outputs the write address signal and the read address signal in synchronization with the write command signal button and the read command signal generated by the timing generation circuit 13, respectively, and writes and reads digital video signals to and from the memory 6. is possible. The digital p video signal read from the memory 6 is converted into an analog signal by the D/A converter 7 and output from the output terminal 2.

The video special playback device is configured as described above, and the video signal can be read out from the memory 6 with a new synchronization relationship independent of the synchronization relationship in the input video signal. 1. Writing to the memory 6 can be controlled in accordance with a write permission signal input to the input terminal 4, and a video signal with special effects such as still image playback or strobe playback is played back and output. .

Problems to be Solved by the Invention The above-mentioned conventional video special playback device writes data into a memory in synchronization with a vertical synchronization signal for writing separated from an input video signal, and then writes a new one for reading. It reads from memory in synchronization with a vertical synchronization signal, and its potential for use is extremely large.

However, if the vertical synchronization signal for writing to the memory and the vertical synchronization signal for reading intersect in time, the read video signal may be shifted forward or backward by one field. In particular, when writing to memory is performed field by field, if the above-mentioned vertical synchronization signal for writing and vertical synchronization signal for reading occur in time, the fino led of the read video signal may be an odd number. It may become fixed either in the feed trench or in the even field following it.

FIG. 6 is a waveform diagram showing the temporal intersection of the vertical synchronizing signal for writing and the vertical synchronizing signal for reading described above. The crossover of the two vertical synchronization signals mentioned above will be explained below using FIG.

First, the vertical synchronization signal for writing is separated from the video signal reproduced from the recording medium by a video tape recorder, video disk player, etc., and has some deviation in field units.

On the other hand, the vertical synchronization signal for reading is generated by a reference synchronization signal generation circuit, and is basically a jitter-free signal. When these vertical synchronization signals for writing and vertical synchronization signals for reading are close to each other as shown in FIG. is performed for each field, the displacement of the write address and the read address also causes a temporal crossover as shown in Figure 6C, and the video signal written in the memory is changed to the position shown in Figure 6D.
As shown in Fig. 6e, the video signal read out from the memory even though it has been written normally is read out with the odd number field fixed to the even number field, as shown in Fig. 6e. There is. When this video signal is displayed on a monitor, it is fixed to odd field 1 or even field, which causes problems such as incrementing not occurring or vertical fluctuations occurring on the screen.

The present invention solves the above-mentioned problem, and is intended to solve the above problems when a vertical synchronization signal separated from an input video signal and a vertical synchronization signal separately created for reading the video signal from the memory are close to each other or alternate in time. Another object of the present invention is to provide a special video reproduction device that can provide an interlaced video without fluctuation as a reproduced video signal.

In order to achieve the second object of "Means for Solving the Problems", the video special playback device of the present invention provides a video special playback device that provides a video special playback device that provides a video special playback device in which a vertical synchronization signal for writing and a vertical synchronization signal for reading are close to each other within a predetermined range. The vertical synchronization signal for reading is configured to be delayed by a predetermined amount,
The vertical sync signal B for writing is configured so that it always precedes the vertical sync signal for reading.With the above configuration, the vertical sync signal for writing always precedes the vertical sync signal for reading. By arranging and preceding each field, the write address and read address will not intersect in time even when the entire video signal is written in sequence for each field.

As a result, an interlaced video signal can be reliably obtained as a read video signal, and a reproduced image without fluctuation can be obtained.

Embodiment Hereinafter, a video special playback apparatus according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a video special playback device according to the present invention. In FIG. 1, 1 is an input terminal for a video signal, 2 is an output terminal for a video signal, 3 is an input terminal for a system clock, and 4 is an input terminal for a write permission signal that instructs writing to the memory. Further, 5 is an A/D converter that converts an analog video signal into a digital signal, 6 is a memory that can store video signals, such as a RAM, and 7 is a D/D converter that converts a digital video signal into an analog signal. A converter, 8 is a synchronization separation circuit that separates a vertical synchronization signal in a video signal, 9 is a write address generation circuit that generates a write address to the memory, and 10 is a standard that generates a vertical synchronization signal for reading. 11 is a read address generation circuit that generates a read address signal; 12 is a selector 7 that switches and outputs a write address signal and a read L7 address signal; 13 is necessary for operating the memory 6; This is a timing generation circuit that generates a conheror signal.The above structure is the same as the configuration shown in Figure 6.In Figure 1, 14 indicates the delay amount of the vertical M1 for reading. The control delay control circuit 16 is a proximity detection circuit that detects a state in which the write vertical synchronization signal and the read vertical synchronization signal are close to each other.

The operation of the video special playback apparatus according to the present invention configured as described above will be described below.

The video signal input to the input terminal 1 is sent to the A/D converter 6.
The vertical synchronization signal is input to the synchronization separation circuit 8, and the vertical synchronization signal is separated. The analog video signal input to the A/D converter 5 is converted to a digital p video signal,
It is sent to memory 6.

In the write address generation circuit 30, a write address signal synchronized with the write vertical synchronization signal separated by the synchronization separation circuit 20 is generated in response to the write permission signal input from the terminal 4.

In the reference synchronization signal generation circuit 10 , a vertical synchronization signal for reading that becomes a reference when reading from the memory 6 is created and sent to the delay control circuit 14 and the proximity detection circuit 16 . The proximity detection circuit 15 determines how close the vertical synchronization signal for writing separated by the synchronization separation circuit 8 is to the vertical synchronization signal for reading generated by the reference synchronization signal generation circuit 10 in terms of time. The delay control circuit 1 detects whether the read vertical synchronization signal is delayed by at least a predetermined period with respect to the write vertical synchronization signal.
A control signal is output to 4. In the delay control circuit 6o, the vertical synchronization signal for reading generated by the reference synchronization signal generation circuit 10 is delayed according to the detection result of the proximity detection circuit 15, and is sent to the read address generation circuit 11. The read address generation circuit 11 generates a read address in synchronization with this vertical synchronization signal for reading. The timing generation circuit 13 generates a control signal necessary for operating the memory 6, and sends a write command signal and a read command signal to the memory 6. The selector 12 switches the write address signal and the read address signal so that one of the address signals is output in synchronization with the write command signal and the read command signal generated by the timing generation circuit 13 as input. be done. In the memory 6, a video signal is written according to the write address signal from the selector 12 and the write command signal from the timing generation circuit 13, and the video signal is written according to the read address signal from the selector 12 and the read command signal from the timing generation circuit 13. is read out. The video signal read out from memory e is then sent to D.
The signal is converted into an analog video signal by the /A converter 7 and outputted from the output terminal 2.

Here, the delay control circuit 14 button and the proximity detection circuit 16 will be explained in detail. FIG. 2 is a block diagram showing detailed configurations of the delay control circuit 14 and the proximity detection circuit 16. In FIG. 2, 15 & is the synchronous separation circuit 8
an input terminal to which a write vertical synchronization signal separated by 1 is input; an input terminal to which a read vertical synchronization signal generated by the 1sb standard synchronization signal generation circuit 10 is input;
50 is an input terminal to which a write permission signal from the input terminal 4 is input, and 14a is an output terminal for outputting a vertical synchronizing signal for operating the read address generation circuit 11. Further, 16 and 17 are pulse width shaping circuits that shape the path width of the vertical synchronizing signal to a bus width of 1H for one horizontal scanning period;
1B is an exclusive OR circuit, 19 is a D-flip-flop circuit that latches the input signal, 20 is a delay circuit that delays the signal by one horizontal scanning period 1H, and 21 is a selector that switches and outputs two signals.

The operations of the delay control circuit and proximity detection circuit configured as described above will be described below with reference to FIGS. 2 and 3. In the following explanation, the pulse width control circuit 16.
The pulse width of the 17 output is 1H for 1 horizontal scanning period, the delay amount of the delay circuit 20 is 1H for 1 horizontal scanning period, and the input terminal 1
The description will be made assuming that the write permission signal from 5a is delayed by 0.5H by 0.5 horizontal scanning period from the leading edge of the write vertical synchronization signal. However, these widths and delay amounts are for convenience of explanation, and there is no need to set them to the above-mentioned values.

Now, the write vertical synchronizing signal inputted from the input terminal 15a is shaped by the pulse width control circuit 16, and becomes a signal a (hereinafter abbreviated as write V) having a width of one horizontal scanning period. Further, the vertical synchronizing signal for reading inputted from the input terminal 1sb is shaped by a bus width shaping circuit 17, and becomes a signal b (hereinafter abbreviated as lead V) having a width of one horizontal scanning period. Signal a and signal b are input to exclusive OR circuit 18,
The logic output signal C is latched by the write permission signal d in the D-flip-flop 19 and outputted as a control signal θ.

Here, 1st, the vertical synchronization signal for writing and the vertical synchronization signal for reading are 1. Figure 3 (a) shows the signal waveforms of each part when the distance is more than sH. As shown in FIG. 3(a), the signal a and the signal b are separated by more than 0.5H, and the output of the exclusive OR circuit 18 has the waveform shown in FIG. Further, in the D-flip-flop 19, a write permission signal d
Since the signal is latched by the 0 signal, a Hi level signal is output as the signal 0.

Therefore, the selector 21 selects the H1 side and outputs it to the output terminal 14a.

On the other hand, the write vertical synchronization signal and the read vertical synchronization signal are 0. FIG. 3(b) shows the signal waveforms of each part when the distance is within sH. At this time, in FIG. 3(b), the signal a and the signal b are close to each other within 0.5H, and the output of the exclusive OR circuit 18 has the waveform shown in FIG. 3C. Furthermore, in the D-flip flop 19, since it is latched by the write permission signal d, the signal 0 becomes Lo.
It becomes a level signal. Therefore, the selector 14a is Lo
The input address and read address on the side are shown in Figure 4 d.
According to the address displacement shown in , even if the write vertical synchronization signal contains jitter, the write address always precedes the read address, making it possible to avoid crossover. Therefore, even if a video signal is written field by field as shown in FIG. Ru.

Effects of the Invention According to the video special playback device of the present invention, it is possible to detect a state in which a vertical synchronizing signal for writing and a vertical synchronizing signal for reading are close to each other, and when they are close, the vertical synchronizing signal for reading is increased by a predetermined amount. By using a configuration in which the read address is generated with a delay, even when the vertical synchronization signal for writing and the vertical synchronization signal for reading are close to each other, the write address and read address cannot intersect in time. As a result, the video signal read from the memory is a normal interlaced video signal and is output to the output terminal 14a.

As a result of the above control, the vertical synchronization signal for writing and the vertical synchronization signal for reading are set to 0. If the distance is more than sH, the selector 21 selects the Hi side, and the vertical synchronization signal for reading is outputted to the output terminal 14a without delay, while the vertical synchronization signal for writing and the vertical synchronization signal for reading are output to the output terminal 14a without delay. Gashi o. If they are close within sH, the selector 21 selects the Lo side, and a vertical synchronizing signal for reading delayed by one horizontal scanning period 1H by the delay circuit 20 is output from the output terminal 14a.

FIG. 4 is a waveform diagram for explaining the operation when the write vertical synchronization signal and the read vertical synchronization signal are close to each other. Vertical synchronization signal for writing (Figure 4a)
When the readout vertical synchronization signal (FIG. 4b) is close to each other, the delay control circuit 14 and the proximity detection circuit 15 shown in FIG. It is delayed and output as a read address start pulse (FIG. 4C). At this time, it can be written, and its practical effect is great.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the video special playback device according to the present invention, and FIG. 2 is a detailed diagram of the delay control circuit and proximity detection circuit in the video special playback device of the present invention shown in FIG. A block diagram showing the configuration, Figure 3 (
b), fp) are waveform diagrams for explaining the operation of the circuit shown in Figure 2, Figure 4 is a waveform diagram for explaining the operation of the video special playback device shown in Figure 1, and Figure 6 is a waveform diagram for explaining the operation of the video special playback device shown in Figure 1.
FIG. 6 is a block diagram showing the configuration of a conventional video special playback device, and FIG. 6 is a waveform diagram for explaining the operation of the conventional video special playback device. 6...Memory, 8...Synchronization separation circuit,
10...Reference synchronization signal generation circuit, 11...
. . . Read address 1/s generation circuit, 14 . . . Delay control circuit, 16 . . . Proximity detection circuit.

Claims (1)

[Claims] a storage means having a storage capacity for at least one field capable of storing a composite video signal; a first signal generating means for generating a write start signal that is a reference when writing the composite video signal to the storage means; a second signal generating means for generating a read start signal serving as a reference when reading a composite video signal from the storage means; and a detecting means for detecting that the write start signal and the read start signal are temporally close to each other. and a delay means for delaying the read start signal by a predetermined amount based on detection power indicating that the write start signal and the read start signal are close in time, and a signal delayed by the delay means. A video special playback device, characterized in that the composite video signal is read out from the storage means using as a readout start signal.