JPH03139080A - System and device for reproducing high speed video signal - Google Patents

Abstract

PURPOSE:To normalize the connection of images in the vertical direction by interpolating or relinquishing a reproduced signal and writing it in a field memory, and reading it out by using a standard TV synchronizing signal at the time of switching an azimuth head at the time of reproducing at a high speed. CONSTITUTION:At the time of switching double azimuth heads 1a, 1b, 2a and 2b of different azimuths, which follows a tape track intersection at the time of reproducing at a high speed, in the case the switching direction of a head extends from the preceding head to the succeeding head, a reproducing signal of a line in which the order immediately after switching goes back is relinquished and not written in a field memory of a memory part 25. On the other hand, in the case switching of the head is executed from the succeeding head to the preceding head, the device is constituted so that the reproduced signal is interpolated and written in the field memory. Accordingly, at the time of reproducing at a high speed, almost the same number of lines as in the case of regular reproduction are written in the field memory. In such a way, the contents of the field memory are read out by a standard TV synchronizing signal, and even at the time of reproducing at a high speed, in which a screen size is not varied and whose connection in the vertical direction is normal is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed reproduction method for a magnetic recording and reproducing apparatus (hereinafter referred to as a VTR) and its apparatus.

[Conventional technology]

Conventional devices use bare heads with different azimuths, that is, double azimuth heads, as described in Jikai [64-7783], and during high-speed playback, these are switched in accordance with the recorded azimuth each time a track is crossed. The video signal is played back and stored in the field memory in synchronization with the played synchronization signal, and the stored information is read out using the standard TV synchronization signal as a reference, so that when the rotating head crosses the track, The horizontal screen distortion (skew) was removed.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, when high-speed reproduction is performed, the number of lines in one field increases or decreases. FIG. 6 shows the locus of the rotary head during high-speed reproduction. FIG. 6 shows the forward direction (FF
) The case of 3x speed playback is shown. During high-speed reproduction, the rotary head traverses tape tracks with different azimuths In-11 times (n is a double speed number, expressed as a positive number in the forward direction and a negative number in the reverse direction). A detailed view of the point at which the rotating head traverses the tape track is shown in Figure 7.8i. Figure 7 shows the 8th tape when the tape format is SP format.
The figure shows the case of EP format. Information for one horizontal line is written in one section in the figure, and the numbers in the figure indicate line numbers. The line number indicates the order of the line on the screen in one frame, and the l field is composed of lines with either odd or even line numbers. The arrow indicates the trajectory of the rotating head. There are two directions of head switching when traversing a tape track: one is from the leading head to the trailing head, and the other is vice versa. In FIGS. 7 and 8, (a) shows the former, and (b) shows the latter. Here, head switching is assumed to be asynchronous to the reproduced synchronization signal. Switching from the leading head to the trailing head when playing an SP formatted tape in the forward direction at high speed, that is, as shown in FIG. 7(a),
The reproducing head switches its trajectory from the end point of trajectory (2) to the starting point of trajectory (3). It is physically impossible to arrange both the leading and trailing heads at the same position, so in the present invention, the trailing head is two lines long (hereinafter the length of 1 life is referred to as H) relative to the leading head. It is assumed that the position is located at the rear. Therefore, the reproduction line moves to line m-1 of the adjacent track 2H behind line m. As a result, the number of lines in one field is two more lines than when scanning one field with one head. On the other hand, when switching from the trailing head to the leading head, ie, in FIG. 7(b), the number of lines in one field is two fewer lines than when scanning one field with one head. The two types of head switching occur alternately when crossing the tape track, and at odd-numbered speeds, head switching occurs an even number of times, so the number of lines in one field is limited to the number of lines in one field even when playing back with head switching. Even if it is played back, the number will be the same. When high-speed playback is performed using one head, the number of lines in one field is (n - 1) Decrease by the Φ line (however, n is a negative sign when playing in the reverse direction). Therefore, even when reproducing is performed by switching between two heads with different azimuths, the number of lines in the l field during n-times speed reproduction (where lnl is an odd number) is reduced by (n-1)α□ including the sign compared to normal reproduction.

When the number of lines in one field increases, only a limited number of lines out of all the lines can be viewed.
On the other hand, when the number of lines in one field decreases, the video becomes T
The image is projected only to a limited area above and below the V screen.

This is the first problem with the prior art.

The second problem with the prior art is that when the head is switched by crossing tracks, the order of the externally generated lines is reversed or jumped, the vertical connection of the image becomes abnormal, and the dimensions of objects in the image change. This is true.

When switching from the leading head to the trailing head, the order of the reproducing lines is reversed regardless of the tape format or the reproducing direction t. That is, when playing the SP format tape in the forward direction (FIG. 7, trajectory (2) → (3)), line (m-1) is played next to line (m) by head switching.
When reproducing in the reverse direction (trajectory (2)→(1) in FIG. 7), line (m-7) is reproduced next to line (m). A similar reversal of the order of playback lines occurs on EP format tapes (FIG. 8).

On the other hand, when switching from the trailing head to the leading head, a jump in the reproduction line occurs during forward reproduction, regardless of the tape format. That is, head switching during forward playback of an SP format tape (Fig. 7(b) trajectory (2)
→(3)), line (m) is followed by line (m+
7) is played and the forward playback of the BP format tape (
In the trajectory (2)→(3) in FIG. 8(b), line (m+5) is reproduced next to line (m).

If the order of the reproduced lines is reversed or jumps, the distance in the vertical direction cannot be accurately represented when projected on the screen.

The purpose of the present invention is to solve the above-mentioned problems of the prior art during high-speed playback, firstly, the problem of vertical expansion and contraction of the screen size, and secondly,
The purpose of this invention is to solve an abnormality in the vertical connection of images when switching heads when crossing a track.

[Means to solve the problem]

To achieve the above purpose, when switching between heads with different azimuths as they cross a tape track during high-speed playback, if the head switching direction is from the preceding head to the trailing head, the playback signal of the line whose order immediately after switching is reversed is If the head is switched to a leading head rather than a trailing head, the reproduced signal is interpolated and written to the field memory.

In addition, the difference between the number of interpolated lines and the number of discarded lines is 2αH during forward playback, and -2αH during reverse playback, so that the number of lines in one field is almost the same as in normal playback. They are set to be equal.

By roughly limiting the number of double speeds to an odd number, the number of lines in one field during high-speed playback is made to completely match the number during normal playback.

Alternatively, in order to achieve the above purpose, when the playback head crosses the tape track during high-speed playback, playback is performed using a head with a constant azimuth without head switching, and the playback signal is transmitted line by line in the playback direction. After interpolating and discarding a predetermined number of lines according to the data, the data is written into the field memory.

[Effect]

Double speed number n during high-speed playback is an odd number, but In-I+-21
, 1 is a positive integer, head switching between heads with different azimuths occurs an even number of times in one field when crossing the tape track, and head switching with different head switching directions occurs alternately, so that different heads The head switches in the switching direction can be regenerated the same number of times.

When switching from the leading head to the trailing head in the head switching described above, by not writing the playback signal of the line to be executed into the field memory, the part of the image information on the field memory corresponding to this head switching is Directional connections are maintained normally.

When switching the head from the trailing head to the leading head, image information of a predetermined number of lines is interpolated by some method and stored in the field memory, thereby eliminating vertical jumps in the image on the field memory.

Each time the above switching of both heads is performed, the number of lines written in the field memory is ±2αH relative to the number of reproduced lines.
During forward playback, when the number of lines increases (with a positive sign), and during odd-numbered double speed, both heads switching occurs t times each during the l field, as described above, so the overall increase in the number of lines written to the field memory relative to the number of playback lines is ±2tα
H, that is, ±1rl-11αH, which can offset the decrease in the number of reproduction lines due to high-speed reproduction.

On the other hand, even when the speed is an even number, the number of switching of either head increases only once, and the change in the number of reproduction lines due to high-speed reproduction can be compensated for by switching both heads for the same number of times as described above.

The change in the number of reproduced lines due to one remaining head switch is only a maximum of αH+2, which is constant regardless of the speed number, and is only a small amount compared to the total number of lines in the 1 field.

Therefore, during high-speed playback, approximately the same number of lines are written to the field memory as during normal playback.

As a result, by reading out the contents of the field memory using a standard TV synchronization signal, the screen size does not change even during high-speed playback, and even in the image part J that corresponds to head switching between different types of azimuth heads, the image It is possible to obtain a normal image of vertical connection.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram for realizing the high-speed playback method of the present invention. la, lb, 2a, 2b are heads, 3 is a magnetic tape, 4 is a rotating cylinder, 58.5b, 5c, 5d are amplifier circuits, 6 is an input terminal, 7°8 is a switching circuit, 10 is a synchronous separation circuit, 12, 13 is an envelope detection circuit;
14 is a switching circuit, 16 is an amplitude comparison circuit, 17 is a video signal processing circuit, 19 is a head switching direction discrimination circuit, 20 is a switching circuit, 21 is a write clock generation circuit, 22 is a write control circuit, and 1 is a read control circuit. , 24 is an analog/digital converter (A/D converter), 25 is a memory section,
26, 27, 28 are digital/analog converters (D
/A converter), 4 is an encoder, 30 is a mixing circuit,
31 is an input terminal, and 32 is an output terminal.

In FIG. 1, two sets of double azimuth heads ((1a, 1b)k and (2a, 2b) are mounted on the rotating cylinder 4.
) are arranged at an angular spacing of 180° from each other.

Head 1m, 7. b is +azimuth angle, 1b, 2a are
-It has an azimuth angle.

Two heads of a set of double azimuth heads are
One horizontal scan (hereinafter referred to as l) of the video signal on the tape
They are assumed to be located at a distance twice the length of the line (referred to as a line). The two discs are for reproducing magnetic tapes of different tape formats: la and 2a are for 5P7r-77), and lb and 2b are for BP format. The magnetic tape 3 is wound around the rotating cylinder 4 for an amount slightly longer than half its circumference.
The data is sent at a predetermined speed depending on the playback direction and playback speed. The signals reproduced by each head are sent to amplifier circuits 53 to 5.
In the switching circuit 7.8, the head switching signal 6 having a frequency of 39 Hz synchronized with the rotation of the rotary cylinder 4 is used to switch to the playback signal side of the head scanning the magnetic tape 3 at any time. The reproduction signals outputted from the switching circuits 7 and 8 are input to envelope detection circuits 12 and 13 and the switching circuit 14, respectively, and the envelope signals of the two reproduction signals are detected in the envelope detection circuits 12 and 13, Subsequently, the amplitude comparison circuit 16 determines a reproduced signal with a large amplitude, that is, a reproduced signal from a head having an optimum azimuth angle at that time. Based on the output of the amplitude comparison circuit 16, the switching circuit 14 selects the reproduced signal from the head having the optimum azimuth angle. Head switching by this selection is
Horizontal synchronization signal up to that point, that is, synchronization separation circuit 1
This is done in synchronization with the output H of 0. The output of the switching circuit 14 is
The signal is input to the video signal processing circuit 17, and normal reproduction video signal processing is performed. Furthermore, the color signal consists of two color difference signals R-
Y, B-YG are demodulated. The luminance signal Y is input to the synchronization separation circuit 10, where the horizontal synchronization signal H1 and the vertical synchronization signal V
is generated.

The horizontal synchronization signal H acts as a reset signal for the write clock generation circuit through the delay circuit 18, and outputs the generated write clock to the output (Y, R) of the video signal processing circuit 17.
-Y, B-Y) to have a constant phase relationship. Switching circuit 2 controlled by this built-in clock
0, the output of the video signal processing circuit 17 is converted into a dot sequential signal and then input to the A/D converter and digitized.

The write control circuit 22 has a write clock and a vertical synchronization circuit 9.
The memory line section is controlled by the vertical synchronization signal outputted from the input terminal 31, the reproduction direction discrimination signal inputted from the input terminal 31, and the head switching direction discrimination signal generated by the head switching direction discrimination circuit 19 from the output of the amplitude comparison circuit 16. Store the converted data.

Figure Wc2 is a detailed diagram of part of the memory section 25 and write control circuit 22. The memory section δ consists of a serial access memory (hereinafter referred to as line memory) with a memory capacity of one line, and a random access memory (hereinafter referred to as field memory) with a memory capacity of one field.
It is composed of

The output of the A/D converter 24 is sequentially input to the line memory, and data for one line is stored therein. The data stored in the line memory 33 is processed differently depending on whether there is head switching during the - line.

If head switching does not occur during input of one line of data to the line memory, the data in the line memory is transferred to the field memory indicated by the write address generation circuit 35 in the write control circuit during the following horizontal synchronization period. Forward to the address. After the data transfer, the scan address generation circuit 35 generates an address increased by one line, and resets the address to the address of the first line in response to the vertical synchronization signal.

If head switching occurs during one line, different processing is performed according to the playback direction, head switching direction, tape format (SP or EP). An example of this process is shown in FIG. Each process will be explained below.

Normal processing is the same processing as when head switching does not occur, and is processing in which the contents of the line memory are transferred to the address on the field memory indicated by the write address generation circuit, and then the value of the write address is increased by one line. be.

In the n-line insertion process (n=1, 2, 3), the contents of the current line memory are repeatedly transferred to the memory area of the subsequent n lines in the field memory, including the address indicated by the write address generation circuit. , the final write address is increased by n+1947 from before this process. N line ignoring processing (n=(,,~2.3)
is a process in which writing to the field memory is not performed for line n after head switching, and the write address does not change during this process.

FIG. 4 is an example of a block diagram of a write control circuit that performs the processing described above. The decoder 41 receives the outputs H8l and H8 of the head switching direction discrimination circuit 19 shown in FIG.
2. From the input signal 8PF indicating the tape format and the input signal FF indicating the playback direction, if n lines are inserted, H is output, otherwise output is YES. This controls the switching circuit 43 and switches the horizontal synchronizing signal H8YNC and the output T (, K) of the transfer lock generation circuit 40 as a signal for the clock of the addition counter 45. When n lines are inserted, data for n lives is switched. Since it is necessary to transfer ζ within the horizontal synchronization pulse, TCK is used, and at other times, H
Use 8YNC. FIG. 5 shows the phase relationship between TCK and H8YNC. TCK includes 3 or more pulses within the negative pulse period of H8YNC, and the pulse width is 1 of the memory used.
The output of the switching circuit 4 is inputted to the addition counter 45 via the delay circuit 50 and the buffer 46 with an output enable terminal, and the addition counter integrates this. The output of the buffer 46 is also input to a transfer signal generation circuit, and this circuit generates a transfer signal.

Next, the signal input to the enable 1 child of the buffer 46 will be explained.

First, the case of n-line insertion processing will be explained. H8
According to the values of I, H82, 8PF, and FF, the counter preset value circuit 42 generates a value of n to be preset in the subtraction counter 44, and presets it in the subtraction counter. In the case of n-line insertion, the decoder 41 controls the switching circuit 43 to select TCK as the clock necessary for the subtraction counter.

The subtraction counter output decrements its value for each clock input of TCK. The comparator 47 compares the output of the subtraction counter with O, and outputs a logic value H if they match, and outputs a logic value L if they do not match. In EO 9th w149, comparator 4
7 and the output of the decoder 41 (in the case of n-line insertion, this value is L) are input. TCK to subtraction counter ■
The output of the comparator 47 is L until n clocks are input.
Therefore, the output of the EOR circuit 49 becomes L, the buffer 46 becomes enabled, and the TCK becomes the buffer 4.
6, and is input to the transfer signal generation circuit 48 and addition counter 457, a transfer signal is generated, and the write address is increased by 1 line 7. When the (n+1)th clock pulse is input to the subtraction counter 44, the output of the subtraction counter becomes O, the output of the comparator 47 becomes H, the buffer 46 becomes disabled, and TCK is stopped there, so data transfer is also stopped. The increase in write addresses will also be temporarily suspended. A control signal is input from the comparator output so that the subtraction counter 44 also stops subtraction.

Next, a case where n lines are ignored will be explained.

The counter preset value circuit 42 sets the value of n in the subtraction counter as in the case of inserting the n line. Decoder 41
inputs the logic value H to the switching circuit 43 and the EOR circuit. Therefore, the subtraction counter 1 operates using the horizontal synchronizing signal H8YNC as a clock. For line n from head switching, the value of the subtraction counter I is non-zero, and the comparator 47
The output of is L.

Therefore, the EOR circuit 49 output becomes H, and the buffer 4
6 is a disabled state, and no transfer to memory is performed. Due to head switching, the output of the subtraction counter 44 becomes zero at the n+1th line, and the buffer 4
6 changes to the enabled state and transfer to the memory is performed. At this time, a control signal to stop counting is inputted to the subtraction counter from the comparator 47, and the enable state of the buffer 46 is maintained until the next head switching.

Finally, the case of normal processing will be explained. The counter preset value circuit sets a value of zero for the subtraction counter. The decoder 41 outputs H, and the horizontal synchronization signal HaYNC is input to the clock of the subtraction counter I. However, the subtraction counter outputs zero, and the comparator 47 inputs a control signal to stop counting. continues to output a value of zero. Therefore, the output of the comparator 47 is H,
Since the output of the decoder 41 is H, the buffer 46 continues to be enabled, a transfer signal is generated for each line, data is transferred from the line memory to the field memory, and the write address is increased by one line. As described above, the write control circuit shown in FIG. 4 stores the video signal in the field memory through each process shown in FIG.

By sequentially reading out the data stored in the field memory one line at a time using the reference vertical synchronization signal by the read control circuit 23, a video signal without vertical shape distortion can be obtained. Memory section 25
Since the output is a dot sequential signal, it is converted into parallel data to obtain a luminance signal Y1 and a color difference signal B-Y, R-Y.The encoder 29 modulates the two color difference signals to generate a color signal. This is mixed with the luminance signal, and a synchronization signal is added to obtain the final reproduced video signal.

With the above processing, the number of lines in one field during high-speed playback can be made almost the same as during normal playback, and the vertical connection of the output video signal can be maintained even when crossing the tape tracks of a double azimuth head that causes cloudy high-speed playback. can be maintained normally.

FIG. 9 is a block diagram of another embodiment of the invention. Parts corresponding to those in FIG. 1 are given the same reference numerals.

This embodiment is a reproduction method in which the reproduction head is not switched when the reproduction head crosses between tape tracks during high-speed reproduction. Therefore, during high-speed playback as well as during normal playback, the playback signals of the heads 1a and 2a are switched in the switching circuit 7 by a head switching signal of a frequency of 30 Hz synchronized with the rotation of the rotary cylinder 4 inputted from the input terminal 6. Switch.

In this embodiment, unlike the embodiment shown in FIG. 1, as described above, since heads with different azimuths in the double azimuth head are not switched during reproduction of one field, the envelope detection circuit 13 is unnecessary, and the amplitude comparison Circuit 16 also 2
Instead of comparing two envelope detection signals to detect when switching to a head with a different azimuth, the output of the envelope detection circuit 12 is compared with a threshold level that can be adjusted, and the reproduction signal is interpolated or discarded. Detect processing timing.

The output of the amplitude comparison circuit 16 is input to the write control circuit 22, and the write control circuit 22 uses this signal as a trigger to generate the reproduced signal in synchronization with the reproduced horizontal synchronization signal under the condition of the reproduction direction discrimination signal 31. The memory line section is controlled to perform interpolation and discard processing.

FIG. 10 shows an example of processing contents in each reproduction direction. In this example, interpolation, abandonment (10th
In the figure, only one of the processes (denoted as 2αH line insertion and 2α5 line ignored) is shown, but the difference between the number of interpolated lines and the number of discarded lines is ±2αI (positive sign during forward playback, backward playback). As an example, image processing may be performed at the same time so as to obtain a negative sign).

The process shown in FIG. 10 can be performed in the same manner as in the previous embodiment. However, in the block diagram showing an example of a part of the write control circuit 22 shown in FIG. 4, the head switching direction discrimination signals H8I and H82 to the decoder 41 and the counter preset circuit 42 are unnecessary.

The processing shown in this embodiment also allows the number of lines in one field during high-speed playback to be the same as during normal playback, and the output video signal is The vertical connection can be maintained normally.

〔Effect of the invention〕

According to the present invention, when switching the azimuth head during high-speed playback, the playback signal is interpolated, discarded, written into the field memory, and read out using a standard TV synchronization signal, so that the number of lines in the l field can be reduced. It can be made almost the same as during normal playback, the screen dimensions are the same as during normal playback, and a video signal with normal vertical video connection, that is, no distortion in the vertical direction, can be output, so it can be used during high-speed playback. Not only the content of the reproduced image, but also the dimensions of the objects in it,
It has the effect of being able to grasp even the shape.

In particular, by limiting the number of double speeds during high-speed reproduction to an odd number (thereby, the number of lines in one field can always be kept the same as during normal reproduction).

[Brief explanation of the drawing]

FIG. 1 is an overall block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a part of the memory section 5 and write control circuit of FIG. 1, and FIG. FIG. 4 is a detailed block diagram of the write address generation circuit of FIG. 2, FIG. 5 is a diagram showing the phase relationship between the horizontal synchronization signal and transfer lock, and FIG. 6 is a diagram showing the processing method for head switching. A diagram showing a tape pattern of a magnetic tape and a head trajectory during triple-speed playback. FIGS. 7 and 8 are both diagrams showing playback head trajectories when switching between conventional heads. FIG. FIG. 10 is a block diagram of the embodiment, and is a diagram showing an example of processing contents in each reproduction direction. (la, lb), (2a, 2b) - Double azimuth head 7.8... Switching circuit 12, 13... Envelope detection times %14... Switching circuit 16... Amplitude comparator 17. ...Video signal processing circuit 10...Synchronization separation circuit 19...Head switching direction discrimination circuit 22...Write control circuit 23...Read control circuit 24...A/D converter 25...Memory Part 2 figure 5 figure 10 figure i6 figure 44 figure ¥i5 figure (1) Leading line - h trailing line Cb) A moxibustion A1 → Missing line 1

Claims (1)

[Claims] 1. In a magnetic recording and reproducing device having a double azimuth head and a field memory, when the double azimuth head crosses a tape track during high-speed reproduction, the double azimuth head is switched according to the azimuth of the tape track. If the above switching is performed, the reproduced signal is discarded or interpolated by a predetermined number of lines in accordance with the switching direction, and if the above switching is not performed, the reproduced signal is directly reproduced. The high-speed method is characterized in that the reproduction signal is written into a field memory using a standard TV synchronization signal as a reference, and after the writing, the playback signal is read from the field memory using a standard TV synchronization signal as a reference, and the read signal is used as an output signal. Video signal reproduction method. 2. The above request that the difference between the number of lines to be discarded and the number of lines to be interpolated be 2α_H (α_H is the deviation of the line start point between adjacent tracks on the tape) during forward playback, and -2α_H during reverse playback. The high-speed video signal reproduction method according to item 1. 3. The high-speed video signal reproducing system according to claim 1 or 2, wherein the speed ratio is an odd number. 4. means for switching the double azimuth head in accordance with the azimuth of the recorded tape track in a magnetic recording and reproducing device capable of high-speed reproduction having a double azimuth head and a field memory; means for performing discard or interpolation processing on a line-by-line basis; means for writing the processed video signal into a field memory in synchronization with a reproduction synchronization signal; and means for reading out the contents of the field memory with reference to a standard TV synchronization signal. A high-speed video signal reproducing device characterized by having: 5. In high-speed reproduction of a magnetic recording/reproduction device having a field memory, reproduction is performed using a reproduction head having a constant azimuth while reproducing one field, and when the head crosses a tape track recorded with an azimuth different from that of the head. , performs interpolation and discard processing on the reproduced signal for a predetermined number of lines according to the reproduction direction line by line, and writes the processed reproduced signal into a field memory with reference to the reproduced synchronization signal;
After the writing, the reproduction signal is read from the field memory using a standard TV synchronization signal as a reference, and the read signal is used as an output signal. 6. The difference between the number of lines to be interpolated and the number of lines to be discarded is 2α_H during forward playback and - during reverse playback.
6. The high-speed video signal reproducing method according to claim 5, wherein 2α_H.