JPH01147979A - Video signal processor - Google Patents

Abstract

PURPOSE:To eliminate the discontinuity of a pattern at skewless search by writing a video signal in a main memory via a buffer memory at write of a video signal and reading a data of an optional address from the main memory at readout. CONSTITUTION:A write control circuit 42, based on a rotation phase signal, counts a field number of a reproducing signal and writes the signal via the buffer memory 21, in a main memory 22 intermittently for each optional field. At readout, the signal is read continuously from the main memory 22. Thus, the field signal stored in the main memory 22 is read repetitively in the field not writing any signal. Thus, even with a fast search speed at high speed reproduction, since the picture is visible longer for each one scene, the content is surely grasped and the visual stability is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to digital signal processing technology, and particularly to a video signal processing device suitable for digitally processing video signals.

(Prior Art) As a video signal processing device, for example, there are proposals such as a zoom function for enlarging a video signal, a mirror function for reversing the left and right sides, etc.As a known technology related to these, Japanese Patent Laid-Open No. 6
2-29297, JP-A-62-64189, and the like. Also, as a known technology regarding skewless search.

Caliber Electronics October 20, 1986 No.

406, pages 195 to 209, including a paper entitled "Home VTRJ with Built-in Field Memory to Improve Noise Bars and Skew Distortion in Search Mode."

[Problems to be Solved by the Invention] The conventional technology related to the zoom function and mirror inversion function described above is a composite signal processing technology, and the technology is characterized by the way color burst signals are handled.

Composite signal processing has the problem that sufficient image quality cannot be obtained because the luminance signal and color signal are processed simultaneously.

Further, regarding the skewless search, in the above-mentioned conventional technology, noise removal is performed by combining images of different fields, so there is a problem that the results vary greatly in moving images.

An object of the present invention is to provide a video signal processing device that performs component signal processing on a video signal and uses memory in a method suitable for various functions. The video signal processing device according to the present invention realizes functions such as skewless search, mirror inversion, and zooming.

[Means for solving problems]

The above purpose uses a memory consisting of a buffer memory of one line memory and a main memory having a memory capacity of at least multiple lines, and when writing a video signal, it writes to the main memory via the buffer memory, and when reading it,
This is achieved by reading data at an arbitrary address from the main memory.

[For production]

By using a 1-line buffer memory, data can be transferred to the main memory line by line.
Discontinuities in skew benefits can be replaced in the previous line.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows an embodiment in which the present invention is applied to a skewless playback function in a high-speed playback mode of a magnetic recording/playback device. In this embodiment, a helical scan type magnetic recording/reproducing apparatus performs azimuth recording, and at least one of the opposing magnetic heads.

It is assumed that the head has a double azimuth head configuration with heads at both azimuth angles.

In FIG. 1, 1 is an input terminal for a reproduced video signal, 2 is an output terminal, 3 is an input terminal for a stable lock signal, 4 is an input terminal for a double azimuth head (not shown) switching signal,
10 is a Y/C separation circuit that separates the luminance signal Y and color signal C; 11 is a decoder circuit that converts the color signal C into two color difference signals R-Y and B-Y; and 12 is a luminance signal Y and color difference signal R. −
20 is a memory, 21 is a buffer memory with a memory capacity of at least one line of video signal, 22 is a main memory with a memory capacity of multiple lines, 3° is a D/A conversion circuit, 31 is an encoder circuit that converts the color difference signals R-Y', B-Y'' into color signals C', and 32 is a luminance signal Y' and a color signal C.
40 is a synchronization signal dividing circuit, 41 is a write clock generation circuit, 42 is a write control circuit, 43 is a read control circuit, and 44 is a reference synchronization signal generation circuit.

A high-speed reproduction video signal inputted from terminal 1 is inputted to Y/C separation circuit 10 and synchronous separation circuit 40.

The Y/C separation circuit 10 separates the luminance signal Y and the color signal C, and the decoder circuit 11 further decomposes the color signal C into two color difference signals RY and BY. Each signal is input to the A/D conversion circuit 12 and converted into a digital signal.

On the other hand, the synchronization separation circuit 40 separates the synchronization signal.

The write clock generation circuit 41 generates a clock signal that is instantaneously phase-synchronized with the separated horizontal synchronization signal. Using this write clock signal, the A/D conversion circuit 12 performs sampling. Furthermore, the write clock signal is input to the write control circuit 42, which controls writing of the A/D converted digital video signal to the memory 20.

FIG. 2 is a waveform diagram for explaining the principle of skew correction. FIG. 2(1) shows the envelope of a high frequency signal reproduced by a double azimuth head.

When the signal levels reproduced by each head of the double azimuth head become equal, the double azimuth head is switched to obtain a continuous signal. At this time, at the head switching section,
Skew distortion occurs because the signal becomes discontinuous.

Figure 2 (2) shows how the reproduced high frequency signal is demodulated and Y/
This is the waveform of the luminance signal Y obtained by separating C. Indicates that the video signal is discontinuous at the head switching section.

FIG. 2(3) shows the horizontal synchronization signal separated by the synchronization separation circuit 40. Figure 2 (4) shows a write clock generation circuit 4 that starts oscillation in instantaneous phase synchronization with the horizontal synchronization signal.
1 output signal is shown. Using this write clock signal, the A/D converter 12 outputs the luminance signal Y9 color difference RY, B.
−Y is sampled and written to memory 20.

Since the write clock is generated by starting oscillation in phase synchronization with the horizontal synchronization signal, sampling data at a predetermined position relative to the horizontal synchronization signal can be stored at a predetermined address position in the memory 20. At this time.

It is assumed that the memory 20 consists of a buffer memory 21 having a memory capacity of at least one line and a buffer memory having a memory capacity of at least several lines. The A/D converted sampling data is written to the buffer memory 21 line by line, and is written to the main memory 22 line by line.
Transfer to.

Reading from the memory 20 is performed based on a stable read clock signal input from the terminal 3.

The read clock is input to a reference synchronization signal generation circuit 44 and a read control circuit 43 to control reading from the memory 20. The signal read from the memory 20 is input to the D/A conversion circuit 30 and converted into an analog luminance signal Y and two color difference signals R-Y'B-Y'. Color difference signal R-
Y", B-Y' are input to the encoder 31 and modulated to obtain the color signal C'.Furthermore, the luminance signal Y' and the color signal C' are input to the mixing circuit 32, and after being mixed, the terminal 2
It is output as a video signal with more skew correction.

FIG. 2(5) shows the reference horizontal synchronization signal generated by the reference synchronization signal generation circuit 44 from the read clock.

The reference horizontal synchronization signal is a signal at regular intervals, and by reading the signal from the memory 20 based on this, discontinuity in the synchronization signal can be eliminated and skew distortion can be removed.

FIG. 2 (6) shows that the video signal read out in this way is
A waveform with synchronization information added by the mixer 32 is shown.

Skew distortion can be removed as described above, but
In the waveform diagram shown in FIG. 2(6), the discontinuity of the picture that occurs at the head switching portion remains. In order to eliminate this discontinuity, immediately after head switching, the data is replaced with the data of the previous line. FIG. 2 (7) shows a waveform diagram in the replaced state. As a result, skew correction without pattern discontinuity can be realized with minimal signal replacement.

The pattern replacement can be realized as in the embodiment shown in FIG. A head switching signal inputted from the terminal 4 is inputted to the write control circuit 42. Figure 3 shows the buffer memory 21
FIG. If the head cannot be switched, data is sequentially written as shown in FIG. 3(1). In FIG. 3, data nm indicates the m-th sampling data of the n line. Figure 3 (2
), when the head is switched immediately after sampling data 22, the write control circuit 42 stops writing data to the buffer memory 21. Therefore, the data of the previous line remains in the buffer memory 21. Therefore, by transferring the data in the buffer memory 21 shown in FIG. 3(2) to the main memory 22, the data in the previous line is replaced.

In the next line, data is sequentially written into the buffer memory 21 as shown in FIG. 3(3). However, if the playback horizontal sync signal is not detected on the next line,
Furthermore, writing of data to the buffer memory 21 is prohibited. Then, as shown in FIG. 3(3)', the same data is transferred to the main memory 22 again. This corresponds to the processing of dropouts where signals are missing, but this is particularly likely to occur near the head switching section where the level of the reproduced signal decreases, and interpolation can be easily performed in this case as well.

The memory 20 may be composed of a line memory, a plurality of line memories, a field memory, etc.
Alternatively, for example, HM53461 manufactured by Hitachi, which is called a dual port memory, can be used.

According to the present invention, pattern discontinuity can be realized with a minimum of signal replacement, and skew correction can be realized without deteriorating image quality.

Next, another embodiment of the present invention will be described. In Figure 1,
100 is an input terminal for a signal indicating the rotational phase of the cylinder. The rotational phase signal is input to the write control circuit 42 as shown by the dotted line. In this embodiment, the main memory 22 is assumed to have a storage capacity sufficient to write field signals.

The write control circuit 42 counts the number of fields of the reproduced signal based on the rotational phase signal, and intermittently writes the signal to the main memory 22 via the buffer memory 21 for each arbitrary field.

During reading, signals are continuously read from the main memory 22. Therefore, in fields where no signals are written, the field signals stored in the main memory 22 are read out repeatedly.

When the search speed due to high-speed playback is high, the movement of the pictures is too rapid, not only is there no sense of stability, but it is also difficult to grasp the contents. In this example, each scene can be viewed for a long time, so the content can be grasped with certainty, and there is also a sense of visual stability.

FIG. 4 shows an example of a memory map when the main memory 22 is a field memory. Write each line's data in each row. In the example shown in FIG. 4, it is assumed that one field consists of n lines, and each line consists of data of m samples.

If you have a field memory as the main memory 22,
Various functions can be realized with the configuration shown in Part 1.

By writing in the memory map shown in FIG. 4 and reading data in the opposite direction for each row when reading, a mirror reversal function can be realized in which the left and right sides are reversed. In addition, by repeatedly reading out the horizontal data twice each time like 13.13, 14.14, etc., and then reading each line twice each time, a zoom function that doubles vertically and horizontally is realized. be able to.

FIG. 5 is a diagram showing an example of an enlarged position of the zoom function. FIG. 5(1) shows the video signal before enlargement.

Generally, significant information exists near the center of the screen.

When various TV programs and video software are statistically handled, human faces are located slightly above the center of the screen. Therefore, when enlarging the fixed position, 25±
If the image is expanded around the 15th line, most of the necessary video signal can be seen as shown in FIG. 5(2).

〔Effect of the invention〕

According to the present invention, since a video signal can be written line by line and read out data by line, it is possible to eliminate discontinuity of a picture during a skewless search, and skew distortion can be eliminated.

Furthermore, since the main memory is a field memory and video signals can be written intermittently field by field, pictures can be stably read out during a search.

Furthermore, when using the fixed position, double vertical and horizontal magnification function, most of the necessary video can be viewed by enlarging the screen centered on 25±15 lines from the center of the original screen.

[Brief Description of the Drawings] Figure 1 is a block diagram showing an embodiment of the present invention, Figure 2 is a waveform diagram for explaining skewless search, Figure 3 is an address diagram for explaining line memory, and Figure 4 is a diagram for explaining line memory. The memory map diagram, FIG. 5, is an explanatory diagram of the zoom function. 12...A/D converter, 20...memory, 21...
・Buffer memory, 22...Main memory, 41...
-Write clock generation circuit, 42...Write control circuit. 43...read control circuit. ! 4) 4 lines 4/42 4344-45
・・4 key et al. 4-

Claims (1)

[Scope of Claims] 1. At least one of the opposing magnetic heads that write and read video signals on the magnetic tape is composed of a double azimuth head having both azimuth angles, and the side of the double azimuth head with a higher reproduction output level during high-speed reproduction. In a helical scan type magnetic recording and reproducing apparatus having a double azimuth head switching means for switching to a head output signal, the apparatus further comprises means for separating a horizontal synchronization signal from the video signal, and means for generating a write clock signal phase-synchronized with the horizontal synchronization signal. a means for AD converting the video signal based on the write clock signal; a line memory having a capacity for storing at least one line of the digital video signal output from the AD conversion means; A main memory having a capacity to store signals of a plurality of lines, means for transferring the stored contents of the line memory to the main memory, means for writing and controlling the digital video signal to the line memory, and a stable clock signal. It has a means for reading and controlling the digital signal from the main memory, and a means for DA converting the read digital video signal, and immediately after the head is switched by the writing means, the next reproduced horizontal synchronization signal is separated and output. A video signal processing device characterized in that write control is performed so as to stop writing of the video signal into the line memory until the head is switched, and immediately after head switching, the video signal is replaced with the signal of the previous line. 2. The main memory has a storage capacity of one field or more of the digital video signal, and has means for inputting a field period signal to the write control means, and intermittently writes the digital video signal for each field based on the field period signal. 2. The video signal processing device according to claim 1, wherein a video signal is written into said line memory, and said digital video signal is continuously read out from said main memory by said readout control means.