JPH0832020B2 - Video signal processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing technique, and more particularly to a video signal processing device suitable for digitally processing a video signal.

[Conventional technology]

As a video signal processing device, for example, there is a proposal such as a zoom function for enlarging a video signal and a mirror function for inverting left and right. Known techniques related to these are disclosed in
62-29297, JP-A-62-64189, and the like. Further, as a publicly known technique related to the skewless search, there is a method of day diameter electronics, October 20, 1986, No. 406, 195th.
From page to page 209, there is a paper entitled "Home VTR with Built-in Field Memory to Improve Noise Bar and Skew Distortion in Search Mode".

[Problems to be solved by the invention]

The conventional technology relating to the zoom function and the mirror inversion mechanism described above is a technology for processing a composite signal, and the technology is characterized in how to handle a color burst signal. In the composite signal processing, since the luminance signal and the color signal are processed at the same time, there is a problem that the image quality cannot be sufficiently obtained.

Further, regarding the skewless search, in the above-mentioned conventional technique, noises are removed by combining images of different fields, so that there is a problem that a pattern is largely shifted in a moving image.

It is an object of the present invention to provide a video signal processing device that uses a memory in a method suitable for various functions by processing a video signal as a component signal. The video signal processing device according to the present invention realizes skewless search, mirror inversion, zoom function and the like.

[Means for solving problems]

The above purpose uses a memory composed of a buffer memory of 1 line memory and a main memory having a memory capacity of at least a plurality of lines. When writing a video signal, the main memory is written to and read from the main memory via the buffer memory. This is achieved by reading data at any address.

[Action]

By using the buffer memory of one line, the data can be transferred to the main memory line by line, and the discontinuity of the pattern of the skew can be replaced by the previous line.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. FIG. 1 shows an embodiment in which the present invention is applied to a skewless reproducing function in a high speed reproducing mode of a magnetic recording / reproducing apparatus. In this embodiment, a helical scan type magnetic recording / reproducing apparatus for azimuth recording is used, and at least one of the opposing magnetic heads has a double azimuth head structure having heads of both azimuth angles.

In FIG. 1, 1 is an input terminal for a reproduced video signal, 2 is an output terminal, 3 is an input terminal for a stable clock signal, 4 is an input terminal for a switching signal of a double azimuth head (not shown), and 10 is a luminance signal. Y / C separation circuit for separating Y and color signal C, 11 a decoder circuit for converting color signal C into two color difference signals R-Y, B-Y, 12 a luminance signal Y, color difference signals R-Y, B
-A / D conversion circuit for converting Y into a digital signal, 20 is a memory, 21 is a buffer memory having a memory capacity of at least one video signal line, 22 is a main memory having a memory capacity of a plurality of lines, and 30 is a D / A. A conversion circuit, 31 is a color difference signal R-
An encoder circuit for converting Y ', BY' into a color signal C ',
32 is a mixing circuit for the luminance signal Y'and chrominance signal C ', 40 is a synchronizing signal separating circuit, 41 is a write clock generating circuit, 42 is a writing control circuit, 43 is a reading control circuit, and 44 is a reference synchronizing signal generating circuit. .

The high-speed reproduction video signal input from the terminal 1 is input to the Y / C separation circuit 10 and the sync separation circuit 40. The Y / C separation circuit 10 separates the luminance signal Y and the color signal C, and the color signal C is further decomposed into two color difference signals RY and BY by the decoder circuit 11. Each signal is input to the A / D conversion circuit 12 and converted into a digital signal.

On the other hand, the sync separation circuit 40 separates the sync signal, and the write clock generation circuit 41 instantaneously generates a clock signal that is in phase with the separated horizontal sync signal. The A / D conversion circuit 12 performs sampling using this write clock signal. Further, the write clock signal is input to the write control circuit 42, and the writing of the A / D converted digital video signal to the memory 20 is controlled.

FIG. 2 is a waveform diagram for explaining the principle of skew correction. FIG. 2 (1) shows the envelope of the high frequency signal reproduced by the double azimuth head. When the signal level reproduced by each head of the double azimuth head becomes equal, the double azimuth head is switched to obtain a continuous signal. At this time, since the signal becomes discontinuous at the head switching unit, skew distortion occurs.

Figure 2 (2) demodulates the reproduced high-frequency signal,
It is the waveform of the luminance signal Y obtained by C separation. Indicates that the video signal is discontinuous at the head switching unit.

FIG. 2 (3) shows the horizontal sync signal separated by the sync separation circuit 40. FIG. 2 (4) shows a write clock generation circuit 41 for instantaneously pulsating the horizontal synchronizing signal to start oscillation.
The output signal of is shown. With this write clock signal,
The A / D converter 12 samples the luminance signal Y and the color difference signals RY and BY and writes them in the memory 20.

Since the write clock is generated by oscillating in synchronization with the horizontal synchronizing signal in phase, sampling data at a predetermined position with respect to the horizontal synchronizing signal can be stored at a predetermined address position in the memory 20. At this time, the memory 20 is composed of a buffer memory 21 having a memory capacity of at least one line and a buffer memory having a memory capacity of at least several lines. The A / D-converted sampling data is written in the buffer memory 21 line by line and transferred to the main memory 22 line by line.

Reading from the memory 20 is performed based on a stable read clock signal input from the terminal 3. The read clock is input to the reference synchronizing signal generation circuit 44 and the read control circuit 43 to control the reading from the memory 20. The signal read from the memory 20 is input to the D / A conversion circuit 30, and the luminance signal Y of an analog signal and the two color difference signals R-Y'B-Y '.
Is converted to. Color difference signals RY 'and BY' are encoders
It is input to 31 and modulated to obtain a color signal C '. Further, the luminance signal Y'and the color signal C'are input to the mixing circuit 32, mixed, and then output from the terminal 2 as a skew-corrected video signal.

FIG. 2 (5) shows a reference horizontal synchronizing signal generated by the reference synchronizing signal generating circuit 44 from the read clock. The reference horizontal sync signal is a signal at regular intervals, and by reading the signal from the memory 20 based on this, discontinuity of the sync signal can be eliminated and skew distortion can be removed.

FIG. 2 (6) shows a waveform in which the synchronizing information is added by the mixer 32 to the video signal thus read.

As described above, the skew distortion can be removed, but in the waveform diagram shown in FIG. 2 (6), the discontinuity of the pattern generated in the head switching portion remains. In order to eliminate this discontinuity, the data of the previous line is replaced immediately after the head is switched. FIG. 2 (7) shows a waveform diagram in the state of replacement.
As a result, it is possible to realize skew correction without discontinuity of the pattern by the minimum signal replacement.

The pattern replacement can be realized as in the embodiment shown in FIG. The head switching signal input from the terminal 4 is input to the write control circuit 42. FIG. 3 is a diagram showing states of signals written in the buffer memory 21. In the case of a head shape in which the heads cannot be switched, data is sequentially written as shown in FIG. In FIG. 3, data nm indicates the m-th sampling data of n lines. As shown in FIG. 3 (2), when the head is switched immediately after the sampling data 22, the write control circuit 42 stops writing data to the buffer memory 21. Therefore, the data of the previous line remains in the buffer memory 21. Therefore, the data in the buffer memory 21 shown in FIG. 3B is transferred to the main memory 22 to replace the data in the previous line.

In the next line, as shown in FIG. 3C, the data is sequentially written into the buffer memory 21. However, if the playback horizontal sync signal is not detected on the next line,
Further, writing of data to the buffer memory 21 is prohibited. Then, the same data is transferred to the main memory 22 again as shown in FIG. This corresponds to the processing of dropout in which the signal is missing, but it is particularly likely to occur near the head switching section where the reproduction signal level drops, and even in this case interpolation can be performed easily.

As the memory 20, it is also possible to configure a line memory and a plurality of line memories or field memories,
Alternatively, for example, Hitachi's HM53461 called a dual port memory can be used.

According to the present invention, the discontinuity of the pattern can be realized with the minimum signal replacement, and the skew correction can be realized without the image quality deterioration.

Next, another embodiment of the present invention will be described. In FIG. 1, reference numeral 100 is an input terminal for a signal indicating the rotation phase of the cylinder. The rotation phase signal is input to the write control circuit 42 as shown by the dotted line. In this embodiment, the main memory 22 has a sufficient storage capacity for writing a field signal.

The write control circuit 42 counts the number of fields of the reproduction signal based on the rotation phase signal, and intermittently writes the signal to the main memory 22 via the buffer memory 21 for each arbitrary field.

At the time of reading, signals are continuously read from the main memory 22. Therefore, in a field where no signal is written, the field signal stored in the main memory 22 is repeatedly read.

When the search speed by high-speed reproduction is high, not only is the movement of the picture too intense, there is no sense of stability, but it is difficult to grasp the contents. In this embodiment, each scene can be viewed for a long time, so the contents can be grasped with certainty, and a sense of visual stability is also provided.

FIG. 4 shows an example of a memory map when the main memory 22 is a field memory. Write the data for each line to each line. In the example not shown in the fourth example, one field consists of n lines, and one line consists of m samples of data.

If you have a field memory as the main memory 22,
Various functions can be realized with the configuration shown in Part 1.

By writing the data in the memory map form shown in FIG. 4 and reading the data in the respective rows in the opposite direction at the time of reading, the mirror inversion function of left-right inversion can be realized. In addition, by reading the horizontal data repeatedly twice, such as 13,13,14,14 ..., and by reading one line twice,
It is possible to realize a zoom function that is twice as wide in the vertical and horizontal directions.

FIG. 5 is a diagram showing an example of an enlarged position of the zoom function. FIG. 5 (1) shows a video signal before expansion. Generally, significant information exists near the center of the screen. When we statistically handle various TV programs and video software, the faces of people are slightly above the center of the screen. Therefore, when the fixed position is enlarged, if the enlargement is made on the line 25 ± 15 from the center of the screen, most of the necessary video signals can be seen as shown in FIG. 5 (2).

〔The invention's effect〕

According to the present invention, since a video signal can be written line by line and read out for each data, it is possible to remove the discontinuity of the pattern at the time of skewless search and remove the skew distortion.

Further, since the main memory is used as a field memory and the video signal can be written intermittently for each field, the picture at the time of search can be stably read.

In addition, at the fixed position and the vertical / horizontal 2x enlargement function, you can see most of the required image by enlarging the image on the line 25 ± 15 with respect to the center of the original screen.

[Brief description of drawings]

1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining skewless search, FIG. 3 is an address diagram for explaining a line memory, FIG. 4 is a memory map diagram, and FIG. The figure is an illustration of the zoom function. 12 ... A / D converter, 20 ... Memory, 21 ... Buffer memory, 22 ... Main memory, 41 ... Write clock generation circuit, 42 ... Write control circuit, 43 ... Read control circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hiroyasu Otsubo Inventor Hiroyasu Otsubo 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Electric Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Hideo Nishijima 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Ltd. Home Appliances Research Laboratory (72) Inventor Michio Masuda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Corporation Home Appliances Research Laboratory (72) Inventor Satoshi Tamura 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture (56) References JP 62-18879 (JP, A) JP 62-7277 (JP, A) JP 62-264782 (JP, A) Nikkei Electronics, 1987 May 18th issue (No. 421) P. 147-162

Claims (3)

[Claims] 1. A video signal processing device for obtaining a reproduced video signal by switching a plurality of rotary heads from a video signal recorded obliquely on a tape, and means for separating horizontal synchronization information from the reproduced video signal, and the separation means. Write clock generating means for generating a write clock phase-synchronized with the horizontal synchronizing information, a line memory for storing at least one line signal of the reproduced video signal, and a main memory for storing signals of a plurality of lines of the reproduced video signal. A memory; a transfer control means for transferring the stored contents of the line memory to the main memory line by line; a writing control means for writing the reproduced video signal in the line memory; and a reproduced video signal written from the main memory Read-out control means for reading out without passing through the line memory, Immediately after the head is switched, until the next horizontal synchronization information is separated, and when the horizontal synchronization information is not separately detected, write control is performed so as to stop writing the reproduced video signal in the line memory. A video signal processing device characterized by the above. 2. The video signal is stored on the tape so as to have a predetermined azimuth angle which is different for each track, and at least one of the plurality of reproducing heads corresponds to each azimuth angle of the track. Each time the respective head outputs of the double azimuth head are switched, each head output of the double azimuth head is switched until immediately after the next horizontal synchronization information is separated from immediately after the switching of each head. The video signal processing device according to claim 1, wherein write control is performed so as to stop writing to the line memory. 3. The main memory has a storage capacity for at least one field of the reproduced video signal, the transfer control means has means for stopping the transfer in field units, and the line memory is transferred to the main memory. The video signal processing according to claim 2, characterized in that, when the reproduced video signal of a new field is not transferred, the reproduced video signal already stored in the main memory is repeatedly read field by field. apparatus.