JPS6399683A - Video recording and reproducing device - Google Patents

Abstract

PURPOSE:To obtain the reproduced picture of a good quality by operating the address of a memory so as not to write the reproduced signal of the part of a discontinuous synchronizing signal by using a field memory, and besides, reading-out from the memory being made not synchronized with a writing. CONSTITUTION:The address of the memory is operated so as not to write the reproduced signal of the part of the discontinuous synchronizing signal in the memory by using the field memory 9, and further, the reading-out from the memory is performed being made not synchronized with the writing. Namely, the output of a delay circuit 31 to delay a head switching signal inputted to a terminal 42, that is an output from a comparator 6, and the head switching signal are inputted to an exclusive OR (EX-OR) circuit 32, and thus, a pulse waveform is generated in a prescribed period including the point of the time of the switching of the head. A horizontal synchronizing signal from this output terminal 41 is gated by an OR circuit 33, and the counting-up of an address counter 30 at the point of the switching of the head is stopped and the updating of an address is prevented.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a video recording and reproducing device, and in particular to a video recording and reproducing device that uses field memory to obtain high-quality reproduced images with reduced noise bars and skew distortion during high-speed reproduction. It is.

[Conventional technology]

Currently, video tape recorders (hereinafter referred to as VTRs) have various head configurations for the purpose of improving special playback performance. Here, we will take as an example the commonly used 4-hefed configuration.

FIG. 5 shows an example of the four-head configuration described above. As shown in this figure, in a 4-head configuration, head bears (Ja, Jb), (
Ka, Kb) are mounted on the rotating drum 60, facing each other at 180°, as shown in (8) to (C1) in the figure.

Now, let us consider a case where the video track 51 on the video tape 50 shown in FIG. 6 is played back at triple speed in the reverse direction using such a head configuration. Here, e and f in the figure represent head trajectories, and head pair J follows the trajectory of e, and head it! It is assumed that each head pair K traces the It trace. Also, for the truck to J
The head of a, Ka is Kb, J to the trunk of B.
Let b and 7d have the same azimuth.

At this time, the output obtained from the head during one field period is as shown in FIG. 7 with respect to the trajectory of e. That is, 1
Within the field, a head with the same azimuth angle as track 2 is selected, and the output is sequentially switched. Here, FIG. 7 shows only half of the output waveform obtained vertically symmetrically. In this case, the reproduced image on the monitor will appear as shown in FIG. 8, but the noise bar m and skinny distortion n at the head switching point will remain.

[Problem to be Solved by the Invention 3] As described above, in the conventional apparatus, since the reproduced image is a continuous reproduction signal, large noise bars do not occur, and the quality of the reproduced image is good to some extent. However, there is still no synchronization signal connection at the head switching point, and one horizontal period at that point does not result in a complete reproduced image, so the noise bar and skew distortion remain as they are, causing the problem that the reproduced screen is unsightly.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a video recording and reproducing apparatus that can obtain high-quality, high-speed reproduced images without noise bars or skew distortion.

[Means for solving problems]

A video recording and reproducing device according to the present invention uses a field memory, manipulates memory addresses so as not to write discontinuous portions of a playback signal of a synchronous signal to the memory, and makes reading from the memory asynchronous with writing. This is what I decided to do.

[Effect]

In this invention, the discontinuous portion of synchronization due to head switching is not written to memory, so when reproduced on a monitor, the noise bar disappears. Furthermore, since reading from the memory is asynchronous with writing, skew distortion is eliminated and high-quality reproduced images can be easily obtained.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

In FIG. 1, Ja, Jb, Ka, and Kb are pairs of bare heads having different azimuth angles, that is, Ja and Ka, and Jb and Kb are heads having the same azimuth. 2 is a first changeover switch that alternately selects the head pair output for each field, whereby the reproduction signal on the selected video tape 50 is guided to the first preamplifier 2 and the second preamplifier 3, respectively. 4
．． 5 is a first circuit which detects the envelope of the reproduction signal output from the preamplifier 2.3. This is the second detection circuit, which extracts the upper half of the vertically symmetrical detection signal. A comparator 6 compares the levels of the detected signals.

The output of the comparator 6 is used as a cover head switching signal to control opening and closing of the second changeover switch 7 to select the bare head and send the reproduced signal to the video signal processing circuit 8.

Further, 10 is a memory control circuit consisting of an address generation circuit 11 and a timing generation circuit 12. The address generation circuit 11 generates an address to the field memory 9, and the timing generation circuit 12 is separated from the video signal processing circuit 8. The write timing to the field memory 9 is generated based on the synchronization signal and the output from the comparator 6.

15 is a control head, and based on this reproduction output, a servo circuit 16 controls a capstan motor 17.
The reel motor 18 is controlled to control tape running in each mode. At the same time, the drum motor 19 of the rotating drum is controlled to generate switching timing for the first changeover switch 1.

Note that the field memory 9 is a dual port memory or a multi-boat memory (not shown), and has a random output and a serial output as output ports.
Using a serial port allows you to write to and read from memory asynchronously. Here, while writing the reproduced signal from the video signal processing circuit 8 into the field memory 9, an asynchronous operation is performed in which the contents of the field memory 9 are read out using a serial port.

Further, FIG. 2 shows in detail the address generation circuit 11 included in the memory control DliILO. In the figure, 30 is an address counter, which is reset by the vertical synchronizing signal input from the video signal processing circuit 8 to the terminal 40 for each field, and by counting up the horizontal synchronizing signal input to the terminal 41, the field memory 9 is output to the terminal 43. Further, 31 is a delay circuit that delays the head switching signal that is the output from the comparator 6 that is input to the terminal 42, and this output and the head switching signal are input to the exclusive OR (EX-OR) circuit 32. As a result, a pulse waveform is generated during a predetermined period including the time of head switching. At this output, the horizontal synchronizing signal from the terminal 41 is gated by the OR circuit 33, and the count amplifier of the address counter 30 at the head switching point is stopped so that the address is not updated.

Next, the operation will be explained.

Here again, we will take 3x speed in the reverse direction as an example.

Now, the trajectory of e on the video track 51 in FIG.
, Jb are selected and traced. At this time, the first changeover switch 1 is connected to the S side, and the outputs from the first preamplifier 2 and the second preamplifier 3 are as shown in FIG. 3(a).

(The output is as shown in bl. This output is output from the first detection circuit 4.
, are input to the second detection circuit 5, and only the envelopes are extracted, as shown in FIG. 3 (C1, ldl).

Then, these are compared by the comparator 6 and shown in Fig. 3 (e
1 head switching signal is obtained. That is, the level of this head switching signal is "L" 17) LH;! On the other hand, when the head Ja output is at level I'', the head Jb output is selected.

Next, the operation of the head switching point will be described in detail.

Here, consider the vicinity of point P in FIG. 3 (8).

Now, when a head switching signal as shown in Fig. 4 (Ta) is inputted from the terminal 42 in Fig. 2 and passed through the delay circuit 31, it becomes as shown in Fig. 4 (bl).This signal and the original input are unchanged. EX-
When inputted to the OR circuit 32, an output as shown in FIG. It is slightly less than the 63.5μ38C of .

Here, as described above, the horizontal synchronizing signal at the track crossing portion, that is, near the head switching point, is discontinuous between the signal before the head switching point and the signal after it.

FIG. 4 fdl and fQl respectively show this situation, which is shorter than the period of a normal horizontal synchronizing signal.

At this time, the first horizontal synchronization signal after head switching is E
X-Or! The output of the circuit 32 is gated by the OR circuit 33, so the address counter 30 does not count up. That is, the contents of one horizontal period based on the first horizontal synchronization signal after head switching are rewritten to the current address position. This situation is shown in FIG. 4ffl. In other words, the Nth horizontal synchronization signal shown in Fig. 4 (el) is not counted up, and the content of the reproduced image for one horizontal period based on this synchronization signal is shown in Fig. 4 +dl (N-1).
written to the address location. Therefore, the synchronous discontinuous portion has been removed.

As described above, in this embodiment, since the content of the noise bar is not written within the monthly horizontal period, there is no noise bar. Further, as described above, since the contents of the reproduced signal written in the field memory 9 are read out sequentially and asynchronously with the reproduced synchronization signal, it goes without saying that skew distortion is eliminated.

Note that in the above embodiment, overwriting to the memory is performed only during one horizontal period after head switching, but this overwriting period may be set to several horizontal periods depending on the system.

Further, for asynchronous operation, a dual port memory or a multi-port memory is used as the field memory, but there is no need to be particular about this, and a general-purpose memory may be used.

Also, as an example of high-speed playback, we explained 3x speed in the reverse direction.
The present invention is applicable to both odd and even speeds, and any speed may be used as long as the speed is within the range allowed by the system.

Further, although the above embodiment uses a four-head configuration, a two-head configuration may be used if noise bars are expected to occur to some extent and the purpose is to eliminate skew distortion.

〔Effect of the invention〕

As described above, according to the present invention, a field memory is used, the address of the memory is manipulated so as not to write the reproduced signal of a discontinuous part of the synchronous signal to the memory, and the reading from the memory is asynchronous with the writing. Therefore, when the image is reproduced on a monitor, noise bars and skew distortion are eliminated, and therefore, a high-quality reproduced image can be easily obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video recording and reproducing apparatus according to an embodiment of the present invention, FIG. 2 is a diagram showing the memory control circuit in detail, and FIGS. 3 and 4 are both diagrams of an embodiment of the present invention. Figure 5 is a diagram to explain the operation, Figure 5 is a diagram showing the conventional 4-head configuration, Figure 6 is a diagram showing the relationship between the video track and head trajectory during high-speed playback, and Figure 7 is the envelope during high-speed playback. A diagram showing a line detection waveform, and FIG. 8 is a diagram showing a reproduction screen of a conventional device. J, K...Magnetic head, 4, 5...1st. 2nd detection circuit, 6... Comparator, 7... Second changeover switch, 9... Field memory, 10... Memory control circuit, 11... Address generation circuit,
DESCRIPTION OF SYMBOLS 12... Timing generation circuit, 30... Address generation circuit, 31... Delay circuit, 32... Exclusive OR circuit, 33... OR circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) First and second envelope detection circuits that extract envelope detection waveforms of reproduced signals obtained from the first and second magnetic heads during high-speed reproduction; and from the first and second envelope detection circuits. a comparator for comparing outputs of the first and second magnetic heads; a changeover switch for switching and outputting reproduction signals from the first and second magnetic heads based on the comparator output; a field memory whose contents are read out asynchronously with the synchronization signal of the reproduced signal; a detection means for detecting the switching point of the first and second magnetic heads to detect a discontinuous portion of the synchronization signal; and the detection result. A video recording and reproducing apparatus comprising: address control means for controlling an address to the field memory so that a reproduction signal of a discontinuous portion of the synchronization signal is not written to the field memory. (2) The detection means includes a delay circuit that delays the output of the comparator for a predetermined period, and performs a logical operation on the output of the delay circuit and the output of the comparator, and generates a gate pulse for a predetermined period including the switching point of the magnetic head. The address control circuit includes an address counter that counts up the horizontal synchronization signal of the reproduced signal and outputs the address to the field memory, and a gate circuit that outputs the address to the field memory by the gate pulse. 2. The video recording and reproducing apparatus according to claim 1, further comprising a gate circuit that stops inputting a horizontal synchronizing signal and stops updating addresses.