JPH0577239B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a video recording and reproducing device, and particularly to a video recording and reproducing device that uses field memory to obtain high-quality reproduced images with reduced noise bars and skew distortion during high-speed reproduction. It is.

[Conventional technology]

Currently, video tape recorders (hereinafter referred to as VTRs) are equipped with
There are various head configurations. Here, we will take as an example a commonly used four-head configuration.

FIG. 5 shows an example of the four-head configuration described above. As shown in this figure, in a four-head configuration, pairs of heads with different azimuth angles
Ja, Jb, Ka, Kb are 180° opposed, rotating drum 6
0 as shown in Figures a to c.

Now, let us consider the case where the video track 51 on the video tape 50 shown in FIG. 6 is played back at triple speed in the reverse direction using such a head configuration. Here, e and f in the figure represent the trajectory of the head, and e
Assume that head pair J traces the trajectory of f, and head pair K traces the head trajectory of f. Furthermore, for track A, the heads of Ja and Ka have the same azimuth, and for track B, the heads of Kb and Jb have the same azimuth.

At this time, the output obtained from the head during one field period is as shown in FIG. 7 with respect to the trajectory of e. That is, heads with the same azimuth angle as the azimuth angle on the track are selected within one field, and the outputs are sequentially switched. Here, FIG. 7 shows only the upper half of the output waveform obtained vertically symmetrically. In this case, the reproduced image on the monitor will appear as shown in FIG. 8, but the noise bar m and skew distortion n at the head switching point will remain.

[Problem that the invention seeks to solve]

As described above, in the conventional apparatus, since the reproduced image is a continuous reproduction signal, large noise bars do not occur, and the quality of the reproduced image is good to some extent. However, there is still no synchronization signal connection at the head switching point, and one horizontal period at that point is not a safe playback image, so the noise bar and skew distortion remain as they are.
There was a problem with the playback screen being ugly.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a video recording and reproducing apparatus that can obtain high-quality, high-speed reproduced images without noise bars and skew distortion.

[Means for solving problems]

The video recording and reproducing device according to the present invention uses a field memory, manipulates memory addresses so as not to write discontinuous portions of a playback signal of a synchronous signal to the memory, and asynchronously reads and writes data from the memory. This is what I decided to do.

[Effect]

In this invention, since discontinuous parts of synchronization due to head switching are not written to memory,
When played on the monitor, the noise bar disappears. Also, since reading from memory is asynchronous with writing, skew distortion is eliminated.
High-quality playback images can be easily obtained.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In FIG. 1, Ja, Jb, Ka, and Kb are pairs of heads having different azimuth angles, that is, Ja and Ka, and Jb and Kb are heads having the same azimuth. 1 is a first changeover switch that alternately selects the head pair output for each field, and this switches the selected videotape 50.
The above reproduced signal is guided to the first preamplifier 2 and the second preamplifier 3, respectively. Reference numerals 4 and 5 designate first and second detection circuits for envelope detection of the reproduced signal output from the preamplifiers 2 and 3, respectively, whereby the upper half of the vertically symmetrical detected signal is extracted. 6
is a comparator that compares the levels of the detected signals. The output of the comparator 6 is used as a head switching signal to control the opening and closing of the second changeover switch 7, selects one of the paired heads, and sends the reproduced signal to the video signal processing circuit 8.

Further, 10 is a memory control circuit consisting of an address generation circuit 11 and a timing generation circuit 12. The address generation circuit 11 generates an address to the field memory 9, and the timing generation circuit 12 is separated from the video signal processing circuit 8. The write timing to the field memory 9 is generated based on the synchronization signal and the output from the comparator 6.

Reference numeral 15 designates a control head, and based on this reproduction output, a servo circuit 16 controls a capstan motor 17 and a reel motor 18 to control the running of the tape in each mode. At the same time, the drum motor 19 of the rotating drum is controlled to generate switching timing for the first changeover switch 1.

Note that the field memory 9 is a dual port memory or a multiport memory (not shown), and has a random output and a serial output as output ports, and if the serial port is used, writing and reading to the memory can be performed asynchronously. This can be done with Here, field memory 9
An asynchronous operation is performed in which the contents of the field memory 9 are read using the serial port while writing the reproduced signal from the video signal processing circuit 8 to the field memory 9.

Further, FIG. 2 shows the address generation circuit 11 included in the memory control circuit 10 in detail. In the figure, 30 is an address counter, which is reset by the vertical synchronizing signal inputted to the terminal 40 from the video signal processing circuit 8 for each field, and by counting up the horizontal synchronizing signal inputted to the terminal 41, the field memory is 9 is output to the terminal 43. Further, 31 is a delay circuit that delays the head switching signal which is the output from the comparator 6 inputted to the terminal 42, and this output and the head switching signal are connected to the exclusive OR (EX-OR) circuit 3.
2, thereby generating a pulse waveform during a predetermined period including the time of head switching. Then, at this output, the horizontal synchronizing signal from the terminal 41 is gated by the OR circuit 33 to stop the address counter 30 from counting up at the head switching point, thereby preventing the address from being updated.

Next, the operation will be explained.

Here again, we will take 3x speed in the reverse direction as an example.
Now, the trajectory of e on the video track 51 in Fig. 6 is
Assume that Ja and Jb video heads are selected and traced. At this time, the first changeover switch 1 is connected to the S side, and the outputs from the first preamplifier 2 and the second preamplifier 3 are respectively shown in FIG.
It becomes as shown in . This output is input to the first detection circuit 4 and the second detection circuit 5, and only the envelope is extracted, as shown in FIG. 3c and d, respectively. These are then compared by a comparator 6 to obtain the head switching signal shown in FIG. 3e. That is,
When the level of this head switching signal is "L", the head Ja output is selected, and when the level is "H", the head Jb output is selected.

Next, the operation of the head switching point will be described in detail.
Here, consider the vicinity of point P in FIG. 3e.

Now, if a head switching signal as shown in FIG. 4a is inputted from the terminal 42 in FIG. 2 and passed through the delay circuit 31, the result will be as shown in FIG. 4b. When this signal and the original input head switching signal (Fig. 4a) are input to the EX-OR circuit 32, the fourth
The output shown in Figure c is obtained. That is, the head switching point can be detected as a pulse waveform. Note that the delay amount of the delay circuit 31 here is slightly smaller than 63.5 μsec of one horizontal period.

Here, as mentioned above, the horizontal synchronizing signal at the track crossing portion, that is, near the head switching point, is discontinuous between the signal before the head switching point and the signal after it. FIGS. 4d and 4e each show this situation, which is shorter than the period of a normal horizontal synchronizing signal. At this time, the first horizontal synchronizing signal after switching the head is sent to the EX-OR circuit 32.
The address counter 30 is gated by the OR circuit 33 at the output thereof, so the address counter 30 does not count up. That is, the contents of one horizontal period based on the first horizontal synchronization signal after head switching are rewritten to the current address position. This situation is shown in FIG. 4f. In other words, the N-th horizontal synchronization signal shown in FIG. 4e is not counted up, and the content of the reproduced image for one horizontal period based on this synchronization signal is at the (N-1)th address shown in FIG. 4d. written to the position. Therefore, the synchronous discontinuous portion has been removed.

In this way, in this embodiment, half-finished content as a noise bar is not written within one horizontal period, so there is no noise bar. Further, as described above, since the contents of the reproduced signal written in the field memory 9 are read out sequentially and asynchronously with the reproduced synchronous signal, it goes without saying that skew distortion is eliminated.

In the above embodiment, the memory is overwritten for only one horizontal period after head switching, but the overwriting period may be several horizontal periods depending on the system.

Further, for asynchronous operation, a dual port memory or a multiport memory is used as the field memory, but there is no need to be particular about this, and a general-purpose memory may be used.

Further, triple speed in the reverse direction has been described as an example of high-speed playback, but the present invention can be applied to both odd and even numbered speeds, and any number of times may be used as long as the speed is within the range allowed by the system.

Furthermore, although the above embodiment uses a four-head configuration, assuming that noise bars occur to some extent, if the purpose is to remove skew distortion, two heads can be used.
A head configuration may also be used.

〔Effect of the invention〕

As described above, according to the present invention, a field memory is used, the address of the memory is manipulated so as not to write the reproduced signal of a discontinuous part of the synchronous signal to the memory, and the reading from the memory is performed asynchronously with the writing. Therefore, when the image is reproduced on a monitor, noise bars and skew distortion are eliminated, and a high-quality reproduced image can be easily obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a video recording and reproducing apparatus according to an embodiment of the present invention, FIG. 2 is a diagram showing the memory control circuit in detail, and FIGS. 3 and 4 are both diagrams of an embodiment of the present invention. A diagram to explain the operation,
FIG. 5 is a diagram showing the conventional four-head configuration, FIG. 6 is a diagram showing the relationship between the video track and the head trajectory during high-speed playback, FIG. 7 is a diagram showing the envelope detection waveform during high-speed playback, and FIG. FIG. 8 is a diagram showing a playback screen of a conventional device. J, K...Magnetic head, 4, 5...1st, 2nd
Detection circuit, 6... Comparator, 7... Second changeover switch, 9... Field memory, 1
0...Memory control circuit, 11...Address generation circuit, 12...Timing generation circuit, 30
... Address counter, 31 ... Delay circuit, 32
...Exclusive OR circuit, 33...OR circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. A magnetic head pair consisting of first and second magnetic heads having different azimuth angles is provided on a rotating drum so as to face each other approximately 180 degrees, and during high-speed reproduction, the 1st
and first and second envelope detection means for extracting an envelope detection signal of a reproduced signal reproduced by a second magnetic head; and a comparison means for comparing outputs from the first and second envelope detection means. and reproduction signal switching means for switching the reproduction signal from the first or second magnetic head based on the result of the comparison means, the reproduction signal switching means corresponding to the synchronization signal of the reproduction signal from the reproduction signal switching means. generating an addressing signal and storing the reproduced signal in a field memory;
In a video recording and reproducing device that reads out the stored contents using a synchronous signal and an asynchronous signal of a reproduction signal, discontinuous discontinuity occurs when the reproduction signal from the first or second magnetic head is switched by the reproduction signal switching means. a discontinuous synchronization signal detection means for detecting a synchronization signal; and an address control means for stopping designation of a memory address corresponding to the synchronization signal detected by the discontinuous synchronization signal detection means; When a discontinuous synchronization signal is detected by the discontinuous synchronization signal detection means when writing a signal to the field memory, memory address specification using this discontinuous synchronization signal is stopped, and the discontinuous synchronization signal is A video recording/playback device characterized in that a corresponding playback signal is rewritten to a current memory address.