JP2734278B2 - Video signal magnetic playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] The present invention relates to a video signal magnetic reproducing apparatus capable of magnetic reproduction or magnetic recording / reproduction of a video signal.

[0002]

2. Description of the Related Art FIG. 17 is a conceptual diagram for explaining a tape pattern during special reproduction, FIG. 18 is a block diagram of a conventional video signal magnetic reproducing device, and FIG. 19 is for explaining head switching during a horizontal blanking period. Timing chart,
FIG. 20 is a timing chart for explaining the problem of the reproduced luminance signal, and FIG. 21 is a conceptual diagram for explaining the problem of the reproduced color signal. Hereinafter, a conventional technique will be described with reference to the drawings.

In a conventional VTR for reproducing a video signal, as shown in FIG. 17A, a magnetic tape T is wound around a rotary drum X by approximately 180 degrees, and the magnetic tape TT runs along a running direction TT1. The rotary drum X is rotated in the rotation direction X1, and 180
The reproduction is performed by selectively using the first and second magnetic heads H1 and H2 having different azimuth angles formed so as to oppose each other.

[0004] During special reproduction in which the magnetic tape TT runs at a speed higher than the normal speed of running the magnetic tape, third and fourth azimuth angles having different azimuth angles formed on the rotating drum X so as to oppose 180 degrees are provided. Magnetic head H
3 and H4. Here, the third and fourth magnetic heads H3 and H4 correspond to the first and second magnetic heads H1 and H1, respectively.
The first and fourth magnetic heads H1 and H4 are formed at a distance of approximately one horizontal period (hereinafter, abbreviated as "H") from H2.
Have the same azimuth angles, and the second and third magnetic heads H
The azimuth angles of 2 and H3 are the same.

At the time of high-speed reproduction, one magnetic head passes through tracks written at different azimuth angles, so that the amplitude of a reproduction signal alternately increases or decreases. For example, as shown in FIG. 3B, the waveform of the reproduction signal reproduced by the first magnetic head H1 is as shown by H1a, and the waveform of the reproduction signal reproduced by the third magnetic head H3 is It looks like H3a. Then, these reproduced signals are selected by a switch circuit 1 to be described later, in which the amplitude of both reproduced signals is larger, to obtain a switch circuit output signal 1a.

Here, the conventional VTR will be described in detail with reference to FIG.
Are amplified to predetermined amplitudes by a preamplifier (not shown), respectively, and then the switch circuits 1 (SW) and F
It is supplied to the M level detection circuit 2. And this FM
The level detection circuit 2 detects the magnitude of the amplitude of both signals and
The FM level detection circuit output signal 2a obtained by the conversion is supplied to the latch circuit 10.

The operation of the latch circuit 10 will be described with reference to FIG. 19. First, the sync separation circuit 9 performs synchronization separation from the reproduced luminance signal 7a shown in FIG. The horizontal synchronizing signal 9a shown in FIG. 2B is input as a clock signal of the latch circuit 10, and at this rising edge, the FM level detection circuit output signal 2a shown in FIG. 2C is latched and shown in FIG. The latch circuit output signal 10a is obtained.

The latch circuit output signal 10a is
8, a signal reproduced from the first magnetic head H1 during a period when the latch circuit output signal 10a is at a high level, and a third magnetic signal during a period when the latch circuit output signal 10a is at a low level. The signal reproduced from the head H3 is switched and output to obtain a switch circuit output signal 1a.

In this manner, the switching timing of the reproduced signal can be set within the horizontal blanking period, so that the noise caused by the discontinuity of the FM modulation signal caused by the switching of the reproduced signal can be reduced. It can be generated within a horizontal blanking period that does not cause a visual problem.

A signal obtained from the switch circuit output signal 1a through a low-pass filter 3 for frequency-separating a low-frequency-converted color signal and a high-pass filter 4 for frequency-separating an FM-modulated luminance signal is The signals are supplied to the color signal reproduction system 5 and the luminance signal reproduction system 7, respectively. Then, the color signal reproduction system 5 performs the rotation restoration for restoring the phase rotation of 90 degrees every 1H performed when the input signal is subjected to the low-frequency conversion at the time of recording by using the above-described synchronization signal 9a and performs the high-frequency conversion. The obtained reproduction color signal 5a is converted into a first time axis correction circuit 6 (T
BC1). On the other hand, the luminance signal reproducing system 7 supplies a reproduced luminance signal 7a obtained by subjecting the input signal to FM demodulation or the like to the synchronization separation circuit 9 and the second time axis correction circuit 8 (TBC2).

The first and second time axis correction circuits 6,
Reference numeral 8 denotes an output color signal 6 obtained by performing time axis correction on the reproduced color signal 5a and the reproduced luminance signal 7a using the horizontal synchronization signal 9a.
a and the output luminance signal 8a are supplied to a transmission line (not shown) and also to an addition circuit 11, where the output video signal 11a obtained by adding the two signals is supplied to a transmission line (not shown).

As described above, the switching timing of the magnetic head during high-speed reproduction is performed within the horizontal blanking period and FM demodulation is performed, so that the switching noise appearing in the output luminance signal 7a is generated within the horizontal blanking period that is inconspicuous on the screen. I was able to.

[0013]

However, since the phases of the signals reproduced by the first and third magnetic heads H1 and H3 at the switching timing of the magnetic heads do not coincide with each other, the horizontal frequency of the reproduced luminance signal 7a sharply increases. It changes and causes skew. Therefore, the second time axis correction circuit 8
Even if this is corrected, there is a problem that the output luminance signal 8a has a skew remaining on the line immediately after the switching of the magnetic head, and in the reproduced color signal 5a, the order of the rotation correction is discontinuous. Therefore, it takes time until the phase is pulled in the so-called APC circuit, and there is a problem that the color is disturbed in the line immediately after the switching of the magnetic head.

First, the problem of the output luminance signal 8a will be described with reference to FIG.
(A) shows the reproduction luminance signal 7a of the first magnetic head when the magnetic head is not switched, and FIG. (B) shows that the magnetic head is not switched. 7 is a reproduction luminance signal 7a relating to the third magnetic head in the case where it is assumed that the reproduction luminance signal 7a is set. Here, assuming that the magnetic heads have been switched with the phase relationships shown in FIGS. 7A and 7B, the first magnetic head H1 is switched to the third magnetic head H3 at the timing "A". In this case, a reproduced luminance signal 7a shown in FIG. Also, the third
When the magnetic head H3 is switched to the first magnetic head H1 at the timing "B", the reproduced luminance signal 7a shown in FIG. The reproduced luminance signal 7a thus obtained has a skew.

The operation of the second time axis correction circuit 8 for performing time axis correction on these signals will be described with reference to FIG. 1E. The reproduction luminance signal 7a in FIG. In the first to seventh memories M1 to M7 in the second time axis correction circuit 8,
For each H, the data is written with a clock signal following the jitter of the reproduced video signal 7a for a predetermined period from the falling edge of the horizontal synchronization signal 9a, read with a clock signal having a stable frequency, and output as shown in FIG. Luminance signal 8a
Have gained. Here, there are two horizontal synchronization signals in the output luminance signal 8a of the fourth memory M4, and skew occurs. Also, the output luminance signal 8a relating to the sixth memory M6 lacks the first half of the picture, so skew occurs again.

Next, the problem of the output color signal 6a will be described with reference to FIG. 21. FIG. 21A shows the latch circuit output signal 10a, and FIG. Represents the rotation of the reproduced low-frequency conversion color signal 3a obtained by the above. As shown in the figure, the phase shift is performed so that the phase is sequentially delayed while the latch circuit output signal 10a is at the low level, while the high level period is Are sequentially shifted so that the phase advances, and as a result, phase continuity is maintained.

However, the continuity of the phase is not always maintained in practice, and the phase discontinuity may occur at the timings P1 and P2 as shown in FIG.

The problem caused by such phase discontinuity will be described with reference to a conventional color rotation process BB shown in FIG. 1D. It comprises a generation circuit 63, a switch circuit 64, a frequency conversion circuit 65, and a 2-bit counter circuit 66.

The frequency conversion circuit 65 multiplies the high frequency conversion signal bb (3.58) obtained by multiplying the reproduced low frequency conversion signal 3a by a switch circuit output signal 64a in order to convert it into a high frequency.
MHz) is output from the second phase comparison circuit 91.
The phase is compared with a signal supplied from a crystal oscillation circuit 92, which is a stable oscillation source, and a so-called local signal (4.2 MHz) oscillated by a voltage-controlled oscillation circuit (not shown) in four phases. By feeding back to the phase generation circuit 63, an APC loop for obtaining a stable high-frequency conversion signal bb is formed.

The high-frequency conversion signal bb is also supplied to a first phase comparison circuit 90, where it is compared with a signal supplied from a crystal oscillation circuit 92 to determine the discontinuity of the color rotation phase. If there is, a control signal is supplied to the 2-bit counter circuit 66 in order to forcibly restore the phase, where the first to fourth stations are controlled based on the control signal, the horizontal synchronizing signal 9a and the latch circuit output signal 10a. Signal S
0 to S3 are selected by the switch circuit 64. As described above, in the related art, a feedback loop is configured to correct the discontinuity of the phase of the color rotation.

However, in this configuration, since the discontinuity of the phase is detected only after the high-frequency conversion signal bb is output, it is considered that the high-frequency conversion signal bb is not perfect and the phase discontinuity remains. Had become. This causes a problem that the color of the line immediately after the switching of the magnetic head is disturbed.

[0022]

SUMMARY OF THE INVENTION The present invention provides the following means for solving the above problems.

In a video signal magnetic reproducing apparatus for reproducing a video signal from a magnetic recording medium using the first and second magnetic heads, a reproduced signal from the first magnetic head and a reproduced signal from the second magnetic head are reproduced. Switch circuit for switching and outputting a signal, a video signal reproduction processing circuit for demodulating a signal output from the switch circuit and outputting a reproduced video signal, and a synchronizing signal separating circuit for separating a horizontal synchronizing signal from the reproduced video signal A time axis correction circuit for writing the reproduced video signal every horizontal period using a clock following the jitter of the reproduced video signal, and outputting an output video signal obtained by reading with another clock; A delay circuit for outputting a first control signal obtained by delaying the first magnetic head by a predetermined time, an amplitude of a reproduction signal relating to the first magnetic head, and an amplitude of a reproduction signal relating to the second magnetic head. An amplitude detection circuit for outputting a second control signal obtained by comparison, wherein the switch circuit switches and outputs the signal in accordance with the first and second control signals. .

[0024]

[0025]

[0026]

FIG. 1 is a block diagram for explaining a main part of a reproduction system of a VTR according to an embodiment of the present invention, and FIG. 2 is an operation of a second time axis correction circuit 8 according to the first embodiment. 3 and 4 are timing charts for explaining the operation of the delay circuit 12.
5 is a timing chart for explaining the delay time T, FIG. 5 is a block diagram for explaining the operation of the second time axis correction circuit 8 according to the second embodiment, and FIG. 6 is a first method relating to noise removal. Timing chart for explaining, FIG. 7
8 is a timing chart for explaining a second method relating to noise removal, FIG. 8 is a timing chart for explaining a third method relating to noise removal, and FIG. 9 is a timing chart for describing a fourth method relating to noise removal. FIG. 10 is a block diagram for explaining a main part of the color signal system 5 according to the third embodiment, FIG. 11 is a block diagram for explaining a burst phase detection circuit AA, and FIG. 12 is a burst phase detection circuit AA. 13 is a block diagram for explaining the color tension process BB, FIG. 14 is a timing chart for explaining the operation of the 2-bit Bit counter circuit 66, and FIG. 15 is a time axis correction circuit. FIG. 16 is a timing chart for explaining the improvement of the APC error according to the first embodiment. It is a block diagram. The first embodiment will be described below in order with reference to the drawings.

(First Embodiment) FIG. 1 described above with reference to FIG.
8, the same reference numerals are given to the same components, and the description thereof will be omitted. Here, FIG. 1 is different from FIG. 18 in that a delay circuit 12 is newly provided, and a circuit which conventionally supplies the horizontal synchronizing signal 9a directly to the clock signal input of the latch circuit 10 is different from FIG. After a predetermined delay time T is applied to the horizontal synchronizing signal 9a through the circuit 12 (DL), the horizontal synchronizing signal 9a is supplied to the clock signal input of the latch circuit 10.

As a result, the skew of the reproduced luminance signal 7a can be improved by the second time axis correction circuit 8. The reason will be described with reference to FIG.

FIGS. 20A and 20B are diagrams corresponding to FIGS.
As in (B), when the magnetic head is not switched, the reproduced luminance signal 7a for the first and third magnetic heads
Are respectively illustrated. Since the switching timing of the magnetic head is delayed, the switching of the magnetic head is performed at timings “α” and “β” which are delayed by the delay time T of the delay circuit 12 from the timings “A” and “B” shown in the figure. . Therefore, when switching from the first magnetic head H1 to the third magnetic head H2, FIG.
In contrast, when the reproduction luminance signal 7a shown in FIG. 4 is switched from the third magnetic head H3 to the first magnetic head H1, the reproduction luminance signal 7a shown in FIG. 4D can be obtained.

The operation of the second time axis correction circuit 8 for performing time axis correction on these signals will be described with reference to FIG. 7E. The reproduced luminance signal 7a in FIG. In the first to seventh memories M1 to M7 in the second time axis correction circuit 8,
For each H, the data is written with a clock signal that follows the jitter of the reproduced luminance signal 7a for a predetermined period from the falling edge of the horizontal synchronization signal 9a, read with a clock signal having a stable frequency, and output as shown in FIG. Luminance signal 8a
Have gained.

In this manner, the switching of the magnetic head is performed by delaying the latch circuit output signal 10a by the delay time T using the delay circuit 12, so that the output luminance signal 8a with improved skew can be obtained. . Here, it is desirable that the delay time T be a maximum value not exceeding 1H-τ, where τ is a skew generated between the two magnetic heads.

The reason will be described with reference to FIGS.
As shown in FIG. 3, when the delay time T exceeds 1H-τ, the signal after switching shown in FIG. 3B advances from the signal before switching shown in FIG. In such a case, as shown in FIG. 7C, there occurs a disadvantage that the front edge of the horizontal synchronization signal of the reproduction luminance signal 7a is missing. On the other hand, as shown in FIG.
Is too small compared to 1H-τ, FIG.
This is because, when switching to FIG. 2B, the switching of the magnetic head appears at the center of the screen as shown in FIG. Therefore, the delay time T is set to a maximum value that does not exceed 1H-τ.

(Second Embodiment) In the first embodiment, the skew can be improved by appropriately setting the delay time T. However, the setting of the delay time T is based on the skew time τ generated between the two magnetic heads. Is not easy to determine, the switching of the magnetic head sometimes appears at the center of the screen (hereinafter, referred to as “in-screen switching”).

Therefore, in the second embodiment, the writing and reading control of the memory constituting the second time axis correction circuit 8 is improved to remove the switching noise in the screen.

Referring to FIG. 5, the second time axis correction circuit 8 will be described. This circuit is an A / D and D / A conversion A / D converter.
D, D / A conversion circuits 81 and 87 and first to fourth memories 82 to 85 (A to D) capable of storing information per 1H line
And a memory control circuit 86.
Memories 82 to 85 are simply referred to as A to D memories.

The output terminals A to A of the memory control circuit 86
DWE, A to DWR, A to DRE, and A to DRR represent the sign of the output signal, and A to DWE are write enable signals for setting the A to D memories to a writable state at a high level. DWR is a high level pulse and A
A to DRE are write enable signals for resetting the write addresses of the memory D, A to DRE are read enable signals for enabling the memory A to D to be readable at a high level, and A to DRR are pulses of a high level A to D This is a read reset signal for resetting a read address of the D memory, and these control signals control the A to D memories.

Since all of these A to D memories are not necessarily required for noise removal, four cases will be described separately.

The first method is a method for improving the noise by using two 1H memories A and B to stop writing to the memories A and B during the period in which the switching noise in the screen exists. is there. This will be described with reference to FIG.

The magnetic head is switched by the latch circuit output signal 10a shown in FIG. For this reason, the continuity of the FM modulation signal is lost at the rising edge, and as shown in FIG.
a becomes a signal having noise synchronized with the rising edge. Normally, the reproduced luminance signal 7a is
Of the time axis correction circuit 8 is alternately written every 1H, and the read luminance signal 7a written 1H earlier than the other memory is read out while writing to one memory.

However, in the vicinity of the rising edge of the latch circuit output signal 10a, in order to stop writing to the memory, the write enable signal BWE, which is at a low level during the period B6 as shown in FIG. It shall be written to memory. Since writing to the A memory is the same as in the normal case, the write enable signal AWE shown in FIG.

When such a write enable signal BWE is used, data is not written in the period B6, so that the reproduced luminance signal 7a written in the period B5 remains in the B memory during the corresponding period. .

Since reading is performed using the read enable signals ARE and BRE shown in FIGS. 7E and 7D, the output shown in FIG. The luminance signal 8a is obtained. It is needless to say that writing may be stopped at all for a horizontal line where noise is present.

The second method is to use the two 1H memories A and B during the period in which the in-screen switching noise exists, without reading the parts written in the memories A and B and reading the other parts. This is a method of improving by reading out. This will be described with reference to FIG.

Since the magnetic head is switched by the latch circuit output signal 10a shown in FIG. 7A, the continuity of the FM modulation signal is lost at the rising edge of the magnetic head. Therefore, as shown in FIG. The reproduction luminance signal 7a is a signal having noise synchronized with the rising edge. Then, the write enable signals AWE and BWE shown in FIGS.
The data is written alternately every time, and the read enable signals ARE and BRE shown in FIGS.
Control is performed such that the previously written reproduction luminance signal 7a is read.

However, in the period B7 for reading the B memory in which noise is written as shown in FIG. 9E, the read enable signal BRE is set to low level to stop reading from the B memory, and the read enable signal ARE is output. At a high level to read from the A memory. In this manner, the output luminance signal 8a shown in FIG. 9G is obtained by interpolating the signal during the period in which noise occurs in another period.

The third method uses three or more memories,
It is a method to improve the noise by stopping the writing of the memory during the period when the switching noise in the screen exists.
Similar to the first method, except that when the number of memories to be used increases, the signals to be interpolated are temporally separated and the correlation is reduced.

The third method will be described with reference to FIG. still,
Here, the case where four memories are used is described for convenience, but the same applies to the case of three memories or the case of five or more memories.

Since the magnetic head is switched by the latch circuit output signal 10a shown in FIG. 7A, the continuity of the FM modulation signal is lost at the rising edge thereof, and as shown in FIG. The reproduction luminance signal 7a is a signal having noise synchronized with the rising edge. Normally, the reproduction luminance signal 7a is alternately written to the A to D memories in the second time axis correction circuit 8 every 1H, and the reproduction luminance signal written from another memory during the period of writing to one memory. Control is performed so that the signal 7a is sequentially read.

However, in the vicinity of the rising edge of the latch circuit output signal 10a, the writing to the memory is stopped, so that the level becomes low during the period C8 as shown in FIG. It is assumed that data is written to the C memory by using the write enable signal CWE provided with a period C9 in which a high level is set for substantially the same time as the time C8. Since writing to the A, B, and D memories is the same as in the normal case, FIGS.
Write enable signals AWE and BW shown in FIG.
E and DWE are used.

When such a write enable signal CWE is used, the data is not written in the period C8, but is written in the period C9 having a correlation with this period. The reproduced luminance signal 7a is written.

Then, since reading is performed using the write enable signals ARE to DRE shown in FIGS. 8G to 8J, the output shown in FIG. The luminance signal 8a is obtained.

The fourth method is a method in which three or more memories are used and the other part is read without reading the part written in the memory during the period in which the switching noise in the screen exists. Yes, the method is similar to the second method, but when the number of memories to be used increases, the signals to be interpolated become temporally separated and the correlation decreases, so that this is avoided.

The fourth method will be described with reference to FIG. still,
Here, the case where four memories are used is described for convenience, but the same applies to the case of three memories or the case of five or more memories.

Since the magnetic head is switched by the latch circuit output signal 10a shown in FIG. 7A, the continuity of the FM modulation signal is lost at the rising edge of the magnetic head. Therefore, as shown in FIG. The reproduction luminance signal 7a is a signal having noise synchronized with the rising edge. Then, 1H is stored in the A to D memories by using the write enable signals AWE to DWE shown in FIGS.
Each time the data is sequentially written, the read luminance signal 7a written from another memory is sequentially read during writing to one memory using the read enable signals ARE to DRE shown in FIGS. Control.

However, during the period of reading the C memory in which noise is written as shown in FIG. 7B, the read enable signal CRE is set to C as shown in FIG.
Reading from the C memory is stopped at the low level for one period, and the read enable signal BRE is set at the high level to read from the B memory. In this way, the output luminance signal 8a shown in FIG. 9K is obtained by interpolating the signal in the period in which noise occurs by the signal 1H before.

(Third Embodiment) In the first and second embodiments described above, the improvement relating to the luminance signal system has been described. However, the third embodiment corrects the color rotation accompanying the switching of the magnetic head. Therefore, the color signal system 5 is improved as follows, and this will be described with reference to FIGS.

In the main part of the color signal system 5 shown in FIG. 10, the burst phase detection circuit AA is for detecting the discontinuity of the color rotation accompanying the switching of the magnetic head, and has a latch circuit output signal 10a. The phase difference of the burst signal in the reproduced low-frequency conversion color signal 3a is detected before and after the switching timing of the magnetic head supplied by the above. That is, the burst phase detection circuit AA
Is supplied with the reproduced low-frequency conversion color signal 3a before and after passing through the 1H delay circuit 61 (1HDL), and detects the phase difference between the signals, thereby detecting the first and second color rotation correction signals aa.
1 and aa2 are supplied to the color rotation process BB to correct the color rotation.

First, the burst phase detection circuit AA will be described in detail with reference to a block diagram of FIG. 11 and a timing chart of FIG. 629KH
The reproduced low-frequency conversion color signal 3a illustrated in FIG. 12B having z as a carrier frequency is converted into a signal illustrated in FIG. Supplied to

This filter circuit 51 has a first delay circuit 511 (1) having a delay time of a half wavelength of the carrier frequency.
/ 2λ DL) and a first subtraction circuit 512, which is obtained by subtracting the signal shown in FIG. 3D obtained from the input signal through the first delay circuit 511 (FIG. The subtraction circuit output signal 51a shown in E) is supplied to the binarization circuit 52. The binarization circuit 52 extracts the sign bit of the subtraction circuit output signal 51a and binarizes the same, as shown in FIG.
Is supplied to a differentiating circuit 53 as shown in FIG.
Here, a differentiated signal 53a shown in FIG. 11G synchronized with the rising edge of the binary signal 52a is obtained.

The differential signal 53a is gated by the burst gate pulse 55a shown in FIG. 7H obtained by the burst gate pulse generation circuit 55 based on the horizontal synchronization signal 3a shown in FIG. The signal is gated at 54 to obtain a phase information signal 54a shown in FIG.

The time from the falling edge of the horizontal synchronizing signal 9a to the rising edge of the phase information signal 54a is
After all, it indicates the phase information of the burst signal related to the reproduced low-frequency conversion color signal 3a. Therefore, the time is 1
If the measurement is performed for each H, the phase of the burst signal can be obtained, and the continuity of rotation can be determined by comparing the phases around 1H. The following configuration plays such a role.

For the sake of convenience, the phase information signal 54a shown in FIG. 9J is again supplied as a clock signal to the first latch circuit F1, where it is cleared and counted at the falling edge of the horizontal synchronizing signal 9a. The count data of the counter circuit 56 for starting
The output data shown in FIG. 9 (K) obtained by latching in step (a) is supplied to the second latch circuit F2.

In the second latch circuit F2, the output data is delayed by a substantially constant time from the rise of the phase information signal 54a generated from the horizontal synchronizing signal 9a by the timing pulse generation circuit 57 (FIG. (M) obtained by latching with the timing pulse 57a shown in (L).
Is supplied to a third latch circuit F3, and similarly latched by a timing pulse 57a to obtain third output data F3a shown in FIG. Incidentally, in FIGS. 9 (N) and 9 (M), D0 to D2 are 0th.
To data representing the phase of the burst signal in the second line.

Then, the second difference circuit 58 subtracts the third output data F3a from the second output data F2a, and the phase difference data 58a shown in FIG. 59, and the discrimination data obtained by discriminating the current rotation based on the phase difference data 58a is supplied to the rotation correction signal generation circuit 60, and the rotation data is supplied to the rotation correction signal generation circuit 60.
First and second rotation correction signals aa1 and aa2, which are command signals for advancing by 80 degrees, respectively, are obtained.

Next, the color rotation process BB to which the first and second rotation correction signals aa1 and aa2 are supplied will be described with reference to FIGS. 13 and 14, which is different from the conventional color rotation process BB. The point is that there is no feedback loop using the first phase comparison circuit 90. And the main part is 4
It comprises a phase / phase generation circuit 63, a switch circuit 64, a frequency conversion circuit 65, and a 2-bit counter circuit 66.
Note that the APC loop is the same as the conventional technique, and thus the description thereof is omitted.

The frequency conversion circuit 65 outputs a high-frequency conversion signal bb obtained by multiplying the reproduced low-frequency conversion signal 3a by a switch circuit output signal 64a in order to convert the reproduced low-frequency conversion signal 3a to a high frequency. Select a signal in which the rotation correction is considered.

That is, the 4-phase generating circuit 63 is a so-called local frequency of 4.2 MH used for high-frequency conversion.
The first to fourth local signals S0 to S3 having a frequency of z and having a phase shifted by 90 degrees are supplied to the switch circuit 64, where they are supplied from a 2-bit Bit counter circuit 66. The first to fourth local oscillation signals S0 to S3 are selected using the selection data signal 66a represented by 4 bits to obtain the switch circuit output signal 64a.

Now, the operation of the 2-bit Bit counter circuit 66 will be described with reference to FIG. 14. The horizontal synchronizing signal 9a shown in FIG. 90 degrees, 18 shown in FIG.
When the high level of the first and second rotation correction signals aa1 and aa2, which are the command signals for advancing by 0 degrees, is input, the count value is incremented or decremented by "1" and "2", respectively, from the normal value. It is the latch circuit output signal 10a shown in FIG. 1I that determines whether the 2-bit Bit counter circuit 66 performs the addition or subtraction operation.
That is, an addition operation is performed during a period when the signal is at a low level, and a subtraction operation is performed during a period when the signal is at a high level. The selection data, which is the count value of the 2-bit Bit counter circuit 66 thus obtained, is shown in FIG. 7B, and the respective selection data signals 66a are shown in order of LSB in FIGS.
Illustrated in FIG.

Here, the timing t1 shown in FIG.
First, at the timing t1, the latch circuit output signal 10a is at the low level, so that the operation is in the addition state, and the first rotation correction signal aa1 is at the high level. The selection data normally changes from “0” to “1”, but changes from “0” to “2”. At the timing t2, the latch circuit output signal 10a is at the low level, the operation is in the added state, and the second rotation correction signal aa2 is at the high level. A change from "0" to "1" is a change from "0" to "3". Further, at timing t3, the latch circuit output signal 1
Since 0a is at a high level, the operation is in a subtraction state, and since the first and second rotation correction signals aa1 and aa2 are both at a high level, the selection data is normally "3" to "2". Is changed from "3" to "3" because "3" is further subtracted.

In this way, since the rotation can be corrected for each 1H, the color reproducibility is improved even during special reproduction.

FIG. 15 shows a means for solving the problem that the pull-in time of the well-known APC loop used for high-frequency conversion during the color rotation process BB is prolonged due to the discontinuity of rotation due to switching of the magnetic head. It will be described using FIG.

FIGS. 9A to 9D show a reproduced luminance signal 7a for easy understanding of an ideal reproduced low-frequency converted color signal 3a.
And the order of the lines, and the phase of the burst signal in the reproduced low-frequency conversion color signal 3a is delayed by every 90 degrees.

However, if there is a skew, the skew occurs not only in the reproduced luminance signal 7a but also in the reproduced low-frequency conversion color signal 3a as shown in FIG.

The main part of the color signal reproducing system 5 which solves this problem will be described with reference to FIG. Here, the difference from FIG. 10 is a configuration in which a variable delay circuit 93 and a third time axis correction circuit 94 are newly added. Since other configurations are the same, the same reference numerals are given and the description thereof is omitted. I do.

The reproduced low-frequency conversion color signal 3a is the horizontal synchronization signal 9
After the skew is removed by the third time-axis correction circuit 94 based on a in the third time-axis correction circuit 94, the signal is supplied to the color rotation process BB and subjected to a predetermined process to obtain a high-frequency conversion signal bb. Note that the third time axis correction circuit 94 has the same configuration as the second time axis correction circuit 8.

When the third time axis correction circuit 94 performs time axis correction, a delay time occurs. Therefore, the first
The second color rotation correction signals aa1 and aa2 also need to be delayed, and the variable delay circuit 93 plays this role. However, the delay data 93 supplied from the third time axis correction circuit 94 so that the delay time of the variable delay circuit 93 automatically becomes substantially the same as that of the third time axis correction circuit 94.
b. The third time axis correction circuit 9
4 performs A-time correction before high-frequency conversion,
Since the operation of the PC loop is stabilized, the third time axis correction circuit 94 is inserted at the position of EE in FIG. 9F to perform the time axis correction on the reproduced low-frequency conversion color signal 3a. After that, the signal may be supplied to the 1H delay circuit 61 and the burst phase detection circuit AA. In such a case, the variable delay circuit 93 becomes unnecessary, and the configuration can be simplified.

As described above, since the color rotation can be corrected using the reproduced low-frequency converted signal from which the skew has been removed, a good high-frequency converted signal bb can be obtained without disturbing the operation of the APC loop.

(Fourth Embodiment) In the third embodiment described above, the discontinuity of the color rotation accompanying the switching of the magnetic head is corrected by detecting the phase of the burst signal. However, since this burst signal is a signal that has been subjected to low-frequency conversion, it is not possible to reduce crosstalk interference due to azimuth loss, and thus there is a possibility that errors in phase detection may increase. Therefore, in the fourth embodiment, a comb-shaped filter is applied to the low-frequency-converted burst signal to improve the accuracy of phase detection.

The comb filter used in the fourth embodiment will be described with reference to FIG. 16. This comb filter includes a second delay circuit 68 (1H ± 1 / 4λ DL) and an adder circuit 69. The delay time of the second delay circuit 68 is controlled by the latch circuit output signal 10a so as to correspond to the forward / reverse phase shift of the burst signal. When the delay time is low, the delay time is set to 1H-Ｈλ, In this case, the input signal is set to 1H + λλ, so that the phase of the input signal coincides with the phase of the signal obtained through the second delay circuit 68, and these signals are added by the adding circuit 69 to obtain the output signal. Thus, it is possible to obtain an output signal in which a signal component effective for a crosstalk component is emphasized.

Then, the comb filter described above is used in FIG.
Medium, by interposing between the AD conversion circuit 50 and the filter circuit 51 or interposing between the filter circuit 51 and the binarization circuit, crosstalk interference can be reduced, and the The phase of the burst signal can be detected.

[0081]

As described above, according to the configuration of the present invention,
In particular, the switch circuit outputs the reproduced video signal obtained by demodulating the reproduced signal switched and output at the timing of the change of the first control signal immediately after the change of the second control signal by the time axis correction circuit. Since the writing and reading are performed every horizontal period, when reproducing the video signal from the magnetic recording medium using the first and second magnetic heads, an output video signal with improved skew generated at the switching timing of the two magnetic heads is provided. In particular, it is possible to provide a video signal magnetic reproducing apparatus capable of improving skew even in a line immediately after the switching timing.

[0082]

[0083]

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a main part of a reproduction system of a VTR according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of a second time axis correction circuit 8 according to the first embodiment.

FIG. 3 is a timing chart for explaining a delay time T of a delay circuit 12;

4 is a timing chart for explaining a delay time T of the delay circuit 12. FIG.

FIG. 5 is a block diagram for explaining an operation of a second time axis correction circuit 8 according to the second embodiment.

FIG. 6 is a timing chart for explaining a first method relating to noise removal.

FIG. 7 is a timing chart for explaining a second method relating to noise removal.

FIG. 8 is a timing chart for explaining a third method relating to noise removal.

FIG. 9 is a timing chart for explaining a fourth method relating to noise removal.

FIG. 10 is a block diagram for explaining a main part of a color signal system 5 according to a third embodiment.

FIG. 11 is a block diagram for explaining a burst phase detection circuit AA.

FIG. 12 is a timing chart for explaining a burst phase detection circuit AA.

FIG. 13 is a block diagram for explaining a color rotation process BB.

FIG. 14 is a timing chart for explaining the operation of the 2-bit Bit counter circuit 66.

FIG. 15 is a timing chart for explaining improvement of an APC error by a time axis correction circuit.

FIG. 16 is a block diagram for explaining a comb filter.

FIG. 17 is a conceptual diagram for explaining a tape pattern during special reproduction.

FIG. 18 is a block diagram of a conventional video signal magnetic reproducing apparatus.

FIG. 19 is a timing chart for explaining head switching during a horizontal blanking period.

FIG. 20 is a timing chart for explaining a problem of a reproduced luminance signal.

FIG. 21 is a conceptual diagram for explaining a problem of a reproduced color signal.

[Explanation of symbols]

 Reference Signs List 1 switch circuit 2 FM level detection circuit (amplitude detection circuit) 7 luminance signal reproduction system (video signal reproduction processing circuit) 7a reproduction luminance signal (reproduction video signal) 9a horizontal synchronization signal 12 delay circuit 8 second time axis correction circuit ( Time axis correction circuit) 82 to 85 First to fourth memories (plural memories) 86 (writing means, reading means) H1 first magnetic head H3 second magnetic head (third magnetic head)

Claims (1)

(57) [Claims] 1. A video signal magnetic reproducing apparatus for reproducing a video signal from a magnetic recording medium using first and second magnetic heads, wherein a reproduced signal relating to the first magnetic head and a second magnetic head A switch circuit for switching and outputting the reproduction signal, a video signal reproduction processing circuit for demodulating a signal output from the switch circuit and outputting a reproduction video signal, and a synchronization signal for separating a horizontal synchronization signal from the reproduction video signal Minute
A separation circuit, a time axis correction circuit for writing the reproduced video signal every horizontal period using a clock following the jitter of the reproduced video signal, and outputting an output video signal obtained by reading with another clock; A delay circuit for outputting a first control signal obtained by delaying a synchronization signal by a predetermined time; and comparing an amplitude of a reproduction signal relating to the first magnetic head with an amplitude of a reproduction signal relating to the second magnetic head. And an amplitude detection circuit for outputting a second control signal obtained as described above, wherein the switch circuit switches and outputs the signal in accordance with the first and second control signals.