GB2231981A - Memory read/write arrangement - Google Patents

Abstract

A first in first out (FIFO) memory is provided with the Fig 2 generation means for flags FFINT, EFINT indicative of a full or empty memory. The flags are generated by sensing the proximity of read and write pointers. A look-ahead scheme uses the result of the proximity sensing to set up external flags one read or write cycle in advance of the full or empty condition. A half-full flag may also be generated. The proximity sensed may be that the pointers are on the same memory cell row and in adjacent, or adjacent plus one, columns; or that the pointers are on adjacent rows with one pointer at one end column and the other pointer at the opposite end or next-to-end column. <IMAGE>

Description

LOOK-AHEAD FLAG GENERATION IN A MEMORY STORE This invention relates to integrated circuit memories, and in particular to a read/write arrangment for a first in first out (FIFO) memory.

A first in first out (FIFO) memory comprises an array of rows and columns of memory cells into which data are written in sequence. The memory cells are then read in the same sequence to recover the data from the memory. The arrangement thus functions as a buffer store in which the sequential order of the stored data is maintained. In order to preserve the correct data sequence, it is necessary to provide some means of controlling the timing of the read and write operations to ensure that, for example, reading does not overtake writing and cause corruption of data. It is also desirable to indicate the occurence of a full ormempty condition of the memory by corresponding signals commonly referred to as 'flags'.

Conventionally this controlling mechanism is achieved by comparing the numbers of read and write cycles completed, or partially completed, at the beginning of every new read or write cycle. If the difference is zero, an empty flag is output, and further read cycles are disabled until the difference is non-zero. Likewise if the difference is the same as the memory size, a full flag is output and further write cycles are disabled until the difference is less than the memory size. This conventional technique is very slow to generate firstly the difference value and secondly rhe flag from the difference value. In addition, this conventional technique does not provide a look-ahead facility indicative that the memory is approaching a full or empty condition.

The object of the invention is to minimise or to overcome this disadvantage.

According to the invention there is provided a first in first out (FIFO) memory store, including an array of memory cells, means for writing data into and reading data from the memory cells, a read pointer for identifying a cell from which data is to be read, a write pointer for identifying a cell into which data is to be written, and means for determining the relative memory locations of those cells identified by the pointers whereby to generate a look-ahead signal indicative of a full or empty memory, when said identified cells are separated by a predetermined spacing in the memory array.

According to the invention there is further provided a first in first out memory store, including an array of rows and columns of memory cells,means for writing data sequentially into the memory cells, means for reading sequentially the written data from the memory cells, first row and column counters for generating a read pointer whereby a cell to be read is identified, second row and column counters for generating a write pointer whereby a cell to be written into is identified, means for determining one or other of the conditions that the cells identified by the read and write pointers are on the same row and in adjacent columns or on adjacent rows and or opposite end columns of the array, and means responsive to the detection of said one or other conditions for generating an output signal indicative of that condition prior to commencement of a next write or read operation.

The read and write pointers may be coded so that the predetermined spacing" condition occurs one cycle before the last read or last write cycle. By detecting this spacing condition in the memory and latching out an internal flag signifying this condition at the next falling edge of the write signal (for full flag) or the read signal (for empty flag) a look-ahead function is provided. The memory may be employed e.g.

as a buffer store in a high speed data processing system.

An embodiment of the invention will now be determined with reference to the accompanying drawings in which: Fig. 1 is a schematic diagram of a FIFO memory incorporating full and empty look-ahead flag generation; Fig. 2 shows the full and empty flag generation circuitry of the memory of Fig. 1; and Figs. 3 and 4 are timing diagrams corresponding to the flag generation circuit of Fig. 2: Referring to Fig. 1, the FIFO memory includes an array 11 of n rows and rn columns of typically dual port memory cells accessible via row and column read decoders 12, 13 and row and column write decoders 14, 15.

Ring-counters 16 and 17 are associated with the row and column read decoders 12 and 13 respectively.

The ring-counter 16 is as long as the number of rows, n and ring counter 17 is as long as the number of columns m. Thus single logic 1 'bits' in 16 and 17, representing the current read row and column locations, can be thought of as forming a read pointer into the memory (R in Fig. 1), indicating the memory cell currently being read from or last read from.

The same is true of ring counters 18 and 19 providing a write pointer W, indicating the memory cell currently being written to or last written to.

The read (R) and write (W) pointers are coded such that, when they are pointing to adjacent ot "one-apart" sequential memory locations, the memory is either about to become empty or about to become full, on the next read or write cycles, respectively. If the pointers are such that the read pointer R is one location ahead of the write pointer W, the memory will become full on the next write cycle. If the read pointer R is one location behind the write pointer W the memory will become empty on the next read cycle. By detecting this one-apart condition and the sequential orientation of the pointers, an empty or full signal is generated one cycle before it is required, provided the look-ahead provision.Latching out this empty or full signal on the next write (for full flag) or read (for empty flag) cycle, allows the flags to be output very early during these last cycles, giving an early warning of the approach of these error conditions. Flag generation is performed by generator circuit 20 which will be described below with reference to Fig. 2.

Referring now to Fig. 2, the flag generation circuit, 20, of the memory of Fig. 1, consists of several large input term OR gates (21,22,23,24), driven from combinations of the outputs of ring-counters 16,17,18,19 in Fig. 1. The exact combinations are illustrated in Fig. 2 where Wcx represents the output of the xth bit of the write column ring-counter 19 and Wrx represents the xth bit of the write row ring counter 18 and so on. In Fig. 2 standard logic symbols are used to represent the gates and latches.

Fig. 2 assumes a typical memory whete the number of rows n = 64, and the number of columns m = 16, giving a total of 1024 locations. The column ring-counters 17 and 19 are clocked once every read/write cycles respectively, whilst the row ring-counters are clocked once every m cycles.

To detect that the read and write pointers are one location apart, the circuit looks for one of the following conditions; - Both read and write pointers on the same row and in adjacent columns.

- Pointers on adjacent rows and pointers at opposite ends of their respective rows.

In addition, because of the uncertainties involved with look-ahead circuits, described later, the circuit may also advantageously detect the condition that the pointers are two locations apart. To detect the "two-apart" condition the circuit looks for the following options; - Both read and write pointers on the same row and in adjacent plus one columns.

- pointers on adjacent rows and one pointer at a row end and the other pointer one location away from the opposite end of its row.

These conditions are detected and OR'ed together by the OR gates, which perform a boolean F(A.B) + (c.D) ] / operation, to produce the signals EF1, EF2, FF1, FF2, which are effectively OR'ed together by NAND gates 29, 210 to produce an, active high, look-ahead flag signal EFINT and FFINT. These signals are latched out on the appropriate edges of the read (for empty flag) and write (for full flag) cycles. As, for example, the memory cannot be empty after the completion of a valid write cycle, the rising (completing) edge of write clock (vow/) is used to reset the empty flag output latch 211. The reset on latches 211 and 212 are sensitive to the rising edge of the read/write clocks (VR/ and Vow/) only, not to the level of the clocks.

In this embodiment the NOR gates 221-224 are used to minimise the logic for determining the orientation of the pointers. The signals HFF and HFF/ are complementary and indicate whether the memory is greater than or less than half full. HFF and HFF/ are generated in the same way as the empty and full flags by the use of coded pointers and look-ahead techniques.

When the memory is greater than half full, any read cycle cannot be the last one before an empty condition, so no empty flag can occur. Likewise when the memory is less than half full any write cycle cannot be the last one before a full condition, so no full flag can occur.

If desired, the half full/empty flags can be latched out in the same way as the full and empty flags.

The components 213-220, 230-233 are used to overcome uncertainties in the look-ahead scheme, described below.

The look-ahead scheme described above with reference to Fig. 2 is intended to predict the outcome of future read or write cycles. However, under certain startup or end conditions, the use of a simple one-apart pointer detection can result in errors. These possible error conditions are summarised as; - Long write (read) cycle approaching empty (full).

- Second write from empty / second read from full The long read/write approaching full/empty problem is illustrated in Fig. 3. The problem occurs if a long write cycle (read cycle) is still active, aa several read cycles (write cycles) are executed approaching the empty (full) condition. The EF1 (FF1) signal, representing the one-apart signal can occur one cycle too late because the write (read) cycle has not completed even though the read and write pointers have been updated. The EF2 (FF2), two-apart signal, is used in this circumstance (when write (read) is low) to generate the look-ahead signal which can be latched out at the, apparent one-apart, next read (write) cycle.

Fig. 3 also shows that the latched version of the empty (full) flag is reset at the completion of the long write (read). releasing the internal read clock to read out the recently written data.

The second write (read) from empty (full) problem, is illustrated with reference to Fig. 4. This demonstrates how the circuits formed by 213,214,215, 216,230,231 and 217,218,219,220,232,233 (Fig. 2) produce a pulse, generated from the two-apart signal, to fill up the gap formed between the one apart signal going high and the end of the second write pulse, during which thew start of a read cycle would otherwise latch out an incorrect value of the empty (full) flag. This pulse, being OR'ed with the one-apart or EF1 (FF1) signal, extends EFINT (FFINT) over the required period.

Although the look-ahead flag generation technique has been described with particular reference to a semi-conductor memory, it will be appreciated that it can be applied to other memory devices.

Claims (6)

1. A first in first out (FIFO) memory store, including an array of memory cells, means for writing data into and reading data from the memory cells, a read pointer for identifying a cell from which data is to be read, a write pointer for identifying a cell into which data is to be written, and means for determining the relative memory locations of those cells identified by the pointers whereby to generate a look-ahead signal indicative of a full or empty memory, when said identified cells are segmented by a predetermined spacing in the memory array.

2. a first in first out memory store, including an array of rows and columns of memory cells,means for writing data sequentially into the memory cells, means for reading sequentially the written data from the memory cells, first row and column counters for generating a read pointer whereby a cell to be read is identified, second row and column counters for generating a write pointer whereby a cell to be written into is identified, means for determining one or other of the conditions that the cells identified by the read and write pointers are on the same row and in adjacent columns or on adjacent rows and or opposite end columns of the array, and means responsive to the detection of said one or other conditions for generating an output signal indicative of that condition prior to commencement of a next write or read operation.

3. A FIFO memory as claimed in claim 1 or 2, wherein said look-ahead signal is generated in response to the condition that one memory cell is disposed between the cells identified by the read and write pointers.

4. A FIFO memory as described in claim 1, 2 or 3 and including means for generating a further signal indicative of a half full memory.

5. A first ir. first out memory store substantially as described herein with reference to and as shown in the accompanying drawings.

6. Is data processing system incorporating one or more memory stores as claimed any one of claims 1 to 5.