GB2199469A

GB2199469A - Clock signal generator

Info

Publication number: GB2199469A
Application number: GB08630817A
Authority: GB
Inventors: Stewart Frederick Bryant
Original assignee: Philips Electronic and Associated Industries Ltd
Current assignee: Philips Electronics UK Ltd
Priority date: 1986-12-23
Filing date: 1986-12-23
Publication date: 1988-07-06
Also published as: GB8630817D0

Abstract

A clock signal generator for an asynchronous data interface (UART) comprises an oscillator (4) feeding a binary divider (6) which has presettable inputs to enable the divisor to be adjusted. The presettable inputs of the divider (6) are fed from parallel outputs of an up/down counter (9). The up/down counter (9) also has presettable inputs to which an input terminal (8) is connected to allow the up/down counter (9) to be set to a predetermined state dependent on the nominal clock frequency. When a data character is received over a data bus (11) it is read into a first in first out memory FIFO (10). Each character is read out in turn from the FIFO (10) at a rate which is dependent on the clock frequency at the output of divider (6). Each time a character is read into the FIFO (10) the up/down counter (9) is incremented while each time a character is read out from the FIFO (10) the up/down counter (9) is decremented. Thus the number to which the divider (6) is preset is increased or decreased and hence the frequency at its output is increased when a character is read into the FIFO (10) and decreased when a character is read out from the FIFO (10). Therefore the clock frequency stabilises at a value which causes characters to be read out from the FIFO (10) at the same rate as characters are read into the FIFO (10). <IMAGE>

Description

CLOCK SIGNAL GENERATOR The invention relates to an arrangement for generating a clock signal for an asynchronous data interface.

When data is to be transmitted from a first to a second asynchronous data terminal character over-run may occur unless precautions are taken to lock the outgoing character rate to the incoming character rate.

It is an object of the invention to enable the provision of a clock signal generator which enables the incoming and outgoing character rates to be locked.

The invention provides an arrangement for generating a clock signal for an asynchronous data interface, said arrangement comprising an oscillator from which the clock signal is derived, a first in first out memory having an input for receiving transmitted characters and an output for entering characters into the data interface, means for increasing the clock frequency when a character is read into the memory, and means for decreasing the clock frequency when a character is read out of the memory.

By varying the clock frequency applied to the data interface in response to the number of incoming and outgoing characters character over-run can be averted.

The output of the oscillator may be connected to a frequency divider whose output provides the clock signal.

The frequency divider may have presettable inputs which determine its divisor, the signals at the presettable inputs being arranged to set the divisor to a desired value each time the divider adopts a given state so that the divisor is increased or decreased depending on whether a character has been read into or read out of the memory.

The arrangement may further comprise an up/down counter having parallel outputs which are connected to the presettable inputs of the frequency divider, the state of. the up/down counter being incremented in one direction when a character is read into the memory and in the other direction when a character is read out of the memory.

An embodiment of the invention will now be described, by way of example, with reference to the accompanying drawing, the sole Figure of which shows in block schematic form an arrangement for transmitting data from a first to a second asynchronous data terminal, the arrangement including an arrangement for generating a clock signal according to the invention.

The Figure shows an arrangement for transmitting data between first and second asynchronous data terminals 1 and 2.

The output of the data terminal 1 is connected to the receiver input RI of an asynchronous data interface (or UART) 3. In a particular implementation of the arrangement shown in the Figure the UART 3 was that sold by Texas Instruments under the type number TMS 6011 and the references shown for the inputs and outputs are as specified in the data sheet for that device. A high frequency clock signal is generated by a clock generator 4 and fed to clock inputs of first and second counters 5 and 6.

The terminal count output of counter 5 is fed to the receiver clock input RC of the UART 3. The terminal count output of counter 6 is connected to its parallel load input and to the transmitter clock input TC of a further asynchronous data interface (or UART) 7 whose transmitter output TO is connected to the data terminal 2. Both counters 5 and 6 have parallel presettable inputs to enable their division ratios to be set to a desired value and act as frequency dividers to divide the frequency of the master clock generator 4 to provide appropriate clock signals to the UARTS 3 and 7. The preset inputs of counter 5 are connected to an input 8 which is also connected to preset inputs of an up/down counter 9 whose outputs are connected to the preset inputs of the counter 6.The data ready DR output of the UART 3 is connected to the load input LJ of a first in first out memory (FIFO) 10 via a line 12 and to an input of the counter 9 which when operated causes the counter 9 to increment. The receiver outputs R01-R08 of UART 3 are connected to the memory inputs of the FIFO 10. The memory outputs of the FIFO 10 are fed to the transmitter inputs Tll-T18 of the UART 7. The transmitter buffer register empty flag TBRE is connected to the shift out SO input of the FIFO 10 while the output ready output OR of the FIFO 10 is connected to the transmitter buffer register load input TRBL of the UART 7.

When transmission between two asynchronous terminals takes place it is necessary to compensate for differences in the clock frequencies between the terminals to prevent the loss of data.

Data from the terminal 1 is applied to the RI input of UART 3 in serial form and clocked into the receiver register under the control of the clock signal produced at the output of counter 5 and applied to the input RC of the UART 3. The clock generator 4 generates a high frequency clock signal which is divided by the counter 5 by a factor dependent on the data applied to its preset inputs va the input 8. This enables the selection of different transmission rates by appropriately selecting the division factor of the counter 5. For example for a 1200 band transmission rate RC and TC should be 16x1200 or 19.2kHz. A system clock of 9.8304MHz gives a division factor of 512 for counters 5 and 6.

When a data word has been assembled in the receiver register of UART 3 it is transferred to the receiver buffer register for output to the data bus 11 from outputs R01 to R08. This assumes an 8-bit word. With the UART specified this is the maximum number of parallel outputs but clearly alternative arrangements providing a greater or lesser number of outputs could be used.

The data is passed over a bus 11 to the input of FIFO 10 and read into the FIFO 10 by the DR signal from UART 3 applied to the LOAD input of the FIFO 10. This signal is also applied to the up/down conter 9 to cause it to increment by one each time a character is read into the FIFO 10. This increases the number applied to the preset inputs of counter 6 and thus will cause the terminal count of counter 6 to be reached sooner and consequently the clock signal applied to the input TC of UART 7 will be increased in frequency.

When the UART 7 is ready to take a character at inputs T11 to T18 it generates a signal at output TBRE which is applied to input SO of the FIFO 10. The FIFO 10 then generates an output signal at output OR which is applied to input TBRL of the UART 7 to cause a character to be transferred from the FIFO 10 to the inputs T11 to T18 of the UART 7. The signal at output OR of the FIFO 10 is also applied to an input of the up/down counter 9 to cause its count to decrement by one. This decreases the number applied to the preset inputs of the counter 6 and thus will cause the terminal count of the counter 6 to be reached later and consequently the clock signal applied to the UART 7 will be decreased in frequency.

Clearly if characters are read into the FIFO 10 at the same rate as they are read out then the average count of the up/down counter will remain constant and hence the frequency of the clock signal applied to input TC of UART 7 will be constant. The clock frequency produced by counter 6 will stabilise at a value which causes characters to be read out of the FIFO 10 at the same average rate as they are read in.

If the two UARTS 3 and 7 are connected by a transmission path which comprises the data bus 11 and the line 12 and each UART has its own clock generator, i.e. two separate clock generators 4 one for each UART, the arrangement of counter 6, up/down counter 9, and FIFO 10 will allow the synchronisation of the clock produced by counter 6 with that produced by counter 5 without a physical connection between the two. The preset input 8 would, of course, be replaced by separate preset inputs at each end of the transmission channel.

From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the design and use of data transmission systems and devices and component parts thereof and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation or modification of one or more of those features which would be obvious to persons skilled in the art, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims

CLAIM(S)

1. An arrangement for generating a clock signal for an asynchronous data interface, said arrangement comprising an oscillator from which the clock signal is derived, a first in first out memory having an input for receiving transmitted characters and an output for entering characters into the data interface, means for increasing the clock frequency when a character is read into the memory, and means for decreasing the clock frequency when a character is read out of the memory.

2. An arrangement as claimed in Claim 1, in which the output of the oscillator is connected to a frequency divider whose output provides the clock signal.

3. An arrangement as claimed in Claim 2, in which the frequency divider has presettable inputs which determine its divisor and the signals at the presettable inputs are arranged to set the divisor to a desired value each time the divider adopts a given state so that the divisor is increased or decreased depending on whether a character has been read into or read out of the memory.

4. An arrangement as claimed in Claim 3, further comprising an up/down counter having parallel outputs which are connected to the presettable inputs of the frequency divider, the state of the up/down counter being incremented in one direction when a character is read into the memory and in the other direction when a character is read out of the memory.

5. An arrangement for generating a clock signal for an asynchronous data interface substantially as described herein with reference to the accompanying drawing.