GB2079534A - Package for semiconductor devices - Google Patents

Package for semiconductor devices Download PDF

Info

Publication number
GB2079534A
GB2079534A GB8110198A GB8110198A GB2079534A GB 2079534 A GB2079534 A GB 2079534A GB 8110198 A GB8110198 A GB 8110198A GB 8110198 A GB8110198 A GB 8110198A GB 2079534 A GB2079534 A GB 2079534A
Authority
GB
United Kingdom
Prior art keywords
package
base
leads
metallization pattern
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB8110198A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Publication of GB2079534A publication Critical patent/GB2079534A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
GB8110198A 1980-07-02 1981-04-01 Package for semiconductor devices Withdrawn GB2079534A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16545780A 1980-07-02 1980-07-02

Publications (1)

Publication Number Publication Date
GB2079534A true GB2079534A (en) 1982-01-20

Family

ID=22598970

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8110198A Withdrawn GB2079534A (en) 1980-07-02 1981-04-01 Package for semiconductor devices

Country Status (6)

Country Link
JP (1) JPS5745263A (de)
DE (1) DE3123844A1 (de)
FR (1) FR2486307A1 (de)
GB (1) GB2079534A (de)
IT (1) IT8167917A0 (de)
NL (1) NL8102871A (de)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0116117A2 (de) * 1982-10-21 1984-08-22 Abbott Laboratories Verfahren zum Herstellen elektrischer Verbindungen an einer Halbleiteranordnung
US4547795A (en) * 1983-03-24 1985-10-15 Bourns, Inc. Leadless chip carrier with frangible shorting bars
WO1989008324A1 (en) * 1988-02-29 1989-09-08 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
US4987475A (en) * 1988-02-29 1991-01-22 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
FR2750798A1 (fr) * 1996-07-02 1998-01-09 Sgs Thomson Microelectronics Boitier a faible cout pour circuits integres fabriques en petite quantite

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6263455A (ja) * 1985-09-13 1987-03-20 Hitachi Cable Ltd リ−ドフレ−ムの製造方法
JPS6422043U (de) * 1987-07-30 1989-02-03

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH526203A (it) * 1968-11-06 1972-07-31 Olivetti & Co Spa Procedimento di montaggio di uno o più circuiti elettronici integrati in un contenitore
US3550766A (en) * 1969-03-03 1970-12-29 David Nixen Flat electronic package assembly
GB1258870A (de) * 1969-09-29 1971-12-30
US3760090A (en) * 1971-08-19 1973-09-18 Globe Union Inc Electronic circuit package and method for making same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0116117A2 (de) * 1982-10-21 1984-08-22 Abbott Laboratories Verfahren zum Herstellen elektrischer Verbindungen an einer Halbleiteranordnung
EP0116117A3 (en) * 1982-10-21 1985-09-18 Abbott Laboratories A method of establishing electrical connections at a semiconductor device
US4547795A (en) * 1983-03-24 1985-10-15 Bourns, Inc. Leadless chip carrier with frangible shorting bars
WO1989008324A1 (en) * 1988-02-29 1989-09-08 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
US4987475A (en) * 1988-02-29 1991-01-22 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
FR2750798A1 (fr) * 1996-07-02 1998-01-09 Sgs Thomson Microelectronics Boitier a faible cout pour circuits integres fabriques en petite quantite

Also Published As

Publication number Publication date
FR2486307A1 (fr) 1982-01-08
NL8102871A (nl) 1982-02-01
IT8167917A0 (it) 1981-07-01
DE3123844A1 (de) 1982-04-08
JPS5745263A (en) 1982-03-15

Similar Documents

Publication Publication Date Title
US4608592A (en) Semiconductor device provided with a package for a semiconductor element having a plurality of electrodes to be applied with substantially same voltage
US5227662A (en) Composite lead frame and semiconductor device using the same
US4681656A (en) IC carrier system
US4700276A (en) Ultra high density pad array chip carrier
US3872583A (en) LSI chip package and method
US4876588A (en) Semiconductor device having ceramic package incorporated with a heat-radiator
US5861670A (en) Semiconductor device package
US4115837A (en) LSI Chip package and method
US4855869A (en) Chip carrier
JP2956786B2 (ja) 合成ハイブリッド半導体ストラクチャ
GB2079534A (en) Package for semiconductor devices
EP0027017B1 (de) Kapselung für eine integrierte Halbleiterschaltung
US20060125076A1 (en) Circuit boards, electronic devices, and methods of manufacturing thereof
US4652977A (en) Microelectronics module
JPH09307051A (ja) 樹脂封止型半導体装置及びその製造方法
US5345038A (en) Multi-layer ceramic packages
US5045639A (en) Pin grid array package
JP3210503B2 (ja) マルチチップモジュールおよびその製造方法
JP3470852B2 (ja) 配線基板とその製造方法
EP0100727B1 (de) Halbleiteranordnung mit einem keramischen Träger
JPS6153746A (ja) 半導体装置
JP2575749B2 (ja) 半導体装置におけるリードの製造方法
JP2710893B2 (ja) リード付き電子部品
JP2543149Y2 (ja) 半導体素子収納用パッケージ
JP2546400B2 (ja) 半導体用セラミックパッケージ

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)