GB1567772A

GB1567772A - Data processing systems utilising virtual addressing

Info

Publication number: GB1567772A
Application number: GB2084076A
Authority: GB
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1975-05-28
Filing date: 1976-05-20
Publication date: 1980-05-21
Also published as: FR2312820B3; AT360254B; IT1081081B; FR2312820A1; DE2523686A1; CH601858A5; BE842320A; NL7605610A; ATA332776A

Description

(54) IMPROVEMENTS IN OR RELATING TO DATA PROCESSING SYSTEMS UTILISING VIRTUAL ADDRESSING (71) We, SIEMENS AKTIENGESELL scHFr, a Germany Company, of Berlin and Munich, Federal Republic of Germany, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to a data processing system utilising virtual addressing, and in particular to address translation in such a system having a plurality of processors.

Virtual addressing data processing systems are based on a working store of theoretically arbitrary size, the so-called virtual store, which is divided into zones of equal size, so-called pages, and whose entire contents are located in a backing store of the system.

Only those pages of the virtual store which contain currently required commands or operands of a running programme are in each case transferred into the physical working store, which likewise is divided into pages of equal size.

Virtual addressing can be used effectively in particular when a plurality of programmes are to be processed simultaneously. In this case each user and each programme is provided with its own virtual store, and the virtual store pages are not permanently assigned to the pages of the physical working store but their contents are transferred into currently free pages of the physical working store only when required. Therefore the virtual addresses of commands or operands are assigned to the physical working store addresses via address tables, so-called translation tables, which are prepared for each programme sequence.

The great advantage of virtual addressing consists in that each of the simultaneously running programmes can employ the whole of its virtual storage and address space apparently unrestrictedly. The changes from one user programme to another and the address translation routines remain invisible to the user, i.e. they do not require to be taken into account in the user programmes.

However, in a virtual addressing data processing system, with each access to the physical working store it is necessary to run a translation routine which under certain circumstances may be very time consuming, and which can also comprise several stages using chained translation tables. In the latter case, with a large store, each address translation employs a plurality of translation tables, stage by stage, and necessitates a number of auxiliary accesses to the working store which delay and impede the actual access to the physical working store.

In multi-processor systems, i.e. data processing systems having a ,plurality of processors, the individual processors process various programmes independently of one another and compete with one another for access to the common working store. If the possibility of virtual addressing is provided in such systems, the normal practice is to assign each procsesor a permanently wired address translation control unit which contains extracts from the translation tables currently in use. This restricts the number of store auxiliary accesses of the individual processors and thus reduces the load on the working store interface.

This manner of address translation gives rise to problems in that whilst one processor is modifying a translation table, another processor can use the as yet unchanged extract of this translation table in its own address translation control unit in the course of a translation routine, resulting in a wrongly translated virtual address, and in that one processor can inspect a translation table in the working store in order to check on an extract for its own address translation control unit, but if, during this period of time, this translation table is modified by another processor during the course of an address translation, it cannot be ruled out that the first processor will intermediately store as an extract of the translation table a table entry which is then no longer valid.

In order to allow for these known problems programming conventions with "seizure" and "release" of translation tables have been established and special commands have been introduced which serve on the one hand to eliminate specific fault sources and on the other hand to allow faults which have occurred to be recognised as such, to enable them to be corrected. However, such programming regulations limit the flexibility of the system, and the elimination of faults which have occurred necessitates performance-restricting tests and fault routines.

This invention seeks to provide a data processing system utilising virtual addressing and having a plurality of processors, in which it is possible to achieve a simplified administration and handling of the translation tables in address translation routines without limiting regulations and at the same time to eliminate further fault sources thus reducing the frequency of fault routines.

According ot this invention there is provided a data processing system having a plurality of processors, a working store and a backing store, utilising virtual addressing for a plurality of individual programmes pages of which are transferred as necessary from the backing store to the working store, the working store also serving to store translation tables in which an assignment of virtual addresses to real working store addresses is established for every running programme, wherein the working store is directly assigned a single central address translation control device arranged in operation, independently without the cooperation of a processor requesting a store access, to translate virtual addresses into real addresses with which access is gained to the working store for the purpose of write-in and readout of address contents and via which address translation control device each processor can modify the content of the address translation tables, and a central access control device which, when a processor obtains access to the address translation control device, is arranged to block access to the address translation control device of all other processors for the duration of this access.

In such a system the address translation is not carried out individually in the processor but centrally. For this purpose the working store is assigned the central address translation control device, which operates with the translation table without the cooperation of the processor, and preferably itself stores frequently employed extracts from the address translation tables. By "frequently employed extracts" is meant extracts which are used for address translation during the running of programmes with at least a predetermined frequency.

The processors address the working store directly with virtual addresses. In known manner all the processors compete for accesses to the working store, but in this case to the central address translation control device of the working store. At any given time this device may be operative to effect an address translation in respect of a specific requesting processor, in which case accesses in respect of all other processors are blocked. In view of the integration of the address translation into the region of the working store, it is not possible for the above-mentioned problems to occur so that limiting programming conventions and special commands which were previously necessary to overcome these problems are no longer required.

Preferably a processor requesting a store access is arranged to seize the access control device as soon as this is free and thereupon to send to the device a programme characteristic which serves to identify a particular running programme, a virtual address, and a write or read command, and wherein the address translation control device is arranged to form from the programme characteristic a start address of a translation table assigned to the identified programme, from this start address and a part of the virtual address to read out a specific entry from the relevant translation table, to test such read-out entry to establish whether an access fault exists, to report to the requesting processor any such fault, and, only in the case of a faultfree address translation, to form from this specific entry and a further part of the vritual address a real address for access to the working store and to release the access control device at the end of such access.

This takes into account the use of the address translation control device which is centralised in the working store by a plurality of programmes which possess their own sets of translation tables.

Preferably, a processor requesting a store access is arranged to seize the access control device as soon as this is free and thereupon to send to the device a programme characteristic which serves to identify a particular running programme, a virtual address, and a write or read command, and wherein the address translation control device is arranged to effect a multi-stage address translation, with hierarchically classified translation tables, in which it forms from the programme characteristic a start address of a first translation table assigned to the identified programme, carries out at least once the step of using the latest start address and a part of the virtual address to read out an entry from the relevant translation table to form a new start address of another translation table and utilises the final start address thus obtained, together with a further part of the virtual address, to read out a specific entry from the final translation table, from this specific entry and a further part of the virtual address to form a real addrcss for access to the working store, and to release the access control device at the end of such access, and is furthermore arranged to test each such read-out entry to establish whether an access fault exists, to report to the requesting processor any such fault, and to form said real address only in the case of a fault-free address translation. This takes into consideration in particular the fact that an address translation generally necessitates at least two consecutive accesses to translation tables which are chained to one another. In the case of an address translation in the working store, the usually necessary long transfer times for the access parameters and the read-out table entries on the path between the processor and the working store are then dispense with, i.e. the working store interface is subjected to a lighter load.

Even in a system in accordance with this invention the nature of the address translation can not completely eliminate in particular non-systematic fault sources. These faults do not become manifest until during the course of the address translation and their elimination requires firstly the running of an operating system routine and then the repetition of the command previously run faultily. Therefore in known processor-individual address translation devices, by way of a precaution, address translations are carried out without working store access with the translated address so that programme faults can be recognised earlier and then the command can be broken off before the results of a fault become apparent. Thus in known data processing systems the command remains repeatable.

In a system in accordance with this invention a more general safeguarding of the possibility of repeating a command is necessary than is the case in known systems with processor-individual address translation devices. The fact that this is possible can be gathered from German Specification No.

2,523,795 which describes the repeated execution of commands in a processing unit of data processing system in the event of a fault, thus ensuring an unrestricted recur rence of commands because parameters and operands of a command remain available until the result is fault-free.

The invention will be further understood from the following description by way of example of an embodiment thereof with reference to the accompanying drawings, in which: Fig. 1 shows a greatly simplified schematic Mock diagram of parts relevant to the present invention of a multi-processor data processing system; Fig. 2 schematically illustrates data and control information transmitted via a store interface in the event of a store access of a processor in such a system; Fig. 3 is a time-orientated flow diagram illustrating address translations in respect of two requesting processors; and Fig. 4 is a functional flow diagram of an address translation in association with a store access for a "read" operation.

Referring to Fig. 1, in a multi-processor data processing system utilising virtual addressing a plurality of processors P1 to PN compete for access to a common working store ASP. The working store ASP is of modular construction and in its part which is invisible to the user contains for each of the running programmes, translation tables arranged arbitrarily and indicated purely schematically by blocks AT1 and ATN. It is assumed here that the translation table AT1 is assigned to the processor P1 and the translation table ATN is assigned to the processor PN. The translation tables AT1 and ATN are identified by indicators Z1 and ZN respectively which refer to base addresses of these translation tables.

As the processors P1 to PN are to gain access to the working store ASP with virtual addresses, the working store is directly assigned a central address translation control unit AST, in which the entire address translation routine is run without the cooperation of a requesting processor, and an access control unit ZST which enables the address translation control unit for one of the requesting processors P1 to PN and blocks requests of all other processors for the duration of the relevant address translation. As control devices for address translation and for accesses of competing processors to a specific common unit are known per se it is not necessary to describe these devices here in further detail.

It is in fact sufficient for an understanding of this invention to refer here merely to the items of data and control information which are required by the two devices ZST and AST, to which end reference is made to Fig. 2 which fundamentally shows the individual data and information groups which must be transmitted via the store interface in the case of an access of a processor PN to the working store ASP in one or in both directions. The requesting processor transfers to the working store not only the virtual store address ADR and a command COM stipulating the nature of the store access, i.e. "read" or "write" but also a programme characteristic PRZ which defines the programme running in the requesting processor and thus refers to a specific translation table, e.g. ATN. This programme characteristic PRZ is interpreted in the same way as the indicator e.g. ZN shown in Fig. 1; i.e. a base address for a specific translation table, in this example the translation table ATN, can be obtained therefrom.

In addition to further items of control information STJ and fault messages FM which are normally always transmitted via interfaces in both directions, the actual store data are also transmitted via the interface, either as write-in data SD from the processor PN to the working store ASP or as readout data LD from the working store ASP to the requesting processor PN.

Fig. 3 illustrates time conditions in the case of competing store accesses by requesting processors. By way of simplification the seizure of the working store ASP has been shown for requests by two processors P1 and P2. In the time flow shown by the time axis t, from top to bottom, firstly a request by the processor P1 for access to the working store is handled during a period P11. During this period Pil, in the working store ASP, in a time section Al initially the access control unit ZST is seized so that a possible request by another processor, e.g.

the processor P2, is blocked.

In a following time section A2 the address translation is carried out in the working store ASP. This is followed by a time section A3 for the actual store access whereupon. in a time section A4, the access control unit ZST is released again.

It is assumed in this example that at the start of a period P20 the processor P2 makes a request, and consequently during this period the processor P2 awaits the release of the access control unit ZST and seizes this at the beginning of a period P21, during which in the time sections Alto A4 the same processes take place in the working store ASP as described above. Following the release of the access control unit ZST in the time section A4 of period P21 the processor P1, which has meanwhile made a further request and consequently awaits a store access during a period P10, again seizes the access control unit at the start of a further period P11.

In accordance with this illustration of the time flow of processor requests for store accesses, with the aid of the functional flow diagram illustrated in Fig. 4, an address translation for a "read" operation will be explained. The flow diagram is divided into two columns, the left-hand one of which illustrates all the process steps in which a processor PN requesting a store access participates and the right-hand one of which illustrates all those processes which take place solely within the working store ASP and its assigned access control unit ZST and address translation control unit AST.

Through one of the items of control information STJ represented in Fig. 2, the processor PN requests a store access which is released or blocked by the access control unit ZST. When the access control unit ZST is free and recognises this request it is thereby seized (these initial steps are not shown in Fig. 4). The processor PN then sends the working store ASP a programme characteristic PRZ which defines the programme running therein. a command COM, in this example a read command, which designates the store operation which is to be carried out, and the virtual address ADRV of the store position at which this operation is to be carried out.

In the address translation control unit AST firstly the translation table, in this case ATN, which is assigned to the programme running in the requesting processor PN is determined as a result of a base address.

This base address is then added to a specific distance address with the aid of a part of the virtual address ADRV to determine a specific row ATNX of the translation table ATN. The entry < ATNX > of this row ATNX is then read out and is tested. If the test indicates an obvious programme fault, a report is made back to the requesting processor PN. Although this is not shown in the drawing, this can give - rise to fault routines which lead to the breaking off of the store access and, following the determination and elimination of the fault, request a repetition of the store operation.

In the case of multi-stage address translations, i.e. with chained translation tables, the contents of the row ATNX indicate the base address of a following translation table.

In this case, as described above, from a part of the virtual address ADRV a specific row of the following translation table is established, the contents of which are read out and tested. In dependence upon the size of the address translation stages, this loop may have to be run through several times. Fig. 4 illustrates this by a broken line provided with arrows.

At the end of the address translation routine, the real address ADRR of a specific store position in the physical working store ASP is obtained from the contents (in this example (ATNX > ) of the last determined translation table row and a further part of the virtual address ADRV. The actual access to the working store ASP is thus possible.

Here again a test is carried out to establish whether an access fault exists, and if so the fault is reported back to the requesting processor PN.

In the case of satisfactory access to the working store ASP, now the nature of the store operation is determined from the com- mand COM received from the requesting processor PN. In this case of a read-out operation, the contents (ADRR > of the store position are read out with the estab lished real address ADRR, and are made available and transmitted to the processor PN. This concludes the store access, and the access control unit ZST is released, so that the working store ASP with its assigned devices ZST and AST is available for a further access.

WHAT WE CLAIM IS: 1. A data processing system having a plurality of processors, a working store and a backing store, utilising virtual addressing for a plurality of individual programmes pages of which are transferred as necessary from the backing store to the working store, the working store also serving to store translation tables in which an assignment of virtual addresses to real working store addresses is established for every running programme, wherein the working store is directly assigned a single central address translation control device arranged in operation, independently without the cooperation of a processor requesting a store access, to translate virtual addresses into real addresses with which access is gained to the working store for the purpose of write-in and readout of address contents and via which address translation control device each processor can modify the content of the address translation tables, and a central access control device which, when a processor obtains access to the address translation control device, is arranged to block access to the address translation control device of all other processors for the duration of this access.

2. A system as claimed in claim 1 wherein frequently employed extracts from the translation tables are stored in the central address translation control device.

3. A system as claimed in claim 1 or claim 2 wherein a processor requesting a store access is arranged to seize the access control device as soon as this is free and thereupon to send to the device a programme characteristic which serves to identify a particular running programme, a virtual address, and a write or read command, and wherein the address translation control device is arranged to form from the programme characteristic a start address of a translation table assigned to the identified programme, from this start address and a part of the virtual address to read out a specific entry from the relevant translation table, to test such read-out entry to establish whether an access fault exists, to report to the requesting processor any such fault, and, only in the case of a fault-free address translation, to form from this specific entry and a further part of the virtual address a real address for access to the working store and to release the access control device at the end of such access.

4. A system as claimed in claim 1 or claim 2 wherein a processor requesting a store access is arranged to seize the access control device as soon as this is free and thereupon to send to the device a programme characteristic whilch serves to identify a particular running programme, a virtual address, and a write or read command, and wherein the address translation control device is arranged to effect a multi-stage address translation, with hierarchically classified translation tables, in which it forms from the programme characteristic a start address of a first translation table assigned to the identified programme, carries out at least once the step of using the latest start address and a part of the virtual address to read out an entry from the relevant translation table to form a new start address of another translation table, and utilises the final start address thus obtained, together with a further part of the virtual address, to read out a specific entry from the final translation table, from this specific entry and a further part of the virtual address to form a real address for access to the working store, and to release the accesss control device at the end of such access, and is furthermore arranged to test each such read-out entry to establish whether an access fault exists, to report to the requesting processes any such fault, and to form said real address only in the case of a fault-free address translation.

5. A data processing system substantially as herein described with reference to the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. lished real address ADRR, and are made available and transmitted to the processor PN. This concludes the store access, and the access control unit ZST is released, so that the working store ASP with its assigned devices ZST and AST is available for a further access. WHAT WE CLAIM IS:

1. A data processing system having a plurality of processors, a working store and a backing store, utilising virtual addressing for a plurality of individual programmes pages of which are transferred as necessary from the backing store to the working store, the working store also serving to store translation tables in which an assignment of virtual addresses to real working store addresses is established for every running programme, wherein the working store is directly assigned a single central address translation control device arranged in operation, independently without the cooperation of a processor requesting a store access, to translate virtual addresses into real addresses with which access is gained to the working store for the purpose of write-in and readout of address contents and via which address translation control device each processor can modify the content of the address translation tables, and a central access control device which, when a processor obtains access to the address translation control device, is arranged to block access to the address translation control device of all other processors for the duration of this access.