DE19534155C1 - Microprocessor system circuitry testing method - Google Patents

Abstract

The testing method involves using a microprocessor system, comprising at least one central processing unit (CPU) and a nonvolatile memory (EPROM), that includes programs that comprise testing steps (TS) within a testing procedure (TP), associated memory data (SD), associated error report routines (FR), error detection loops (FMS), as well as an interrupt vector table (IVT) with associated interrupt handling routines. During each execution of a testing procedure a memory pointer of the processor system is set to point to a memory data item, an initialisation is performed, and the testing steps are executed. An error report procedure is executed if an error condition is detected during a testing step, and an associated error detection loop is run to determine the source of the error. During an interrupt, an associated interrupt handling routine is called by using the interrupt table, and the error report program associated with the interrupted test procedure is run to initiate the corresponding error detection loop.

Description

Microprocessor systems are used to control programs controlled facilities such. B. Communication facilities The circuitry core of a microprocessor systems consists of a central processor, memory elements and often also includes control elements for input / Output units.

The commissioning of the microprocessor system, be it at Development, in the test field after production or at Installation or customer service, required first Step the test of the circuit technology.

Should already be in the circuitry core of the microprocess sorsystems errors occur, the operating or appli cation software and various input / output controls not ge be tested. The test of the circuitry core around summarizes at least the self-test of the central processor and one Test the storage elements. The storage elements are usual Usually read / write memory (RAM). It is general known that the egg test for the circuitry core A microprocessor needs data in a read / write memory or stored in a read-only memory or from be fed outside.

Significant problems or malfunctions during the first test steps represent asynchronous events, such as unmaskable Interruptions, representing. The return to the fault location after loading act of the interruption is only conditional or with corresponding realizing a lot of effort. Because such asynchronous Events are rare and may only be sporadic treatment is not planned. A possible che alternative would also be to stop at the disturbance  of the central processor to respond. An error localization and analysis is not possible.

The invention is therefore based on the object of a method for testing a microprocessor system, especially during commissioning, to indicate that even with asynchronous Er events supports fault localization and analysis.

The task is performed by the procedure according to the characteristics of the Claim 1 solved.

The circuitry requirements for testing the Microprocessor systems are given by the programs for the first test functions, error analysis and correction supporting programs in a read-only memory, e.g. B. an electrically programmable read-only memory (EPROM), are saved. This can cause errors in the read / write do not save the execution of the first test steps affect.

The test of the circuit technology can be done in test functions be structured. For each of these test functions, a Kel Memory pointer of the central processor to cellar memory data set and initialization for each test steps associated with the test function. There The test steps are then carried out and at Feststel an error analysis or diagnosis supports. This is how an error assigned to the test function becomes Report program called or in the sense of a determination of An error measuring loop program was executed. Both measures can also be carried out together.

Since the basement memory data is also stored in the read-only memory are stored, the processing of an interrupt requirement supported in a special way. Kick an interruption request, the Un break vector table the associated interrupt break action program called. When an undercut occurs  usually becomes the return address for the sub break handling on the next command within the ak currently executed command sequence set. Because the basement otherwise the memory is always assigned to the read / write memory, the data last stored there will be overwritten. Erfin However, the cellar pointer on the Kel Memory data set in the read-only memory that is not can be overwritten. So it can be guaranteed that after execution of the interrupt handler a mistake assigned to the test function currently being executed lerreportprogramm is called and / or in the sense of a Be an error measurement loop program is performed.

With little programming effort, that an error analysis even with interrupt requests and rectification is possible.

An alternative, but more technically complex solution is that the interrupt handling programs themselves include error report programs and / or error measurement loop programs that can be assigned to the error location. Error report programs FR or error measurement loop programs FMS can be assigned to the interrupt handling program 15 in various ways, ie an interrupt handling program 15 can also directly call error report programs FR or error measurement loop programs FMS via transformation tables without the address being returned using the interrupt return. It would have to be saved a designation of the current error function at the beginning of each error function, so that an additional CPU register would be required.

The method according to the invention delivers, even with asynchro events during the first test steps, test statements on a completely defective read / write memory. For the Use of interrupt origin data within the  Cellar storage data is the test security highest when for each test function, the cellar pointer of the Central processor to the respective basement memory data is provided.

The programs belonging to the test are advantageously those Assigned firmware to the microprocessor system. With it verbes This also ensures that the techni is easy to maintain customer service. A self-test on site during commissioning acceptance or in the event of failures.

Support for troubleshooting in the Development phase, since an emulator to support the Tests usually delayed the actual development of the Microprocessor system is available. The described Test procedure is without test facility and emulator use possible and thus offers special advantages for small fer production quantities, e.g. B. in communication systems. Can too for small quantities on complex automatic test car mate in the test field after production. In addition the test is possible under real-time conditions, which is what Emu is often not given. The test concept can also be quickly transferred to other microprocessor systems, if it is defined in the form of macros and macro assembly tax is implemented in programs.

According to advantageous embodiments of the Ver The error reporting programs are used to drive error data in Form of error documentation and generated by the errors measuring loop programs an oscilloscopic examination of the Operation of the circuit technology under the conditions that led to errors or interruptions.

The error data are advantageously in static and va riable data, the static data being the Mask of the error report with information about the previously output led test function and the variable data the ak  current interruption number and which describes the location of the fault include relevant information.

In the following, the method according to the invention will be based on graphic representations are explained in more detail.

Show it

Fig. 1 is a block diagram of the circuitry of a kroprozessorsystems Mi,

Fig. 2 is a block diagram of a read-only memory with ge stored programs and data,

Fig. 3 shows the sequence of the test process of the circuitry of a microprocessor system and the programs and data involved, and

Fig. 4 is a schematic representation for an error report.

The microprocessor system according to FIG. 1 comprises at least one central processor CPU, a read-only memory EPROM, a read / write memory RAM and an input / output control I / O-ST, which are connected via a common bus system BU. The central processor CPU contains substructures not shown, such as. B. a control unit for controlling the operational ab fes within the microprocessor system, an arithmetic unit for processing various algorithms and in addition to other modules also register sets.

In the read-only memory EPROM are those for the first test radio relevant programs and data. It will assumed that this read only memory EPROM is tainted with such errors that correct execution Prevent relevant programs. The writing / RAM is used for storing programs and Data during the operation of the microprocessor system and  may be required for later test phases. A faulty one Read / write memory RAM affects the invention However, the procedure does not.

Via the input / output control I / O-ST are peripheral assemblies pen can be connected to the microprocessor system. Its function Competitiveness can take place during the first test steps be checked.

Fig. 2 shows the relevant programs and data stored in the read-only memory EPROM for the test. At least one interruption vector table IVT, test steps TS that can be assigned to a test function TP, error report programs FR, error measurement loop programs FMS, cellar memory data SD and the possible interruption associated interrupt handling programs IS are stored in the read-only memory EPROM. The order and position of the storage is irrelevant for the method according to the invention. The division of the test into various test functions TP and its division into test steps TS are also not subject to any restrictions. The read-only memory EPROM and the registers of the central processor CPU are the only storage media which are required for the test method according to the invention.

The process sequence becomes clearer with reference to FIG. 3. The aforementioned required storage media, read-only memory EPROM and the CPU registers are shown as block diagrams, the interruption vector table IVT, commands and programs for initializing and setting the stack memory pointer SP, test steps TS, error report programs FR, fault measurement loop programs FMS, stack memory data SD and Interrupt handling programs IS are stored. Of course, other data can also be stored there. The method is explained below using a test function TP.

At the beginning of the processing of the test function TP, the Kel Memory pointer SP of the central processor CPU to the respective cellar storage data SD set (process step l) and the initia necessary for the next test step TS lization carried out (process step 2).

The basement memory data SD belonging to the test function TP include information about the reset values of the status indicator chen of the central processor CPU, one on the respective error lerreport program FR of the test function TP showing sub-areas Return return address to which an interrupt return jump command IRET, and a description of each because test function TP.

It follows with the execution of the test steps TS continued (step 3).

Now let us assume that due to an error in the microprocessor system an interruption (event 4) is requested. There then usually the interrupt return address for the interrupt handler IS in the Cellar store written so with after the interruption the following command can be continued. Since the Cellar memory data SD, however, on the read-only memory EPROM are overwritten (step 5) unsuccessful. With the help (step 6) of the sub Refraction vector table IVT now becomes an interruption (Event 4) associated interrupt handler IS selected (process step 7).

This interrupt handling program IS is executed the occurrence of the interruption (event 4) indicating information and the interruption number for the, mis can output the documentation on a monitor (procedure step 8). The one at the time of the interruption for the test CPU register contents relevant to TS remain unchanged different.  

After the interrupt handling program IS has been processed is returned to the. with an interrupt return command IRET by the interrupt return address in the basement memory specified address jumped (process step 9). These Address is the start of a test function TP Error report program FR, which should document the error. This error report program FR prepares the CPU register hold in variable fault data FD to the fault location and to the the central processor CPU got up (method step 10).

A further process step can optionally follow, the the data stored in the CPU registers for error documentation mentation on a monitor (step 11). Thereupon after execution of the error report program FR called an error measurement loop program FMS (procedure step 12). In this error measurement loop program FMS e.g. B. for oscilloscopic evaluation of the cause of the error commands preceding the error in a loop fetched and executed under real-time conditions. In doing so the variable data valid at the time of the interruption used. This also allows sporadic errors to be found and an immediate search for the cause of the error is possible Lich.

It should be noted that only one of the two programs for fault localization and analysis, d. H. an error report program FR or an error measuring loop program FMS, out can be led.

The format generated for error documentation is shown by way of example with reference to FIG. 4. The error documentation can on a monitor such. B. can be output via a V24 interface to an external storage medium and displayed (see process steps 8 and 11). The interruption handling program IS issued the designation of the interruption as IS2 as variable data. The error report program FR indicates the test function name stored in the basement z. B. from "at TP1".

In the event of an error, output will continue to be the mask for the documentation mentation, such as address, actual value and setpoint, by the mistake lerreport program FR initiated. Do this in this mask also the variable data that characterizes exactly this error NEN, used. Variable data is the address xx, where the error has occurred, for example for a mistake Read / write memory RAM information for the actual value yy, which denotes the data read out, and for the setpoint zz, which describes the registered data. For various However, this mask can individually design the types of errors be tested.

Claims (10)

1. Method for testing the circuit technology of a microprocessor system with at least one central processor (CPU) and a read-only memory (EPROM),

• - where on the read-only memory (EPROM)
• - Programs for test steps (TS) within test functions (TP)
• - with associated basement storage data (SD),
• - assigned error report programs (FR) and / or
• - error measurement loop programs (FMS),
• - and an interruption vector table (IVT) and interruption handling programs (IS) belonging to the possible interruptions

are saved,
where every time a program for a test function (TP) is processed

• a basement memory pointer (SP) of the central processor (CPU) is set to the respective basement memory data (SD) and an initialization is carried out,
• - on which test steps (TS) are carried out and
• - If an error is detected, the associated error report program (FR) is called up and / or an error measurement loop program (FMS) is executed in the sense of determining the cause of the error and

in the case of an interrupt request

• - With the help of the interrupt vector table (IVT) the associated interrupt handling program (IS) is called and
• - An error report program (FR) assigned to the previously executed test function (TP) is called and / or an error measurement loop program (FMS) is executed in the sense of determining the cause of the error.

2. The method according to claim 1, characterized,  that the basement memory data (SD) is an indication of each because of the error report program (FR) or the error Interruption return showing measurement loop program (FMS) jump address of the test function (TP). 3. The method according to claim 1, characterized, that the interrupt handling programs (IS) test function Error report programs (FR) and / or errors that can be assigned to (TP) include measurement loop programs (FMS). 4. The method according to claim 2, characterized, that the basement memory data (SD) reset values of the state Identity of the central processor (CPU) and a designation Include information of the respective test function (TP). 5. The method according to any one of claims 1 to 4, characterized, that through the error report programs (FR) error data (FD) be cached. 6. The method according to claim 5, characterized, that the error data (FD) both static and variable Include data. 7. The method according to claim 6, characterized, that the static data the occurrence of an interruption indicating information and the break number ten. 8. The method according to any one of the preceding claims, characterized in that in the read-only memory (EPROM) stored programs (TP, FR, FMS, IS, IVT) the Firmware of the microprocessor system are assigned.