GB1419191A - Data processing system - Google Patents

Abstract

1419191 Automatic exchange systems INTERNATIONAL STANDARD ELECTRIC CORP 22 Feb 1973 [25 Feb 1972] 8635/73 Heading H4K [Also in Division G4] A data processing system includes a plurality of processors controlling, e.g. telecommunications switching equipment, by executing a plurality of programs which are divided into two groups, the programs in the first group being performed in general by only a predetermined one of the processors and those in the second group by at least two of the processors. The system comprises two processors each having an individual memory and may be as described in Specification 1,181,182. Programming.-The memories contain a series of words storing the addresses of a series of "clock level programs" and of a series of "base level programs". A clock interrupt is signalled every 10 milliseconds to initiate execution of the sequence of "clock level" programs, any time remaining following completion of the sequence before the next interrupt being used to perform the "base level" sequence. The particular sequence of "clock level" program to be performed, is determined by a "monitor table" containing a series of words which are selected in sequence, one at each interrupt, and which have a bit for each program whose state indicates whether the associated program is to be executed during the current interrupt. The sequence of "base level" programs is determined in the same way. Each processor memory stores a base level program mask word having one but for each base level program whose state indicates whether the associated processor may or may not execute the associated program. The base level programs are then divided into two groups, one for execution on only one processor and,the other on both. A similar mask may be provided for the clock level programs. For programs which may be executed by both processors complementary tables are stored in the processor memories to indicate which elements in the controlled switching equipment are to be controlled by each processor thereby avoiding conflicts. Operation.-A clock interrupt initiates a supervisory program and the relative address of a word in the clock level monitor table is added to the table base to access the word. The relative address is then incremented, or reset to zero, for use in the next interrupt. If the monitor table word is non-zero the first "1" bit is located (see Specification 1,367,709) and a value indicative of the bit position is used as an index to locate the corresponding program which is executed. As each program is executed its bit in the monitor table word is reset until the word is a zero when the sequence is complete. The clock level programs may involve testing certain devices in the switching equipment, a request mask word being set as appropriate to indicate that particular base level programs are required, e.g. to investigate a fault. Following completion of the clock level sequence any remaining time is used for base level programs which are selected in a similar manner except that the base level -monitor table word is AND-ed with the base level mask, to ensure that only allowable programs are executed, and also with a base level effective mask which indicates which programs should not be executed due to lack of data. The resulting word is then OR-ed with the request mask and with the program selecting word left from the previous cycle so as to include urgent requested program (see above) and programs not executed for lack of time in the previous cycle respectively. The resulting word then selects the base level programs (as above for clock level programs).