JPH0484245A - Duplex storage device - Google Patents
Duplex storage deviceInfo
- Publication number
- JPH0484245A JPH0484245A JP2199966A JP19996690A JPH0484245A JP H0484245 A JPH0484245 A JP H0484245A JP 2199966 A JP2199966 A JP 2199966A JP 19996690 A JP19996690 A JP 19996690A JP H0484245 A JPH0484245 A JP H0484245A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- memories
- control part
- mounting
- virtual
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims abstract description 65
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、二重化メモリ装置の管理手段に利用する。特
に、メモリ障害発生時にアクセス処理の継続性を保証す
るためのメモリの管理手段に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is utilized as a management means for a duplex memory device. In particular, the present invention relates to memory management means for ensuring continuity of access processing when a memory failure occurs.
本発明は、2つの記憶領域のひとつを制御対象にする記
憶装置おいて、
この2つの記憶領域を1つのメモリ装置上に実現するこ
とにより、
装置のコストを低減することができるようにしたもので
ある。The present invention is a storage device in which one of two storage areas is controlled, and by realizing these two storage areas on one memory device, the cost of the device can be reduced. It is.
従来、メモリ障害発生時にアクセス処理の継続性を保証
する場合に、実装メモリが1個でなく、メモリを2個実
装して制御していた。Conventionally, when ensuring the continuity of access processing when a memory failure occurs, two memories are mounted instead of one and controlled.
このような従来例では、メモリを2個実装するので、実
装された2つのメモリに同時にアクセスするための制御
装置と、メモリ障害発生時に障害が発生したメモリを物
理的に切り離し、片方の実装メモリのみで処理を継続す
るための制御装置を必要とし、コストが高くつく欠点が
ある。In such a conventional example, two memories are mounted, so when a memory fault occurs, the control device for accessing the two mounted memories at the same time is physically separated from the faulty memory, and one of the mounted memories is This method requires a control device to continue the process by itself, which has the disadvantage of high cost.
本発明は、このような欠点を除去するもので、構成の簡
単な二重化記憶装置を提供することを目的とする。The present invention aims to eliminate such drawbacks and to provide a duplex storage device with a simple configuration.
本発明は、同一の内容が格納される2つの記憶領域と、
制御対象になる記憶領域のひとつをこの2つ記憶領域か
ら選択する手段を含む制御手段とを備えた二重化記憶装
置において、上記2つの記憶領域をもつ1つの実装メモ
リ回路を備えたことをvF徴とする。The present invention provides two storage areas in which the same content is stored;
In a duplex storage device equipped with a control means including a means for selecting one of the storage areas to be controlled from the two storage areas, the vF feature indicates that one implemented memory circuit having the above two storage areas is provided. shall be.
ここで、上記制御手段は、上記2つの記憶領域を同時に
アクセスし、障害の発生している記憶領域をアクセス対
象から切り離す手段を含むことが望まれる。Here, it is desirable that the control means include means for simultaneously accessing the two storage areas and separating the faulty storage area from the access target.
また、上記制御手段は、上記2つの記憶領域を同時にア
クセスし、障害の発生していない記憶領域をアクセス対
象にする手段を含むことが望まれる。Further, it is desirable that the control means includes means for simultaneously accessing the two storage areas and making the storage area in which no failure has occurred an access target.
1つのメモリ回路を論理的に2つに分割して、これを制
御し、1方の障害状態に、同一内容を格納する他方を対
象にアクセス処理を継続する。One memory circuit is logically divided into two parts and controlled, and when one memory circuit is in a faulty state, access processing is continued for the other part that stores the same content.
以下、本発明の一実施例について図面を参照して説明す
る。An embodiment of the present invention will be described below with reference to the drawings.
第1図はこの実施例の構成を表わす図である。FIG. 1 is a diagram showing the configuration of this embodiment.
この実施例は、第1図に示すように、同一の内容が格納
される2つの記憶領域と、制御対象になる記憶領域のひ
とつをこの2つの記憶領域から選択する手段を含む制御
手段とを備え、さらに、本発明の特徴とする手段として
、上記2つの記憶領域をもつ1つの実装メモリ回路であ
る実装メモリ2を備え、上記制御手段は、メモリ論理的
二重化制御部1であり、上記2つの記憶領域は仮想実装
メモリ5および6てあり、この2つの記憶領域を同時に
アクセスし、障害の発生している記憶領域をアクセス対
象から切り離す手段および上記2つの記憶領域を同時に
アクセスし、障害の発生していない記憶領域をアクセス
対象にする手段を含む。As shown in FIG. 1, this embodiment has two storage areas in which the same content is stored, and a control means including means for selecting one of the storage areas to be controlled from the two storage areas. Further, as a feature of the present invention, there is provided a mounted memory 2 which is one mounted memory circuit having the above-mentioned two storage areas, the above-mentioned control means is a memory logical duplication control section 1, and the above-mentioned 2. The two storage areas are virtual implementation memories 5 and 6, and there is a means for simultaneously accessing these two storage areas and separating the faulty storage area from the access target. It includes means for making an unoccupied storage area an access target.
次に、この実施例の動作を説明する。メモリ論理的二重
化制御部1は、本発明の対象である1つの実装メモリ2
を2つの仮想実装メモリ5および6に論理的に分割して
制御する。処理プログラム4は、メモリ管理部3を経由
してメモリへのアクセスを行う。メモリアクセス要求を
受付けたメモリ管理部3は、さらにメモリ論理的二重化
制御部1ヘメモリアクセス要求を行う。メモリへのアク
セス要求を受付けたメモリ論理的二重化制御部1は、実
装メモリ2を論理的に半分に分割した仮想実装メモリ5
および仮想実装メモリ6に対して同時にアクセスを行い
、仮想実装メモリ5と仮想実装メモリ6の内容が常に同
一となるように制御する。実装メモリ2にメモリ障害が
発生すると、第2図に示すように、メモリ論理的二重化
制御部1はメモリ障害に遭遇した方の仮想実装メモリの
みを論理的に切り離し、残った方の仮想実装メモリのみ
でメモリへのアクセス処理を継続する。Next, the operation of this embodiment will be explained. The memory logical duplication control unit 1 has one implemented memory 2 which is the object of the present invention.
is logically divided into two virtual memories 5 and 6 and controlled. The processing program 4 accesses the memory via the memory management section 3. The memory management unit 3 that has received the memory access request further issues a memory access request to the memory logical duplication control unit 1. The memory logical duplication control unit 1 that has received the memory access request creates a virtual mounted memory 5 that logically divides the mounted memory 2 into halves.
and the virtual mounting memory 6 at the same time, and control is performed so that the contents of the virtual mounting memory 5 and the virtual mounting memory 6 are always the same. When a memory failure occurs in the mounted memory 2, as shown in FIG. Continues memory access processing only.
本発明は、以上説明したように、1つの実装メモリを2
つの仮想実装メモリに分割し、これらの内容を常に同一
となるように制御することにより、メモリ障害発生時に
処理を継続することができる効果がある。As explained above, the present invention enables one mounted memory to be used for two
By dividing the memory into two virtual implementation memories and controlling the contents so that they are always the same, it is possible to continue processing even when a memory failure occurs.
第1図は、本発明実施例の構成を示す全体構成図。
第2図は、本発明実施例の動作を示すフローチャート。
■・・・メモリ論理的二重化制御部、2・・・実装メモ
リ、3・・・メモリ管理部、4・・・処理プログラム、
5.6・・・仮想実装メモリ。FIG. 1 is an overall configuration diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a flowchart showing the operation of the embodiment of the present invention. ■... Memory logical duplication control unit, 2... Mounted memory, 3... Memory management unit, 4... Processing program,
5.6...Virtual implementation memory.
Claims (1)
象になる記憶領域のひとつをこの2つの記憶領域から選
択する手段を含む制御手段とを備えた二重化記憶装置に
おいて、 上記2つの記憶領域をもつ1つの実装メモリ回路 を備えたことを特徴とする二重化記憶装置。 2、上記制御手段は、上記2つの記憶領域を同時にアク
セスし、障害の発生している記憶領域をアクセス対象か
ら切り離す手段を含む特許請求項1記載の二重化記憶装
置。 3、上記制御手段は、上記2つの記憶領域を同時にアク
セスし、障害の発生していない記憶領域をアクセス対象
にする手段を含む特許請求項2記載の二重化記憶装置。[Claims] 1. A duplex storage device comprising two storage areas in which the same content is stored, and a control means including means for selecting one of the storage areas to be controlled from the two storage areas. A duplex storage device comprising one mounted memory circuit having the above two storage areas. 2. The duplex storage device according to claim 1, wherein the control means includes means for simultaneously accessing the two storage areas and separating the faulty storage area from the access target. 3. The duplex storage device according to claim 2, wherein said control means includes means for simultaneously accessing said two storage areas and selecting a storage area in which no fault has occurred as an access target.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2199966A JPH0484245A (en) | 1990-07-26 | 1990-07-26 | Duplex storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2199966A JPH0484245A (en) | 1990-07-26 | 1990-07-26 | Duplex storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0484245A true JPH0484245A (en) | 1992-03-17 |
Family
ID=16416566
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2199966A Pending JPH0484245A (en) | 1990-07-26 | 1990-07-26 | Duplex storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0484245A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8135330B2 (en) | 2007-06-28 | 2012-03-13 | Brother Kogyo Kabushiki Kaisha | Image recording device and determination method |
-
1990
- 1990-07-26 JP JP2199966A patent/JPH0484245A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8135330B2 (en) | 2007-06-28 | 2012-03-13 | Brother Kogyo Kabushiki Kaisha | Image recording device and determination method |
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