GB1560487A - Detection of error in digital signals - Google Patents

Description

(54) DETECTION OF ERROR IN DIGITAL SIGNALS (71) We, THE POST OFFICE, a British body corporate established by Statute, of 23 Howland Street, London, W1P 6HQ, do hereby declare the invention, for which wc pray that a patent may be granted to us, and the method by which it is to be pcrformed, to be particularly described in and by the following statement: This invention relates to the detection of errors in digital signals. It is an improvement in or modification of the invention described and claimed in U.K. Patent Specification No. 1,409,237.

Patent Specification No. 1,409,237 describes a pseudo-random binary sequence (PRBS) signal generator which includes a plurality of shift registers whose outputs are arranged to be bit interleaved to provide the generator output and wherein the input signal to each of the shaft registers is derived from at least one of the other shift registers. The PRBS generator generates an output at a very high bit rate compared with prior generators using logic elements of comparable speed.

Claim 1 of Patent Specification No.

1,409,237 reads as follows: A pseudo-random binary sequence generator including a plurality of shift registers, a corresponding plurality of signal combining means and a bit interleaving means, said bit interleaving means having a corresponding plurality of inputs and an output, in which the shift register outputs are coupled to respective inputs of the bit interleaving means and the bit interleaving means output forms the generator output and wherein the inputs to the shift registers are taken from the outputs of respective signal combining means and the input to the signal combining means are taken from the outputs of selected shift register stages so that each combining means receives inputs from more than one shift register.

It is an object of the invention to provide an error detection circuit which operates at a very high bit rate as compared to known error detection circuits using logic elements of like speed.

The present invention provides an error detection circuit operative to detect errors in an incoming serial digital signal, the circuit including a plurality of shift registers, a corresponding plurality of signal combining means and a bit de-interleaving means, said bit de-interleaving means having an input and a corresponding plurality of outputs, the shift register inputs being coupled to respective outputs of the bit deinterleav- ing means and the bit de-interleaving means input forming the error detection circuit input, the inputs to the signal combining means beong taken from the outputs of selected shift register states, and means being provided to compare bits from the incoming signal with the outputs of the signal combining means to detect errors in the incoming signal.

It may be noted that the relationship be tween an error detection circuit as defined in the preceding paragraph and a PRBS generator as claimed in claim 1 of specification No. 1,409,237 is that the circuit connections of the one are, generally speaking, the converse of the circuit connections of the other (for example, the error detection circuit deinterleaves the input whereas the PRBS generator interleaves the output). Thus, the present invention is an improvement in or modification of the invention claimed in specification No. 1,409,237.

Each combining means can receive inputs from more than one shift register. The combining means can be modul2 adders.

The error detection circuit can embody features of the error detecting means described in, and defined in the claims of, U.K.

Patent Specification No. 1,281,390. The following claims of Patent Specification No.

1,281,390 have reference to the error detecting means: 1. Apparatus for testing a digital data transmission system having a transmitter and a receiver, the transmitter including means operable to generate a serial pattern of digits, in which each digit is a predetermined function of two or more digits each preceding that digit by a particular spacing in the pattern, and to transmit the pattern to the receiver, the receiver including error detecting means operable to compare a digit in the received pattern with the combination, in accordance with the said predetermined function, of the two or more digits preceding that digit by the said particular spacings in the received pattern and to generate an error indication when there is no correlation.

2. Apparatus as claimed in claim 1, in which the error detecting means includes means operable to generate, for a digit in the received pattern, a test digit which is the said predetermined function of the two or more digits preceding that digit by the said particular spacings in the received pattern, and means operable to compare that digit with the test digit and to generate an error signal when the compared digits are not the same.

7. Apparatus as claimed in claim 6, in which the error detecting means includes a shift register having at least N stages (Nn), and means operable to compare the input to the (N-n+ 1)th stage with the modulo 2 sum of the output of the Nth and (N - n + r)th stages.

8. Apparatus as claimed in claim 7, in which the Nth stage and the (N-n+r)th stage of the error detecting shift register each has an output to a modulo 2 adder, and the error detecting means includes means operable to compare the output of that modulo 2 adder with the input to the (N-n+ 1)th stage of the error detecting shift register.

9. Apparatus as claimed in claim 7 or claim 8, in which the Nth stage of the error detecting shift register is the (n+l)th stage.

10. Apparatus as claimed in any one of claims 7 to 9, in which the error detecting means is operable to generate an error signal in response to every third occurrence of no correlation between the input to the (N-n+ 1)th stage of the error detecting shift register and the modulo 2 sum of the output of the Nth and (N-n+r)th stages.

11. Apparatus as claimed in any one of claims 6 to 10, in which the nth stage and the rth stage of the shift register(s) are spaced apart by at least one stage.

12. Apparatus as claimed in any one of claims 6 to 11, in which the nth and rth stages of the shift register(s) are the 9th and 5th stages respectively.

13. Apparatus as claimed in any one of claims 6 to 11, in which the nth and rth stages of the shift register(s) are the 18th and 11th stages respectively.

By way of example only, an illustrative embodiment of the invention will now be described with reference to the single figure of the accompanying drawing which shows an error detector embodying the invention.

The error detector shown in the drawing operates basically in the same manner as the error detector shown in Figure 2 of Patent Specification No. 1,281,390 and it is assumed that the reader has studied the disclosure of specification No. 1,281,390. The present error detector is capable of faster operation than the detector of specification No. 1,281,390 when logic elements of like speed are used in it. This result is achieved by employing in the error detector of specification No. 1,281,390 the techniques employed in the PRBS generator of Specification No. 1,409,237. It is assumed that the reader has studied the disclosure of specification No. 1,409,237.

Turning now to the drawing, a six-stage shift register la and a seven-stage shift register lb receive shift signals from a clock source 2. The stages of the register la are referenced starting at the input end S-l,, 51,, S3a, S5a, S7a and S9a respectively, and those of register lb are referenced S-2b, SOb, S2b, S4b, S6b, S8b, SlOb respectively.

The stages S-2b, S-la and SOb in conjunction with an inverter 3 in series with the shift input to stage S-2b constitute a bit deinterleaver. An incoming serial digital signal on a line 4 is commonly applied to stages S-la and S-lb. Because the output of the clock source is a square-wave of frequency one half the bit-rate of the incoming signal and because of the inversion of the shift sign to stage S-2b, the odd bits in the incoming signal enter one register and the even bits in the incoming signal enter the other register. Apart from stage S-2b, all the stages of the registers la and ib are shifted simultaneously at one-half the bit-rate of the incoming signal. Stage S-2b is, of course, shifted half-way between the shift times of the other stages.By this means, the incoming signal is taken into the registers as fast as it is received yet the registers are being shifted at only one half the bit-rate of the incoming signal.

A modulo-2 adder 5 has its inpus connected to the outputs of stages S6b and S9a, and a further modulo-2 adder 6 has its inputs connected to the outputs of stages S7a and SlOb. The adders 5 and 6 are equivalent in function to the adder ADD2 of Figure 22 of Specification No. 1,281,390. The output of adder 5 is connected to the input of a further modulo-2 adder 7, and the output of adder 6 is connected to the input of a further modulo-2 adder 8. The adder 7 receives its other input from the output stage S-la, and adder 8 receives its other input from the output of stage SOb. The adders 7 and 8 are equivalent in function to the correlator CLTR. of Figure 2 of Specification No. 1,281,390.

The outputs of adders 7 and 8 are con nected to the inputs of respective divide-bythree circuits 9 and 10 and the outputs of the circuits 9 and 10 are combined (that is, totalled) in an error count circuit 11. The divide-by-three circuits 9 and 10 are equivalent in function to the divide circuit DTV of Figure 2 of Specification No. 1,281,390.

It can be seen that the present embodiment applies the techniques disclosed in specification No. 1,409,237 to the circuit of Figure 2 of Specification No. 1,281,390 to produce an error detector capable of fast operation when logic elements of like speed are employed.

Whilst the use of two parallel shift rcgi- sters has been described, three, four and higher numbers of shift registers can be employed, a suitable bit de-interleaver being used to divide the incoming bits cyclically and sequentiallv between the registers (appropriately clocked shift register stages can be used for this purpose).

The error detector shown is designated to operate with an incoming pseudo random binary sequence of 2'0--1 bit length. Error detectors for other sequence lengths can be made by an appropriate choice of the number of register stages, the number of modu10-2 adders, the stages to which they are connected, and the division factor of the divider circuits.

It is to be understood that the described circuit can be modified, for example, to use shift registers tof delay-line type or to use an alternative form of de-interleaver.

WHAT WE CLAIM IS:- 1. An error detection circuit operative to detect errors in an incoming serial digital signal, the circuit including a plurality of shift registers, a corresponding plurality of signal combining means and a bit de-interleaving means, said bit de-interleaving means having an input and a correspoading plurality of outputs, the shift register inputs being coupled to respective outputs of the bit de-interleaving means and the bit deinterleaving means input forming the error detection circuit input, the inputs to the signal combining means being taken from the outputs of selected shift register stages, and means being provided to compare bits from the incoming signal with the outputs of the signal combining means to detect errors in the incoming signal.

2. A circuit as claimed in claim 1, wherein each combining means receives inputs from more than one shift register.

3. A circuit as claimed in claim 1 or 2, wherein each combining means is a modu10-2 adder.

4. A circuit as claimed in claim 1, wherein the circuit is arranged to carry out the function of that error detecting means specified in any of the following claims of Patent Specification 1,281,390: claim 1, 2, 7, 8, 9, 10, 11, 12 or 13.

5. An error detection circuit substantially as herein described with reference to and as illustrated by the single Figure of the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (5)

**WARNING** start of CLMS field may overlap end of DESC **. nected to the inputs of respective divide-bythree circuits 9 and 10 and the outputs of the circuits 9 and 10 are combined (that is, totalled) in an error count circuit 11. The divide-by-three circuits 9 and 10 are equivalent in function to the divide circuit DTV of Figure 2 of Specification No. 1,281,390. It can be seen that the present embodiment applies the techniques disclosed in specification No. 1,409,237 to the circuit of Figure 2 of Specification No. 1,281,390 to produce an error detector capable of fast operation when logic elements of like speed are employed. Whilst the use of two parallel shift rcgi- sters has been described, three, four and higher numbers of shift registers can be employed, a suitable bit de-interleaver being used to divide the incoming bits cyclically and sequentiallv between the registers (appropriately clocked shift register stages can be used for this purpose). The error detector shown is designated to operate with an incoming pseudo random binary sequence of 2'0--1 bit length. Error detectors for other sequence lengths can be made by an appropriate choice of the number of register stages, the number of modu10-2 adders, the stages to which they are connected, and the division factor of the divider circuits. It is to be understood that the described circuit can be modified, for example, to use shift registers tof delay-line type or to use an alternative form of de-interleaver. WHAT WE CLAIM IS:-

1. An error detection circuit operative to detect errors in an incoming serial digital signal, the circuit including a plurality of shift registers, a corresponding plurality of signal combining means and a bit de-interleaving means, said bit de-interleaving means having an input and a correspoading plurality of outputs, the shift register inputs being coupled to respective outputs of the bit de-interleaving means and the bit deinterleaving means input forming the error detection circuit input, the inputs to the signal combining means being taken from the outputs of selected shift register stages, and means being provided to compare bits from the incoming signal with the outputs of the signal combining means to detect errors in the incoming signal.

2. A circuit as claimed in claim 1, wherein each combining means receives inputs from more than one shift register.

3. A circuit as claimed in claim 1 or 2, wherein each combining means is a modu10-2 adder.

4. A circuit as claimed in claim 1, wherein the circuit is arranged to carry out the function of that error detecting means specified in any of the following claims of Patent Specification 1,281,390: claim 1, 2, 7, 8, 9, 10, 11, 12 or 13.

5. An error detection circuit substantially as herein described with reference to and as illustrated by the single Figure of the accompanying drawings.