GB2154104A - Test apparatus - Google Patents

Abstract

A test apparatus for determining the reception at a communications receiver of a predetermined data pattern consisting of a repeating sequence of digital bytes 1-10 corresponding to either an "ACTIVE" or "IDLE" state, operates by detecting a frequency component associated with the repetition rate of the sequence i.e. by comparing a corresponding byte, 1, in successive sequences in the manner of a digital filter (7-19, Fig. 2), and monitoring the resultant error count. This makes it unnecessary to uniquely identify each bit to determine whether it forms part of the test pattern, as it is sufficient to extract an expected frequency component. The error count is thresholdably higher in the presence of data, compared with the count produced by the test pattern. Distinction may be made between the "IDLE" and "ACTIVE" patterns, by similarly treating the MSB's of the test pattern bytes. <IMAGE>

Description

SPECIFICATION Test Apparatus This invention relates to test apparatus and is particularly suitable for testing a communications link by monitoring the integrity of a test pattern of data which is passed over the link to a receiver from a distant transmitter. In a large communications system having many individual communications channels which are transmitted over a long distance, possibly using a satellite repeater station, a high degree of confidence in the system must be maintained; that is to say, one must be confident that data in transmission will not be unduly corrupted, and that it will be routed to the correct destination channel. Furthermore, it is highly desirable to be able to test designated transmission channels whilst other parts of the system continue to carry real data traffic.These requirements can make it difficult to verify the operation of a communications system, and this invention seeks to provide an improved test apparatus which is suitable for this purpose.

According to a first aspect of this invention, a test apparatus for determining the reception at a communications receiver of a predetermined data test pattern consisting of a repeating sequence of digital bytes, includes means for comparing received bytes of data with previously received bytes which are spaced apart by the expected length of the sequence; and means for utilising the results of said comparisons to determine whether said compared bytes form part of a predetermined test pattern.

According to a second aspect of this invention a test apparatus for evaluating a communications link is arranged to monitor a sequence of data bytes received via the link, and to perform a digital filtering process on the sequence to identify a frequency component corresponding to the repetition rate of the sequence.

The invention is particularly suitable for use with a large and complex communication system having many communication channels. In normal operation, such a system may consist of channels in which each data byte has a certain number of bits, e.g. 8 bits. As the data traffic level fluctuates, it may rise above the level which can be handled by the available number of channels, and to accommodate the overload the number of bits in each byte can be reduced, e.g. 1 bit, to 7 bits in this example, with the remaining bit from each channel being used to constitute new channels. At a receiver, the reconstituted stream of data bytes relating to a particular message has a constant number of bits, (8 bits in this example) regardless of whether the system is configured in the normal or overload mode.Thus in the overload mode, the least significant bit of a byte output at the receiver will not be related to that message but is likely to be of a random nature. This does not matter greatly in practice, as, being the least significant bit, it does not materially affect the information content of the message. However, this aspect can make it difficult to accurately verify the operation of the communications system, as even though the correct test pattern passes over the link, the whole pattern will not necessarily appear in an output channel under test.

The present invention is further described by way of example, with reference to the accompanying drawing, in which: Figure lisa schematic diagram showing part of a test apparatus in conjunction with a communications receiver, and Figure 2 shows test data patterns.

Referring to Figure 1, there is shown therein in very diagrammatic form, a communication system which includes a transmitter 1 and a receiver 2 which are located remotely from each other and which communicate via a number of communication channels 3. In practice, the channels 3 are likely to travel by repeater stations, one or more of which could be a satellite repeater station.

Because it is expensive to provide a long distance communication channel, the transmitter 1 is organised to effect high utilisation of each of the available channels. Thus the transmitter 1 accepts a large number of input message channels 4 and concentrates them into a fewer number of communications channels 3. Each message on a channel 4 consists of active and idle states, the active state comprising information above a minimum threshold level which represents real data and which must be transmitted to the receiver 2. The idle state represents the pauses in a message, corresponding to the intervals which naturally occur in speech or during the listening intervals of a two-way conversation. By discarding the idle portions of a message, the useful information can be greatly concentrated.However, the process of concentration relies on the statistical properties of the messages being transmitted, and if more than a certain number of messages simultaneously are in the active state, an overload will occur.

During normal operation, each byte of data is quantised into 8 bits. This provides a high degree of intelligibility and generally ensures satisfactory reception of a message. During the overload condition, the number of bits in a byte is reduced to 7, and the surplus 8th bits are organised into additional 7-byte channels which can carry the overload whilst it lasts. It is important that the receiver 2 is able to recognise the nature of the data which is passed to it; that is to say, it must recognise whether the data being received is in an active or an idle state, and whether either state is being transmitted in the normal or the overload mode.

This permits the received data to be reformed into the correct message channels 5, of which the number corresponds to the input channels 4 at the transmitter 1.

Operation of the communications link is verified by transmitting certain test patterns of data which respectively represent the active and idle state.

Typical patterns are given in Figure 2. Thus, the active pattern consists of 10 bytes, each of 8 bits with the bytes being transmitted in a sequentially repeating pattern 1 to 10. The idle pattern is organised in a similar manner.

These patterns are analysed at the receiver by means of test apparatus represented generally below the broken line 6. Although in principle a decoder could identify the presence of the active or the idle sequence of bytes on a byte-by-byte basis, such a decoder would be very complex if it is to be tolerant of errors in the transmission path. In the present context, an additional serious difficulty arises in that the 8th bit of the byte, which is the least significant bit, can under conditions of overload be of an indeterminate nature. Thus under overload conditions only the seven most significant bits relate to a particular message channel, and the 8th bit which appears on the output of the receiver is simply a more significant bit of another channel and it is not possible to predict its nature.Certainly, under overload conditions, it will not correspond with the predicted test pattern.

The test apparatus is organised along the lines of a digital filter in orderto determine with a reasonable degree of certainty the identity of the test pattern which is being received, and it can reliably distinguish between true message data representative of real traffic, and the artificial test pattern which is injected at the transmitter in order to verify operation of the system. As the communications system can be a large one, having many channels, it is desirable to be able to transmit the test pattern over certain channels whilst permitting the remaining channels to continue carrying real traffic.

Referring to Figure 1 again, the test apparatus is arranged to monitor the output of a selected one of the output channels 5 and to feed the bytes sequentially into the first register 7 of a series of eleven registers 7 to 17. Each register has an 8 bit capacity so that it can hold one byte. The bytes are entered into the respective registers under the action of a clock signal derived from a local clock source 18 and the bytes are transferred sequentially from one register to the next on the occurrence of a clock pulse. Respective bits in the first register 7 and the last register 17 are compared at respective modulo-2 gates 19. A modulo-2 gate is of the kind which provides one logic output level if its two inputs have the same state, and the other logic output level if its two inputs have mutually different states.Thus the outputs of the gates 19 provide an indication as to whether the content of the registers 7 and 17 are the same. If the test pattern, whether it be the active or the idle pattern, is correctly received at the receiver, the contents of the register 7 and the register 17 will always be the same as each other at a given moment in time and the output of the gates 19 will be all of the same logic state. If only one or two minor bit errors occur within a particular period, the error count will still be very small, and the value of the error count is passed to a decision circuit 21 which declares whether or not a test pattern has been detected. If normal traffic is being received, there will in general be no correlation whatsoever between the contents of the registers 7 and 17 and the error count will be extremely high.Statistically, this can be shown to be above a particular threshold level. If, on the other hand, the test pattern is present in the overload condition such that the 8th bit is indeterminate, this will give rise to a certain error count level which will be substantial, but still below a clearly defined threshold level which can be quantified. Thus one can be reasonably sure whether a test pattern is being correctly received.

Once it is known whether the active or the idle pattern is being received, it is a relatively simple matter to determine which it is of the two possibilities. It will be seen from Figure 2 that the idle pattern is largely a repetition of the same sequence of bits, the 8th or least significant bit being variable, and the most significant bit altering in a block pattern form. Thus by comparing the contents of thu first shift register and, say, the fifth shift register, in a similar manner to the first and eleventh registers, one can determine from the error rate whether there is any degree of correlation. One would expect a high degree of correlation for the idle pattern, but very little correlation would be expected for the active pattern. In this context, an absence of correlation is represented by a high error count which is above a predetermined threshold level. In order to provide this function a similar system of modulo-2 gates and an error counter would be provided in exactly the same manner as that illustrated for the detection of a test pattern. The test apparatus can be implemented as a series of shift registers as shown, or the data can be entered into locations in a large store, and the individual bits accessed as necessary under the action of a central controller to determine their nature, and degree of correlation. The organisation of bit storage in conjunction with error counters is equivalent to a digital filter operating at the byte rate frequency.

This approach makes it unnecessary to uniquely identify the exact nature of each received bit to determine whether it forms part of a particular byte in a test pattern, yet the results can be accepted with a high degree of confidence.

Claims (6)

1.A test apparatus for determining the reception at a communications receiver of a predetermined data test pattern consisting of a repeating sequence ofdigital bytes including means for comparing received bytes of data with previously received bytes which are spaced apart by the expected length of the sequence; and means for utilising the results of said comparisons to determine whether said compared bytes form part of a predetermined test pattern.

2. A test apparatus for evaluating a communications link arranged to monitor a sequence of data bytes received via the link, and to perform a digital filtering process on the sequence to identify a frequency component corresponding to the repetition rate of the sequence.

3. A test apparatus as claimed in claim 1 or 2 and wherein the sequence of bytes is fed serially through a plurality of registers, with the contents of selected registers being compared on a bit by bit basis to determine the degree of similarity in corresponding bit positions.

4. A test apparatus as claimed in claim 3 and wherein a plurality of modular type gates are used to effect the comparison.

5. A test apparatus as claimed in claim 3 or 4 and wherein a frequency component associated with reception rate of the sequence is determined by the spacing of the selected registers and the block rate of the registers.

6. Atest apparatus substantially as illustrated in and described with reference to Figure 1 of the accompanying drawing.