GB1528187A - Integrated programmable logic circuits - Google Patents
Integrated programmable logic circuitsInfo
- Publication number
- GB1528187A GB1528187A GB39443/75A GB3944375A GB1528187A GB 1528187 A GB1528187 A GB 1528187A GB 39443/75 A GB39443/75 A GB 39443/75A GB 3944375 A GB3944375 A GB 3944375A GB 1528187 A GB1528187 A GB 1528187A
- Authority
- GB
- United Kingdom
- Prior art keywords
- transistors
- matrix
- flops
- flip
- feeding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
- H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19742446654 DE2446654C3 (de) | 1974-09-30 | Integrierte, programmierbare Logikanordnung |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1528187A true GB1528187A (en) | 1978-10-11 |
Family
ID=5927137
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB39443/75A Expired GB1528187A (en) | 1974-09-30 | 1975-09-26 | Integrated programmable logic circuits |
Country Status (7)
Country | Link |
---|---|
US (1) | US3974366A (pt-PT) |
JP (1) | JPS6029254B2 (pt-PT) |
BE (1) | BE834024A (pt-PT) |
FR (1) | FR2286559A1 (pt-PT) |
GB (1) | GB1528187A (pt-PT) |
IT (1) | IT1042852B (pt-PT) |
NL (1) | NL7511377A (pt-PT) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2131584A (en) * | 1982-12-08 | 1984-06-20 | Western Electric Co | Programmed logic array |
Families Citing this family (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4183093A (en) * | 1975-09-04 | 1980-01-08 | Hitachi, Ltd. | Semiconductor integrated circuit device composed of insulated gate field-effect transistor |
US4084152A (en) * | 1976-06-30 | 1978-04-11 | International Business Machines Corporation | Time shared programmable logic array |
US4207556A (en) * | 1976-12-14 | 1980-06-10 | Nippon Telegraph And Telephone Public Corporation | Programmable logic array arrangement |
US4124899A (en) * | 1977-05-23 | 1978-11-07 | Monolithic Memories, Inc. | Programmable array logic circuit |
US4195352A (en) * | 1977-07-08 | 1980-03-25 | Xerox Corporation | Split programmable logic array |
US4140921A (en) * | 1977-08-31 | 1979-02-20 | International Business Machines Corporation | Generalized performance power optimized PLA circuits |
US4123669A (en) * | 1977-09-08 | 1978-10-31 | International Business Machines Corporation | Logical OR circuit for programmed logic arrays |
US4249246A (en) * | 1978-02-27 | 1981-02-03 | Nippon Electric Co., Ltd. | Programmable logic array for generating EOR sums of input signals |
JPS558135A (en) * | 1978-07-04 | 1980-01-21 | Mamoru Tanaka | Rewritable programable logic array |
US4233667A (en) * | 1978-10-23 | 1980-11-11 | International Business Machines Corporation | Demand powered programmable logic array |
US4245324A (en) * | 1978-12-15 | 1981-01-13 | International Business Machines Corporation | Compact programmable logic read array having multiple outputs |
JPS5616243A (en) * | 1979-07-18 | 1981-02-17 | Matsushita Electric Ind Co Ltd | Microaddress production system |
US4395646A (en) * | 1980-11-03 | 1983-07-26 | International Business Machines Corp. | Logic performing cell for use in array structures |
JPS57115188U (pt-PT) * | 1981-01-09 | 1982-07-16 | ||
US4660171A (en) * | 1981-12-21 | 1987-04-21 | International Business Machines Corp. | Apparatus and method using a programmable logic array for decoding an operation code and providing a plurality of sequential output states |
DE3215671C2 (de) * | 1982-04-27 | 1984-05-03 | Siemens AG, 1000 Berlin und 8000 München | Programmierbare Logikanordnung |
US4506341A (en) * | 1982-06-10 | 1985-03-19 | International Business Machines Corporation | Interlaced programmable logic array having shared elements |
US4661922A (en) * | 1982-12-08 | 1987-04-28 | American Telephone And Telegraph Company | Programmed logic array with two-level control timing |
US4488229A (en) * | 1982-12-08 | 1984-12-11 | At&T Bell Laboratories | PLA-Based finite state machine with two-level control timing and same-cycle decision-making capability |
US4577190A (en) * | 1983-04-11 | 1986-03-18 | At&T Bell Laboratories | Programmed logic array with auxiliary pull-up means to increase precharging speed |
US4611133A (en) * | 1983-05-12 | 1986-09-09 | Codex Corporation | High speed fully precharged programmable logic array |
JPS60233932A (ja) * | 1984-05-04 | 1985-11-20 | Nec Corp | ドミノc−mos論理アレイ |
US4609986A (en) * | 1984-06-14 | 1986-09-02 | Altera Corporation | Programmable logic array device using EPROM technology |
EP0178437A1 (de) * | 1984-09-19 | 1986-04-23 | Siemens Aktiengesellschaft | Programmierbare Schaltung in dynamischer C-MOS-Technik |
JPS61101124A (ja) * | 1984-10-24 | 1986-05-20 | Hitachi Micro Comput Eng Ltd | 半導体集積回路装置 |
US4761768A (en) * | 1985-03-04 | 1988-08-02 | Lattice Semiconductor Corporation | Programmable logic device |
KR900003591B1 (ko) * | 1985-04-08 | 1990-05-26 | 가부시기 가이샤 히다찌 세이사꾸쇼 | 데이터 처리장치 |
US4764691A (en) * | 1985-10-15 | 1988-08-16 | American Microsystems, Inc. | CMOS programmable logic array using NOR gates for clocking |
US4841174A (en) * | 1985-10-21 | 1989-06-20 | Western Digital Corporation | CMOS circuit with racefree single clock dynamic logic |
US4740721A (en) * | 1985-10-21 | 1988-04-26 | Western Digital Corporation | Programmable logic array with single clock dynamic logic |
JPH0193927A (ja) * | 1987-10-06 | 1989-04-12 | Fujitsu Ltd | プログラム可能な論理回路 |
FR2654881B1 (fr) * | 1989-11-23 | 1994-10-14 | Sgs Thomson Microelectronics | Reseau logique programmable en technologie cmos. |
US5235221A (en) * | 1992-04-08 | 1993-08-10 | Micron Technology, Inc. | Field programmable logic array with speed optimized architecture |
US5287017A (en) * | 1992-05-15 | 1994-02-15 | Micron Technology, Inc. | Programmable logic device macrocell with two OR array inputs |
US5384500A (en) * | 1992-05-15 | 1995-01-24 | Micron Semiconductor, Inc. | Programmable logic device macrocell with an exclusive feedback and an exclusive external input line for a combinatorial mode and accommodating two separate programmable or planes |
US5300830A (en) * | 1992-05-15 | 1994-04-05 | Micron Semiconductor, Inc. | Programmable logic device macrocell with an exclusive feedback and exclusive external input lines for registered and combinatorial modes using a dedicated product term for control |
US5220215A (en) * | 1992-05-15 | 1993-06-15 | Micron Technology, Inc. | Field programmable logic array with two or planes |
US5331227A (en) * | 1992-05-15 | 1994-07-19 | Micron Semiconductor, Inc. | Programmable logic device macrocell with an exclusive feedback line and an exclusive external input line |
US5298803A (en) * | 1992-07-15 | 1994-03-29 | Micron Semiconductor, Inc. | Programmable logic device having low power microcells with selectable registered and combinatorial output signals |
US5446401A (en) * | 1994-03-13 | 1995-08-29 | Advanced Micro Devices, Inc. | Synchronous dual word decoding using PLA |
US8438522B1 (en) | 2008-09-24 | 2013-05-07 | Iowa State University Research Foundation, Inc. | Logic element architecture for generic logic chains in programmable devices |
US8661394B1 (en) | 2008-09-24 | 2014-02-25 | Iowa State University Research Foundation, Inc. | Depth-optimal mapping of logic chains in reconfigurable fabrics |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3566153A (en) * | 1969-04-30 | 1971-02-23 | Texas Instruments Inc | Programmable sequential logic |
US3816725A (en) * | 1972-04-28 | 1974-06-11 | Gen Electric | Multiple level associative logic circuits |
US3866186A (en) * | 1972-05-16 | 1975-02-11 | Tokyo Shibaura Electric Co | Logic circuit arrangement employing insulated gate field effect transistors |
US3924243A (en) * | 1974-08-06 | 1975-12-02 | Ibm | Cross-field-partitioning in array logic modules |
-
1975
- 1975-09-25 IT IT27626/75A patent/IT1042852B/it active
- 1975-09-26 NL NL7511377A patent/NL7511377A/xx unknown
- 1975-09-26 GB GB39443/75A patent/GB1528187A/en not_active Expired
- 1975-09-29 US US05/617,963 patent/US3974366A/en not_active Expired - Lifetime
- 1975-09-29 FR FR7529740A patent/FR2286559A1/fr active Granted
- 1975-09-30 BE BE160551A patent/BE834024A/xx not_active IP Right Cessation
- 1975-09-30 JP JP50118219A patent/JPS6029254B2/ja not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2131584A (en) * | 1982-12-08 | 1984-06-20 | Western Electric Co | Programmed logic array |
Also Published As
Publication number | Publication date |
---|---|
FR2286559B1 (pt-PT) | 1977-12-16 |
DE2446654B2 (de) | 1976-12-16 |
NL7511377A (nl) | 1976-04-01 |
US3974366A (en) | 1976-08-10 |
JPS5161256A (en) | 1976-05-27 |
DE2446654A1 (de) | 1976-04-01 |
FR2286559A1 (fr) | 1976-04-23 |
JPS6029254B2 (ja) | 1985-07-09 |
BE834024A (fr) | 1976-01-16 |
IT1042852B (it) | 1980-01-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed [section 19, patents act 1949] | ||
PCNP | Patent ceased through non-payment of renewal fee |