GB1494905A - Zener diodes - Google Patents

Zener diodes

Info

Publication number
GB1494905A
GB1494905A GB5168374A GB5168374A GB1494905A GB 1494905 A GB1494905 A GB 1494905A GB 5168374 A GB5168374 A GB 5168374A GB 5168374 A GB5168374 A GB 5168374A GB 1494905 A GB1494905 A GB 1494905A
Authority
GB
United Kingdom
Prior art keywords
wafers
layer
semi
molybdenum
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5168374A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silec Semi Conducteurs SA
Original Assignee
Silec Semi Conducteurs SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silec Semi Conducteurs SA filed Critical Silec Semi Conducteurs SA
Publication of GB1494905A publication Critical patent/GB1494905A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
    • H01J37/305—Electron-beam or ion-beam tubes for localised treatment of objects for casting, melting, evaporating or etching
    • H01J37/3053—Electron-beam or ion-beam tubes for localised treatment of objects for casting, melting, evaporating or etching for evaporating or etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H01L21/02661—In-situ cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Analytical Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)

Abstract

1494905 Semi-conductor device manufacture SILEC-SEMI-CONDUCTEURS 28 Nov 1974 [28 Nov 1973] 51683/74 Heading H1K In the manufacture of a Zener or avalanche breakdown diode involving sequentially coating a semi-conductor substrate with a layer of heavily doped semi-conductor material and at least one layer of metallization all the layers are deposited by ionic sputtering of target materials in a vacuum which is maintained during and between formation of the individual layers. As described 200 ohm cm. P-type silicon wafers are cleared as by etching followed by washing in aqueous and organic solvents and introduced into a sputtering apparatus the details of which are described with reference to Figs. 3 and 4 (not shown). Then with the wafers heated to above 400‹ C. adsorbed impurities are removed by bombardment with an argon ion beam first from the targets and then from the wafers to provide a dislocation free surface. The wafers are then raised to 900‹ C. and an N + layer 1000-1500 Š thick deposited thereon by directing the beam on an arsenic or antimony-doped silicon target. With the wafers at room temperature the beam is directed successively on molybdenum and nickel targets to form layers of molybdenum and nickel respectively 1000 A and 2 Á thick and optionally an intermediate layer of graded composition. After inverting the wafers automatically, or after breaking the vacuum, manually a P + layer of boron-doped silicon and contact layers of molybdenum and nickel are deposited similarly on their back faces.
GB5168374A 1973-11-28 1974-11-28 Zener diodes Expired GB1494905A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7342381A FR2252652B1 (en) 1973-11-28 1973-11-28

Publications (1)

Publication Number Publication Date
GB1494905A true GB1494905A (en) 1977-12-14

Family

ID=9128391

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5168374A Expired GB1494905A (en) 1973-11-28 1974-11-28 Zener diodes

Country Status (5)

Country Link
BE (1) BE821877A (en)
DE (1) DE2456129A1 (en)
FR (1) FR2252652B1 (en)
GB (1) GB1494905A (en)
IT (1) IT1025714B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3310044A1 (en) * 1983-03-19 1984-09-20 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt METHOD AND ARRANGEMENT FOR COATING A SUBSTRATE
EP1096576A1 (en) * 1999-10-27 2001-05-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3310044A1 (en) * 1983-03-19 1984-09-20 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt METHOD AND ARRANGEMENT FOR COATING A SUBSTRATE
EP1096576A1 (en) * 1999-10-27 2001-05-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US6614087B1 (en) 1999-10-27 2003-09-02 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

Also Published As

Publication number Publication date
IT1025714B (en) 1978-08-30
DE2456129A1 (en) 1975-06-05
FR2252652A1 (en) 1975-06-20
BE821877A (en) 1975-05-05
FR2252652B1 (en) 1977-06-10

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee