IT1025714B - ZENER DIODE WITH IMPROVED THRESHOLD VOLTAGE AND REDUCED ELECTRICAL NOISE AND PROCEDURE FOR ITS FABERICAATION - Google Patents
ZENER DIODE WITH IMPROVED THRESHOLD VOLTAGE AND REDUCED ELECTRICAL NOISE AND PROCEDURE FOR ITS FABERICAATIONInfo
- Publication number
- IT1025714B IT1025714B IT2945374A IT2945374A IT1025714B IT 1025714 B IT1025714 B IT 1025714B IT 2945374 A IT2945374 A IT 2945374A IT 2945374 A IT2945374 A IT 2945374A IT 1025714 B IT1025714 B IT 1025714B
- Authority
- IT
- Italy
- Prior art keywords
- wafers
- layer
- semi
- molybdenum
- layers
- Prior art date
Links
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract 6
- 235000012431 wafers Nutrition 0.000 abstract 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 3
- 229910052750 molybdenum Inorganic materials 0.000 abstract 3
- 239000011733 molybdenum Substances 0.000 abstract 3
- 229910052759 nickel Inorganic materials 0.000 abstract 3
- 239000004065 semiconductor Substances 0.000 abstract 3
- 229910052710 silicon Inorganic materials 0.000 abstract 3
- 239000010703 silicon Substances 0.000 abstract 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 238000004544 sputter deposition Methods 0.000 abstract 2
- 239000003125 aqueous solvent Substances 0.000 abstract 1
- 229910052786 argon Inorganic materials 0.000 abstract 1
- 229910052785 arsenic Inorganic materials 0.000 abstract 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 238000010884 ion-beam technique Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 238000001465 metallisation Methods 0.000 abstract 1
- 239000000203 mixture Substances 0.000 abstract 1
- 239000003960 organic solvent Substances 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 239000013077 target material Substances 0.000 abstract 1
- 238000005406 washing Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
- H01J37/305—Electron-beam or ion-beam tubes for localised treatment of objects for casting, melting, evaporating or etching
- H01J37/3053—Electron-beam or ion-beam tubes for localised treatment of objects for casting, melting, evaporating or etching for evaporating or etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
- H01L21/02661—In-situ cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Plasma & Fusion (AREA)
- Analytical Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
1494905 Semi-conductor device manufacture SILEC-SEMI-CONDUCTEURS 28 Nov 1974 [28 Nov 1973] 51683/74 Heading H1K In the manufacture of a Zener or avalanche breakdown diode involving sequentially coating a semi-conductor substrate with a layer of heavily doped semi-conductor material and at least one layer of metallization all the layers are deposited by ionic sputtering of target materials in a vacuum which is maintained during and between formation of the individual layers. As described 200 ohm cm. P-type silicon wafers are cleared as by etching followed by washing in aqueous and organic solvents and introduced into a sputtering apparatus the details of which are described with reference to Figs. 3 and 4 (not shown). Then with the wafers heated to above 400‹ C. adsorbed impurities are removed by bombardment with an argon ion beam first from the targets and then from the wafers to provide a dislocation free surface. The wafers are then raised to 900‹ C. and an N + layer 1000-1500 Š thick deposited thereon by directing the beam on an arsenic or antimony-doped silicon target. With the wafers at room temperature the beam is directed successively on molybdenum and nickel targets to form layers of molybdenum and nickel respectively 1000 A and 2 Á thick and optionally an intermediate layer of graded composition. After inverting the wafers automatically, or after breaking the vacuum, manually a P + layer of boron-doped silicon and contact layers of molybdenum and nickel are deposited similarly on their back faces.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7342381A FR2252652B1 (en) | 1973-11-28 | 1973-11-28 |
Publications (1)
Publication Number | Publication Date |
---|---|
IT1025714B true IT1025714B (en) | 1978-08-30 |
Family
ID=9128391
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT2945374A IT1025714B (en) | 1973-11-28 | 1974-11-14 | ZENER DIODE WITH IMPROVED THRESHOLD VOLTAGE AND REDUCED ELECTRICAL NOISE AND PROCEDURE FOR ITS FABERICAATION |
Country Status (5)
Country | Link |
---|---|
BE (1) | BE821877A (en) |
DE (1) | DE2456129A1 (en) |
FR (1) | FR2252652B1 (en) |
GB (1) | GB1494905A (en) |
IT (1) | IT1025714B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3310044A1 (en) * | 1983-03-19 | 1984-09-20 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | METHOD AND ARRANGEMENT FOR COATING A SUBSTRATE |
JP4129106B2 (en) * | 1999-10-27 | 2008-08-06 | 三菱電機株式会社 | Semiconductor device |
-
1973
- 1973-11-28 FR FR7342381A patent/FR2252652B1/fr not_active Expired
-
1974
- 1974-11-05 BE BE150231A patent/BE821877A/en unknown
- 1974-11-14 IT IT2945374A patent/IT1025714B/en active
- 1974-11-27 DE DE19742456129 patent/DE2456129A1/en active Pending
- 1974-11-28 GB GB5168374A patent/GB1494905A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE2456129A1 (en) | 1975-06-05 |
BE821877A (en) | 1975-05-05 |
GB1494905A (en) | 1977-12-14 |
FR2252652A1 (en) | 1975-06-20 |
FR2252652B1 (en) | 1977-06-10 |
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