GB1470851A - Fail-safe timing circuit - Google Patents

Abstract

1470851 Transistor switching circuits SIE SOC ITALIANA ELETTRONICA SpA 14 May 1974 [30 May 1973] 21212/74 Heading H3T A delayed switching circuit comprises energy storage means 8 which can be charged to a predetermined level, means for discharging it in a modulated, e.g. stepwise, manner and means responsive to the discharge to produce an output. In a first embodiment, Fig. 2, when switch J is open transistors Q1, Q2 are alternately switched on and off by a pulse train at Y to cause capacitor 8 to charge and discharge. The resulting pulse signal is fed via transistors Q3, Q4 and transformer T to hold relay R energized. When switch J is closed transistor Q1 is held off and capacitor 8 cannot recharge. The input pulse signal will now cause it to discharge in a stepwise fashion until, after the required delay period, no more pulses are fed via transformer T and relay R releases to produce an output. In a second embodiment, Fig. 4, a pulse input signal switching between the two levels + 15 v. and 0 v. is applied to point X and the circuit gives an indication if the signal remains at one or other level for more than a predetermined time. When the input is at the 0 v. level transistor Q1 is on and capacitor 6 charges cutting Q3, Q4 off. Initially relay R is held energized by a charge previously given to capacitor 15, but if this state is maintained for more than the predetermined time the charge leaks away to release the relay R closing contacts R1. When the signal switches to +15 v., transistor Q2 is pulsed by the squarewave signal applied at W to discharge capacitor 6 in a stepwise manner. This provides the pulses which charge capacitor 15 and hold on relay R. If this state is maintained for more than a second predetermined time, capacitor 6 becomes discharged, the pulse from to capacitor 15 ceases, and this capacitor in turn discharges to again release relay R.