GB1411864A - Method of manufacturing an interconnection pattern - Google Patents

Method of manufacturing an interconnection pattern

Info

Publication number
GB1411864A
GB1411864A GB3278373A GB3278373A GB1411864A GB 1411864 A GB1411864 A GB 1411864A GB 3278373 A GB3278373 A GB 3278373A GB 3278373 A GB3278373 A GB 3278373A GB 1411864 A GB1411864 A GB 1411864A
Authority
GB
United Kingdom
Prior art keywords
coating
protective
contact
july
contacts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3278373A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
ITT Inc
Original Assignee
Deutsche ITT Industries GmbH
ITT Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH, ITT Industries Inc filed Critical Deutsche ITT Industries GmbH
Publication of GB1411864A publication Critical patent/GB1411864A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
GB3278373A 1972-07-21 1973-07-10 Method of manufacturing an interconnection pattern Expired GB1411864A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19722235749 DE2235749C3 (de) 1972-07-21 1972-07-21 Verfahren zum Herstellen eines Leitbahnenmusters

Publications (1)

Publication Number Publication Date
GB1411864A true GB1411864A (en) 1975-10-29

Family

ID=5851230

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3278373A Expired GB1411864A (en) 1972-07-21 1973-07-10 Method of manufacturing an interconnection pattern

Country Status (6)

Country Link
JP (1) JPS5734647B2 (it)
AU (1) AU5795273A (it)
DE (1) DE2235749C3 (it)
FR (1) FR2194046B1 (it)
GB (1) GB1411864A (it)
IT (1) IT991124B (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4076575A (en) * 1976-06-30 1978-02-28 International Business Machines Corporation Integrated fabrication method of forming connectors through insulative layers
JPS55163860A (en) * 1979-06-06 1980-12-20 Toshiba Corp Manufacture of semiconductor device
DE3109801A1 (de) * 1981-03-13 1982-09-30 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von halbleiterbauelementen
JPS60153122A (ja) * 1984-01-20 1985-08-12 Matsushita Electronics Corp 半導体装置の製造方法
CN107068546B (zh) * 2015-11-06 2022-05-24 马维尔以色列(M.I.S.L.)有限公司 生产用于多功能产品的半导体晶片的方法

Also Published As

Publication number Publication date
AU5795273A (en) 1975-01-16
JPS4980973A (it) 1974-08-05
DE2235749B2 (de) 1978-12-14
DE2235749C3 (de) 1979-09-20
FR2194046A1 (it) 1974-02-22
FR2194046B1 (it) 1977-02-18
DE2235749A1 (de) 1974-01-31
JPS5734647B2 (it) 1982-07-24
IT991124B (it) 1975-07-30

Similar Documents

Publication Publication Date Title
US4209349A (en) Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching
US3966514A (en) Method for forming dielectric isolation combining dielectric deposition and thermal oxidation
US4305760A (en) Polysilicon-to-substrate contact processing
GB1208574A (en) Methods of manufacturing semiconductor devices
GB1222898A (en) Improvements in and relating to methods of manufacturing semiconductor devices
JPS5850015B2 (ja) 半導体装置の製造方法
US3184823A (en) Method of making silicon transistors
US3730778A (en) Methods of manufacturing a semiconductor device
US3489961A (en) Mesa etching for isolation of functional elements in integrated circuits
US3728784A (en) Fabrication of semiconductor devices
US4146413A (en) Method of producing a P-N junction utilizing polycrystalline silicon
GB1515639A (en) Integrated circuits
GB1418969A (en) Method of making integrated circuits
US4363830A (en) Method of forming tapered contact holes for integrated circuit devices
US3808058A (en) Fabrication of mesa diode with channel guard
GB967002A (en) Improvements in or relating to semiconductor devices
GB1411864A (en) Method of manufacturing an interconnection pattern
US3681147A (en) Method for masking semiconductor regions for ion implantation
US3681153A (en) Process for fabricating small geometry high frequency semiconductor device
US3447984A (en) Method for forming sharply defined apertures in an insulating layer
US3764410A (en) Method of making ultra fine geometry planar semiconductor devices
US3592707A (en) Precision masking using silicon nitride and silicon oxide
US3817750A (en) Method of producing a semiconductor device
US3996077A (en) Method of manufacturing a semiconductor device having an insulation layer sunk in a semiconductor body and semiconductor device manufactured according to said method
JPS5745947A (en) Mos type semiconductor integrated circuit

Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee