AU5795273A - Method of manufacturing an interconnection pattern - Google Patents
Method of manufacturing an interconnection patternInfo
- Publication number
- AU5795273A AU5795273A AU57952/73A AU5795273A AU5795273A AU 5795273 A AU5795273 A AU 5795273A AU 57952/73 A AU57952/73 A AU 57952/73A AU 5795273 A AU5795273 A AU 5795273A AU 5795273 A AU5795273 A AU 5795273A
- Authority
- AU
- Australia
- Prior art keywords
- manufacturing
- interconnection pattern
- interconnection
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DEDE822357 | 1972-07-21 | ||
DE19722235749 DE2235749C3 (de) | 1972-07-21 | 1972-07-21 | Verfahren zum Herstellen eines Leitbahnenmusters |
Publications (1)
Publication Number | Publication Date |
---|---|
AU5795273A true AU5795273A (en) | 1975-01-16 |
Family
ID=5851230
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU57952/73A Expired AU5795273A (en) | 1972-07-21 | 1973-07-10 | Method of manufacturing an interconnection pattern |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS5734647B2 (it) |
AU (1) | AU5795273A (it) |
DE (1) | DE2235749C3 (it) |
FR (1) | FR2194046B1 (it) |
GB (1) | GB1411864A (it) |
IT (1) | IT991124B (it) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4076575A (en) * | 1976-06-30 | 1978-02-28 | International Business Machines Corporation | Integrated fabrication method of forming connectors through insulative layers |
JPS55163860A (en) * | 1979-06-06 | 1980-12-20 | Toshiba Corp | Manufacture of semiconductor device |
DE3109801A1 (de) * | 1981-03-13 | 1982-09-30 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von halbleiterbauelementen |
JPS60153122A (ja) * | 1984-01-20 | 1985-08-12 | Matsushita Electronics Corp | 半導体装置の製造方法 |
US9865503B2 (en) * | 2015-11-06 | 2018-01-09 | Marvell Israel (M.I.S.L) Ltd. | Method to produce a semiconductor wafer for versatile products |
-
1972
- 1972-07-21 DE DE19722235749 patent/DE2235749C3/de not_active Expired
-
1973
- 1973-07-10 GB GB3278373A patent/GB1411864A/en not_active Expired
- 1973-07-10 AU AU57952/73A patent/AU5795273A/en not_active Expired
- 1973-07-11 IT IT2644173A patent/IT991124B/it active
- 1973-07-17 FR FR7326105A patent/FR2194046B1/fr not_active Expired
- 1973-07-20 JP JP8259673A patent/JPS5734647B2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
IT991124B (it) | 1975-07-30 |
DE2235749B2 (de) | 1978-12-14 |
JPS4980973A (it) | 1974-08-05 |
DE2235749A1 (de) | 1974-01-31 |
FR2194046A1 (it) | 1974-02-22 |
DE2235749C3 (de) | 1979-09-20 |
GB1411864A (en) | 1975-10-29 |
FR2194046B1 (it) | 1977-02-18 |
JPS5734647B2 (it) | 1982-07-24 |
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