IT991124B - Metodo di fabbricazione di un tracciato di interconnessioni - Google Patents

Metodo di fabbricazione di un tracciato di interconnessioni

Info

Publication number
IT991124B
IT991124B IT2644173A IT2644173A IT991124B IT 991124 B IT991124 B IT 991124B IT 2644173 A IT2644173 A IT 2644173A IT 2644173 A IT2644173 A IT 2644173A IT 991124 B IT991124 B IT 991124B
Authority
IT
Italy
Prior art keywords
manufacturing
interconnection track
interconnection
track
Prior art date
Application number
IT2644173A
Other languages
English (en)
Original Assignee
Itt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Itt filed Critical Itt
Application granted granted Critical
Publication of IT991124B publication Critical patent/IT991124B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291Oxides or nitrides or carbides, e.g. ceramics, glass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
IT2644173A 1972-07-21 1973-07-11 Metodo di fabbricazione di un tracciato di interconnessioni IT991124B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19722235749 DE2235749C3 (de) 1972-07-21 1972-07-21 Verfahren zum Herstellen eines Leitbahnenmusters

Publications (1)

Publication Number Publication Date
IT991124B true IT991124B (it) 1975-07-30

Family

ID=5851230

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2644173A IT991124B (it) 1972-07-21 1973-07-11 Metodo di fabbricazione di un tracciato di interconnessioni

Country Status (6)

Country Link
JP (1) JPS5734647B2 (it)
AU (1) AU5795273A (it)
DE (1) DE2235749C3 (it)
FR (1) FR2194046B1 (it)
GB (1) GB1411864A (it)
IT (1) IT991124B (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4076575A (en) * 1976-06-30 1978-02-28 International Business Machines Corporation Integrated fabrication method of forming connectors through insulative layers
JPS55163860A (en) * 1979-06-06 1980-12-20 Toshiba Corp Manufacture of semiconductor device
DE3109801A1 (de) * 1981-03-13 1982-09-30 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von halbleiterbauelementen
JPS60153122A (ja) * 1984-01-20 1985-08-12 Matsushita Electronics Corp 半導体装置の製造方法
CN107068546B (zh) * 2015-11-06 2022-05-24 马维尔以色列(M.I.S.L.)有限公司 生产用于多功能产品的半导体晶片的方法

Also Published As

Publication number Publication date
AU5795273A (en) 1975-01-16
DE2235749C3 (de) 1979-09-20
JPS4980973A (it) 1974-08-05
FR2194046B1 (it) 1977-02-18
DE2235749B2 (de) 1978-12-14
FR2194046A1 (it) 1974-02-22
GB1411864A (en) 1975-10-29
DE2235749A1 (de) 1974-01-31
JPS5734647B2 (it) 1982-07-24

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