GB1404524A - Method of forming interconnection leads in multilayer micro electronic devices - Google Patents

Method of forming interconnection leads in multilayer micro electronic devices

Info

Publication number
GB1404524A
GB1404524A GB3392673A GB3392673A GB1404524A GB 1404524 A GB1404524 A GB 1404524A GB 3392673 A GB3392673 A GB 3392673A GB 3392673 A GB3392673 A GB 3392673A GB 1404524 A GB1404524 A GB 1404524A
Authority
GB
United Kingdom
Prior art keywords
layer
interconnections
aluminium
masking
magnesium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3392673A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of GB1404524A publication Critical patent/GB1404524A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/467—Adding a circuit layer by thin film methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for
    • H10P95/00—

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • ing And Chemical Polishing (AREA)
  • Weting (AREA)
GB3392673A 1972-07-17 1973-07-17 Method of forming interconnection leads in multilayer micro electronic devices Expired GB1404524A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US27251972A 1972-07-17 1972-07-17

Publications (1)

Publication Number Publication Date
GB1404524A true GB1404524A (en) 1975-09-03

Family

ID=23040144

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3392673A Expired GB1404524A (en) 1972-07-17 1973-07-17 Method of forming interconnection leads in multilayer micro electronic devices

Country Status (4)

Country Link
JP (1) JPS4963966A (enExample)
FR (1) FR2193256B1 (enExample)
GB (1) GB1404524A (enExample)
NL (1) NL7309531A (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2937993A1 (de) * 1979-09-20 1981-04-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von integrierten mos-halbleiterschaltungen nach der silizium-gate-technologie
US7790624B2 (en) 2008-07-16 2010-09-07 Global Foundries Inc. Methods for removing a metal-comprising material from a semiconductor substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3507766A (en) * 1968-01-19 1970-04-21 Texas Instruments Inc Method of forming a heterogeneous composite insulating layer of silicon dioxide in multilevel integrated circuits

Also Published As

Publication number Publication date
NL7309531A (enExample) 1974-01-21
FR2193256A1 (enExample) 1974-02-15
DE2334213A1 (de) 1974-01-31
FR2193256B1 (enExample) 1978-02-17
DE2334213B2 (de) 1974-08-29
JPS4963966A (enExample) 1974-06-20

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee