GB1395991A - Electornic arrangement for the multiplication of a binary- coded number in a system having an even-numbered radix greater than 2 with a factor equal to half the radix of siad system of numbers - Google Patents

Electornic arrangement for the multiplication of a binary- coded number in a system having an even-numbered radix greater than 2 with a factor equal to half the radix of siad system of numbers

Info

Publication number
GB1395991A
GB1395991A GB3921272A GB3921272A GB1395991A GB 1395991 A GB1395991 A GB 1395991A GB 3921272 A GB3921272 A GB 3921272A GB 3921272 A GB3921272 A GB 3921272A GB 1395991 A GB1395991 A GB 1395991A
Authority
GB
United Kingdom
Prior art keywords
radix
numbers
adder
binary
electornic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3921272A
Other languages
English (en)
Inventor
D Melcher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wirth Gallo and Co
Original Assignee
Wirth Gallo and Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wirth Gallo and Co filed Critical Wirth Gallo and Co
Publication of GB1395991A publication Critical patent/GB1395991A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/4915—Multiplying; Dividing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Complex Calculations (AREA)
  • Dc Digital Transmission (AREA)
  • Logic Circuits (AREA)
  • Analogue/Digital Conversion (AREA)
  • Liquid Crystal Display Device Control (AREA)
GB3921272A 1972-05-24 1972-08-23 Electornic arrangement for the multiplication of a binary- coded number in a system having an even-numbered radix greater than 2 with a factor equal to half the radix of siad system of numbers Expired GB1395991A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH768672A CH552249A (de) 1972-05-24 1972-05-24 Elektronische vorrichtung zur multiplikation einer binaer kodierten zahl eines zahlensystemes mit geradzahliger basis groesser als 2 mit einem faktor, der gleich der haelfte der basis dieses zahlensystems ist.

Publications (1)

Publication Number Publication Date
GB1395991A true GB1395991A (en) 1975-05-29

Family

ID=4329013

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3921272A Expired GB1395991A (en) 1972-05-24 1972-08-23 Electornic arrangement for the multiplication of a binary- coded number in a system having an even-numbered radix greater than 2 with a factor equal to half the radix of siad system of numbers

Country Status (9)

Country Link
US (1) US3805042A (enExample)
JP (1) JPS4929543A (enExample)
CH (1) CH552249A (enExample)
DD (1) DD100342A5 (enExample)
DE (1) DE2239996C3 (enExample)
FR (1) FR2193505A5 (enExample)
GB (1) GB1395991A (enExample)
NL (1) NL7213082A (enExample)
SE (1) SE375168B (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3890496A (en) * 1974-04-01 1975-06-17 Sperry Rand Corp Variable 8421 BCD multiplier
JPS63288094A (ja) * 1987-05-20 1988-11-25 Matsushita Electric Ind Co Ltd セラミック多層基板及びその製造方法
US5176811A (en) * 1991-02-01 1993-01-05 International Business Machines Corporation Gold plating bath additives for copper circuitization on polyimide printed circuit boards

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL280023A (enExample) * 1961-06-23
US3456098A (en) * 1966-04-04 1969-07-15 Bell Telephone Labor Inc Serial binary multiplier arrangement
US3495075A (en) * 1966-12-13 1970-02-10 Ibm Shifting apparatus

Also Published As

Publication number Publication date
DE2239996C3 (de) 1974-08-22
US3805042A (en) 1974-04-16
NL7213082A (enExample) 1973-11-27
JPS4929543A (enExample) 1974-03-16
FR2193505A5 (enExample) 1974-02-15
SE375168B (enExample) 1975-04-07
DD100342A5 (de) 1973-09-12
CH552249A (de) 1974-07-31
DE2239996A1 (de) 1974-01-17
DE2239996B1 (de) 1974-01-17

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee