GB1523889A - Logical apparatus for multiplying serial binary operands with sign - Google Patents

Abstract

1523889 Serial binary multipliers GENERAL ELECTRIC CO 30 Oct 1975 [4 Nov 1974 22 Nov 1974] 44806/75 Heading G4A In a serial binary multiplier, a serial binary multiplier b containing magnitude information in the form of, e.g. 7-bit words is fed from a bus 31, Fig. 4, to multiplication stages 34-40, each multiplication stage containing a respective binary storage element (62), Fig. 6 (not shown) which selects a respective bit b 1 -b 7 of predetermined significance from a given word of the multiplier bit stream and stores such bit until a bit of like significance occurs in the succeeding word, a serial binary multiplicand a containing magnitude and sign information in two's complement notation being fed from a bus 32 to the input stage of a 7-bit shift register formed by respective one-bit delays (68) of the multiplication stages 34-40, the accumulated bits of delay of the shift register increasing in correspondence with the significance of the multiplier bit b 1 entered since all the bit streams occur at equal word rates with the least significant bits thereof first in time, each multiplication stage 34-40 multiplying a respective consecutive selection of the more significant bits of a word of the multiplicand a by the respective multiplier bit b i to form a serial partial product, the partial products then being consolidated into a single bit stream containing magnitude and sign information in two's complement rotation on a bus 33 by a summation network 41-47. Each multiplication stage includes means controlled by variable delay W 1 -W 7 and inverted fixed delay W 2 timing waveforms for entering less than all of the bits of the multiplicand, the least significant bits thereof being truncated in inverse relationship with the significance of the multiplier bit entered. Means are provided for infilling the higher order bits of any truncated multiplicand with sign bits each identical to the original sign bit to obtain a respective full length partial product. Each summer 41-47, of which a logic diagram is given in Figs. 8, 8a (not shown), produces a serial data output from two serial data inputs after a one-bit delay and includes means for resetting the internally stored carry bits as the least significant bit of a word passes therethrough. The final summer 47 is provided with means 50, 51 for zeroing the three least significant bits of each word of the serial binary product, thereby producing from the 13-bit product of a 7-bit multiplier b and a 12-bit multiplicand a a 10-bit truncated final product. In order to compensate for such truncation of the multiplicand and of the final product, a rounding value (6 in the present example) is introduced into the summer 44. By suitable choice of the timing waveforms the truncation of the multiplicand and final product and the introduction of a rounding value may be obviated to obtain a full double-precision final product. The output of the multiplier on bus 33 is fed to a serial two's complementer (15), Fig. 1 (not shown) so that the sign of the multiplier b is reflected in the final product. Four similar serial binary multipliers 1-4, Fig. 2, may be used to perform complex multiplication of two complex numbers a + ib, c + id, the numbers a-d being fed as shown to the inputs of the serial binary multipliers whose product outputs feed serial two's complementers 5-8, the outputs of the two's complementers 5-8 being summed in summation networks 9, 10 to obtain the complex product (ac + bd) + i(ad + bc). Each of the two's complementers (15), 5-8 may be in accordance with the logic diagram of Fig. 3 (not shown), or may be conventional. A detailed logic diagram of the multiplication stage of Fig. 6 (not shown) is given in Fig. 7 (not shown).