GB2157032A

GB2157032A - Digital parallel odder

Info

Publication number: GB2157032A
Application number: GB08408992A
Authority: GB
Inventors: Philip Joseph Elce; John Joseph Drudy
Original assignee: Standard Telephone and Cables PLC
Current assignee: STC PLC
Priority date: 1984-04-06
Filing date: 1984-04-06
Publication date: 1985-10-16
Also published as: GB8408992D0

Abstract

To add two binary numbers A & B in parallel the least significant bits of each number are added in a first sample period in adder unit 1, the output bits with carry being held in a latch 2. At the same time the most significant bits of each number are put through delays 3, 4 and added in unit 5 in a succeeding sample period, together with the carry from latch 2. The output bits in latch 2 are put through delay 6, so that they coincide with the outputs from unit 5. The input numbers are thus present for one sample period; two periods later the sum appears. Additions are performed at the full sample rate at the penalty of having the inputs delayed, whilst the internal carries have time to propagate right across the addition. <IMAGE>

Description

SPECIFICATION Digital parallel adder This invention relates to a method and apparatus for performing parallel addition of binary numbers occurring in isochronous data streams.

When two binary numbers, each represented by a number of bits, are required to be added in parallel and registered in a parallel latch, at a sample rate f,, the internal "carrys" in the addition must propagate right across the number of bits within one sample period I/f,. So-called "fast" look-ahead carry circuits are often used to speed-up this process, but still incur some delay.

According to the present invention there is provided a method of adding in a parallel form binary numbers occurring in isochronous data streams wherein the numbers are each divided into corresponding groups of bits of like significance which groups are added in parallel in separate stages operating in successive periods of time, each stage generating a carry which is applied as a carry input to the next operating stage wherein the corresponding groups of next most significance are added.

The invention also provides an apparatus for adding binary numbers occurring in isochronous data streams in parallel, including a plurality of parallel adder units each capable of adding only groups of bits which group each forms part only of a binary number, means for operating the adder units in successive periods of time, means for applying to the adder units in said successive periods of time corresponding groups of bits from the binary numbers such that successive groups applied in successive periods of time have increasing significance, and means for applying a carry from each adder unit as a carry input to the succeeding adder unit.

Embodiments of the invention will now be described with reference to the accompanying drawing which illustrates in schematic form an arrangement for parallel addition of two 8-bit binary numbers.

In the arrangement illustrated two eight-bit binary numbers A and B are presented in parallel for addition, the sum to be registered in a parallel latch. The sample rate of the system is f, and the carrys are required to be propagated right across the addition within one sample period (I/f,). However, provided that the delay incurred by each partial addition can be less than one sample period the additions of successive pairs of numbers can be performed at the sample rate f,.

The four least significant bits of each number A and B are presented, in a first sample period, for parallel addition in a 4-bit adder 1 with a carry output. The 4-bit plus carry outputs from adder 1 are put into a 5-bit latch 2. At the same time the four most significant bits of the two numbers A and B are put into skewing delays 3, 4 where they are delayed for one sample period. In the second sample period the outputs from delays 3 and 4 are presented to a second 4-bit adder 5, together with the carry output from latch 2. At the same time the sum outputs held in latch 2 are put into a linearising delay 6. Meanwhile, also in the second sample period, two new 8-bit numbers are presented for addition, and the four least significant bits of each going into adder 1 and the four most significant bits of each going into the delays 3 & 4.At the end of the second sample period the 8-bit sum of the first two numbers A & B is available, the four least significant bits coming from the linearising delay 6 and the four most significant bits from adder 5.

In the example given above the 8-bit inputs are present for one sample period and two periods later the 8- bit output appears, but new inputs are presented at the full sample rate and the resulting new outputs are calculated at the full sample rate f,.

The skewing delays 3 & 4 and the linearising delay 6 are required where the inputs are presented simultaneously in parallel. However, if the inputs, although in parallel form, are presented staggered in time, then no skewing delays may be required.

Similarly, if staggered outputs can be used for subsequent processing, then the linearising output delays can be eliminated.

Whilst the example given above refers only to the division of 8-bit numbers into two 4-bit groups, other arrangements can be contemplated within the scope of the invention. Thus, the input binary words can consist of larger or smaller numbers of bits and can be divided into greater or lesser groups, A 16-bit word can be divided in four 4-bit groups, the addition sum appearing after four sample periods. Conversely 8-bit input numbers can be divided into eight 1-bit groups, with the output appearing as eight parallel staggered bits over eight successive sample periods. This latter example has a useful application when successively summed pairs of numbers are required to be accumulated.

Alternatively, the second number to be added can be the sum of the previous addition. In this case the groups of bits forming the second number are already produced in a staggered or skewed form.

Thus only the group of the first number need to be put through skewing delays. The latch outputs are linearised as before for use by succeeding circuitry.

This is a particularly useful form of accumulation for certain digital-to-analogue conversion arrangements in the field of speech transmission.

Claims

1. A method of adding in a parallel form binary numbers occurring in isochronous data streams wherein the numbers are each divided into corresponding groups of bits of like significance which groups are added in parallel in separate stages operating in successive period of time, each stage generating a carry which is applied as a carry input to the next operating stage wherein the corresponding groups of next most significance are added.

2. A method according to claim 1 wherein the bits in each of said numbers to be added are presented simultaneously and groups of greater sig nificance are delayed before addition in said successive stages, likewise the outputs of separate stages adding groups of lesser significance are delayed whereby carry outputs from the stages adding lesser significance groups are aligned in time with the delayed greater significance bits input to the succeeding stages and the outputs of all the stages are aligned in time.

3. A method according to claim 1 wherein the groups of bits in each of the said numbers to be added are presented sequentially in successive period of time whereby the bits of the addition output are generated in corresponding later successive periods of time.

4. A method according to claim 1, 2 or 3 wherein the binary numbers to be added are each comprised of an even number of bits and said groups into which said binary numbers are divided each comprise half the bits in a binary number.

5. A method according to claim 1, 2 or 3 wherein the groups into which said binary numbers are divided each comprise one bit only.

6. A method according to claim 1 wherein the bits in one of the numbers to be added are the outputs from the successive stages resulting from a preceding addition and are presented in successive periods of time and the bits of the other number to be added are presented simultaneously in parallel, the groups of the other number being delayed to be input to the stages in the same time periods as the groups of corresponding significance of the one number resulting from the previous addition.

7. A method of adding in parallel form binary numbers substanially as hereinbefore described.

8. An apparatus for adding binary numbers occurring in isochronous data streams in parallel, including a plurality of parallel adder units each capable of adding only groups of bits which group each forms part only of a binary number, means for operating the adder units in successive periods of time, means for applying to the adder units in said successive periods of time corresponding groups of bits from the binary numbers such that successive groups applied in successive periods of time have increasing significance, and means for applying a carry from each adder unit as a carry input to the succeeding adder unit.

9. Apparatus according to claim 8 wherein the bits of said numbers to be added are presented simultaneously, the apparatus including means for delaying successive groups of bits of increasing significance by successive periods of time whereby said delayed groups are presented for addition in respective stages in the periods in which said stages are operative for adding said groups, and means for delaying the outputs of stages wherein groups of lesser significance are added whereby carry outputs from said stages are presented to succeeding stages together with the delayed input groups of greater significance.

10. Apparatus according to claim 8 or 9 wherein the binary numbers to be added each comprise an even number of bits and said groups into which said binary numbers are divided each comprise half the bits in a binary number.

11. Apparatus according to claim 8 or 9 wherein the groups into which said binary numbers are divided each comprise one bit only.

12. Apparatus for adding binary numbers substantially as described with reference to the accompanying drawings.